pinctrl: stm32: Implement .pin_config_dbg_show()
Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Patrice Chotard
Linus Walleij
Родитель
caee57ec71
Коммит
3beed93c16
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@ -454,6 +454,29 @@ static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
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clk_disable(bank->clk);
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}
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static void stm32_pmx_get_mode(struct stm32_gpio_bank *bank,
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int pin, u32 *mode, u32 *alt)
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{
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u32 val;
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int alt_shift = (pin % 8) * 4;
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int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
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unsigned long flags;
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clk_enable(bank->clk);
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spin_lock_irqsave(&bank->lock, flags);
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val = readl_relaxed(bank->base + alt_offset);
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val &= GENMASK(alt_shift + 3, alt_shift);
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*alt = val >> alt_shift;
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val = readl_relaxed(bank->base + STM32_GPIO_MODER);
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val &= GENMASK(pin * 2 + 1, pin * 2);
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*mode = val >> (pin * 2);
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spin_unlock_irqrestore(&bank->lock, flags);
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clk_disable(bank->clk);
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}
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static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
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unsigned function,
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unsigned group)
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@ -525,6 +548,24 @@ static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
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clk_disable(bank->clk);
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}
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static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
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unsigned int offset)
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{
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unsigned long flags;
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u32 val;
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clk_enable(bank->clk);
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spin_lock_irqsave(&bank->lock, flags);
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val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
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val &= BIT(offset);
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spin_unlock_irqrestore(&bank->lock, flags);
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clk_disable(bank->clk);
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return (val >> offset);
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}
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static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
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unsigned offset, u32 speed)
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{
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@ -543,6 +584,24 @@ static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
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clk_disable(bank->clk);
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}
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static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
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unsigned int offset)
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{
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unsigned long flags;
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u32 val;
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clk_enable(bank->clk);
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spin_lock_irqsave(&bank->lock, flags);
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val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
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val &= GENMASK(offset * 2 + 1, offset * 2);
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spin_unlock_irqrestore(&bank->lock, flags);
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clk_disable(bank->clk);
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return (val >> (offset * 2));
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}
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static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
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unsigned offset, u32 bias)
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{
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@ -561,6 +620,57 @@ static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
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clk_disable(bank->clk);
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}
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static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
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unsigned int offset)
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{
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unsigned long flags;
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u32 val;
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clk_enable(bank->clk);
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spin_lock_irqsave(&bank->lock, flags);
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val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
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val &= GENMASK(offset * 2 + 1, offset * 2);
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spin_unlock_irqrestore(&bank->lock, flags);
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clk_disable(bank->clk);
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return (val >> (offset * 2));
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}
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static bool stm32_pconf_input_get(struct stm32_gpio_bank *bank,
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unsigned int offset)
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{
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unsigned long flags;
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u32 val;
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clk_enable(bank->clk);
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spin_lock_irqsave(&bank->lock, flags);
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val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
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spin_unlock_irqrestore(&bank->lock, flags);
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clk_disable(bank->clk);
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return val;
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}
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static bool stm32_pconf_output_get(struct stm32_gpio_bank *bank,
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unsigned int offset)
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{
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unsigned long flags;
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u32 val;
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clk_enable(bank->clk);
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spin_lock_irqsave(&bank->lock, flags);
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val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & BIT(offset));
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spin_unlock_irqrestore(&bank->lock, flags);
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clk_disable(bank->clk);
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return val;
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}
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static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
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unsigned int pin, enum pin_config_param param,
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enum pin_config_param arg)
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@ -634,9 +744,73 @@ static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
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return 0;
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}
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static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
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struct seq_file *s,
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unsigned int pin)
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{
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struct pinctrl_gpio_range *range;
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struct stm32_gpio_bank *bank;
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int offset;
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u32 mode, alt, drive, speed, bias;
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static const char * const modes[] = {
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"input", "output", "alternate", "analog" };
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static const char * const speeds[] = {
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"low", "medium", "high", "very high" };
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static const char * const biasing[] = {
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"floating", "pull up", "pull down", "" };
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bool val;
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range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
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bank = gpio_range_to_bank(range);
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offset = stm32_gpio_pin(pin);
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stm32_pmx_get_mode(bank, offset, &mode, &alt);
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bias = stm32_pconf_get_bias(bank, offset);
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seq_printf(s, "%s ", modes[mode]);
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switch (mode) {
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/* input */
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case 0:
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val = stm32_pconf_input_get(bank, offset);
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seq_printf(s, "- %s - %s",
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val ? "high" : "low",
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biasing[bias]);
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break;
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/* output */
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case 1:
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drive = stm32_pconf_get_driving(bank, offset);
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speed = stm32_pconf_get_speed(bank, offset);
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val = stm32_pconf_output_get(bank, offset);
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seq_printf(s, "- %s - %s - %s - %s %s",
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val ? "high" : "low",
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drive ? "open drain" : "push pull",
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biasing[bias],
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speeds[speed], "speed");
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break;
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/* alternate */
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case 2:
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drive = stm32_pconf_get_driving(bank, offset);
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speed = stm32_pconf_get_speed(bank, offset);
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seq_printf(s, "%d - %s -%s", alt,
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drive ? "open drain" : "push pull",
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biasing[bias],
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speeds[speed], "speed");
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break;
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/* analog */
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case 3:
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break;
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}
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}
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static const struct pinconf_ops stm32_pconf_ops = {
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.pin_config_group_get = stm32_pconf_group_get,
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.pin_config_group_set = stm32_pconf_group_set,
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.pin_config_dbg_show = stm32_pconf_dbg_show,
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};
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static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
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