perf/x86/amd: Fix AMD BRS period adjustment
There's two problems with the current amd_brs_adjust_period() code:
- it isn't in fact AMD specific and wil always adjust the period;
- it adjusts the period, while it should only adjust the event count,
resulting in repoting a short period.
Fix this by using x86_pmu.limit_period, this makes it specific to the
AMD BRS case and ensures only the event count is adjusted while the
reported period is unmodified.
Fixes: ba2fe75008
("perf/x86/amd: Add AMD branch sampling period adjustment")
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
This commit is contained in:
Родитель
bc469ddf67
Коммит
3c27b0c6ea
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@ -1255,6 +1255,18 @@ static void amd_pmu_sched_task(struct perf_event_context *ctx,
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amd_pmu_brs_sched_task(ctx, sched_in);
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}
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static u64 amd_pmu_limit_period(struct perf_event *event, u64 left)
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{
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/*
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* Decrease period by the depth of the BRS feature to get the last N
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* taken branches and approximate the desired period
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*/
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if (has_branch_stack(event) && left > x86_pmu.lbr_nr)
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left -= x86_pmu.lbr_nr;
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return left;
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}
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static __initconst const struct x86_pmu amd_pmu = {
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.name = "AMD",
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.handle_irq = amd_pmu_handle_irq,
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@ -1415,6 +1427,7 @@ static int __init amd_core_pmu_init(void)
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if (boot_cpu_data.x86 >= 0x19 && !amd_brs_init()) {
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x86_pmu.get_event_constraints = amd_get_event_constraints_f19h;
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x86_pmu.sched_task = amd_pmu_sched_task;
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x86_pmu.limit_period = amd_pmu_limit_period;
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/*
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* put_event_constraints callback same as Fam17h, set above
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*/
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@ -1374,13 +1374,6 @@ int x86_perf_event_set_period(struct perf_event *event)
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x86_pmu.set_topdown_event_period)
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return x86_pmu.set_topdown_event_period(event);
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/*
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* decrease period by the depth of the BRS feature to get
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* the last N taken branches and approximate the desired period
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*/
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if (has_branch_stack(event))
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period = amd_brs_adjust_period(period);
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/*
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* If we are way outside a reasonable range then just skip forward:
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*/
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@ -1254,14 +1254,6 @@ static inline void amd_pmu_brs_del(struct perf_event *event)
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}
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void amd_pmu_brs_sched_task(struct perf_event_context *ctx, bool sched_in);
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static inline s64 amd_brs_adjust_period(s64 period)
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{
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if (period > x86_pmu.lbr_nr)
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return period - x86_pmu.lbr_nr;
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return period;
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}
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#else
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static inline int amd_brs_init(void)
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{
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@ -1290,11 +1282,6 @@ static inline void amd_pmu_brs_sched_task(struct perf_event_context *ctx, bool s
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{
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}
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static inline s64 amd_brs_adjust_period(s64 period)
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{
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return period;
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}
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static inline void amd_brs_enable_all(void)
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{
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}
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@ -1324,11 +1311,6 @@ static inline void amd_brs_enable_all(void)
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static inline void amd_brs_disable_all(void)
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{
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}
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static inline s64 amd_brs_adjust_period(s64 period)
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{
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return period;
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}
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#endif /* CONFIG_CPU_SUP_AMD */
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static inline int is_pebs_pt(struct perf_event *event)
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