Qualcomm ARM64 fixes for v6.5
This corrects the invalid path specifier for L3 interconnects in the CPU nodes of SM8150 and SM8250. It corrects the compatible of the SC8180X L3 node, to pass the binding check. The crypto core, and its DMA controller, is disabled on SM8350 to avoid the system from crashing at boot while the issue is diagnosed. A thermal zone node name conflict is resolved for PM8150L, on the RB5 board. The UFS vccq voltage is corrected on the SA877P Ride platform, to address observed stability issues. The reg-names of the DSI phy on SC7180 are restored after an accidental search-and-replace update. -----BEGIN PGP SIGNATURE----- iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmTbiYoVHGFuZGVyc3Nv bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FeCkQAJuHrH8Bb1954UR4yba3P7h4kmLQ xWgDzQXfTT6cl9MHmq/8RwoIhGABAbr3HNX0qwVNVNgn+w90LtVFSSL0SqKczkQk euwtJf+T2NKqFJnRisx2O78WhPYxw52d6rs+v2gw2AoWATX6zRdXpcHch37bUv+/ jBRNdas9wttrkxuOtJ7TD4G42KlIrM+6YukDWCtdwpLhBkKZwqu/UuEa8jwWyV8b cY9edRqo4P2nem0Nt5PmCGwFdHSBKR7wqDGMkwYP9tlziHfe6WTtQNYM+J7ZRMzg tslny8xIXZvo2xy2fwB8JGYD/rhQY3D16wL72mPFxOZelokdU1esX6pURw4JIyiB gHFDWEfEWXXbYzV+QDrxdbm28jgUTZinzDiRkkbxoPsA8roBmN9XHHlxm+/I4Yoj Vm1ymH1KUDOidkKlM1lfuTaXNxFGZ3xTtHweXD72d+uN+woUwcSM9N/FLugPq0Fb rng9FwxpOmr3Wc4NaIneRNOYA57+KaSY1OgMp5X+e9pAkjKoPKqOEPokgWUhqmAG PW+P3VJpwqT9xpaidN15Eyb/dIwtPa6IsRkK70l8DRLhLIwl8Zdbch+bV4AjTc7R fyxkuazL3Y+G7ddEvRXvgo6i0e1w8TTjn11D2NLn9yINZJhr6JqGbuS1F4dzYmUD Zc7WroVo89eep9Wh =ZesT -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmTeFRQACgkQYKtH/8kJ UifBZxAAg83TGfOxhmmHC/+YsJDK3qFDx8TbG1O6a65zpAOF0+mrDOzjIkaCFBVC jxpR8eKTMNVOq/ovfYOzENDik4qIcULyFFyIJDL3KtGQLh97/C6QzALUCDdHUbt5 CTS7sZ08VRIP7BRt0G9C6rlR4/cuCzEC1k5KgIKV8VLbzAgQN+ylC7CQZCCr/4uo mA2yDy2E3X15SA6W1PbH5JUBS1ckFzpwFFm5FsjrNgmAkMXtBshypjW1HFXQQFhg XZV+MLH32+Hdy3MQ016w/fHbln61W0DjVIjiABfyqLSgpiDQ5AqvONDcV3YbsdP3 dTnQQ2UJJ9xrbVT5retKOAs2jjMBZ/hmwZhExaI+m5+ZnSHiuOUctfKDkPL7aHcB fTzgc7Hrzalca7UDWRtC31IUlzlaHyXO/WLuAljwTqwFST2r7Jck/FSPDJMyRdJr hUixLBgby4W32PouDsPNqxsEO5Rhp8cPAa2Eb3i0L85EbZ3Zua9F36cSuhKE3xP6 lANsgnbr5he/wZohPIz9pDFUnFdUcIXghX3NGXM1obNxZ8T6/Y1mG3WZBCmQHgOI nWttoKhMHknnY6pKuk66IzIAvM7wED6wQgHekcUCK9ZkXr8zVZMzBaIX+0d4zx/F asi/g3pnxqt+RL3HjhLMQnIz48wF46rtajCsfEHoGEmoaO1UmD8= =VxVu -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-fixes-for-6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes Qualcomm ARM64 fixes for v6.5 This corrects the invalid path specifier for L3 interconnects in the CPU nodes of SM8150 and SM8250. It corrects the compatible of the SC8180X L3 node, to pass the binding check. The crypto core, and its DMA controller, is disabled on SM8350 to avoid the system from crashing at boot while the issue is diagnosed. A thermal zone node name conflict is resolved for PM8150L, on the RB5 board. The UFS vccq voltage is corrected on the SA877P Ride platform, to address observed stability issues. The reg-names of the DSI phy on SC7180 are restored after an accidental search-and-replace update. * tag 'qcom-arm64-fixes-for-6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: arm64: dts: qcom: sc7180: Fix DSI0_PHY reg-names arm64: dts: qcom: sa8775p-ride: Update L4C parameters arm64: dts: qcom: qrb5165-rb5: fix thermal zone conflict arm64: dts: qcom: sm8350: fix BAM DMA crash and reboot arm64: dts: qcom: sc8180x: Fix OSM L3 compatible arm64: dts: qcom: sm8250: Fix EPSS L3 interconnect cells arm64: dts: qcom: sm8150: Fix OSM L3 interconnect cells Link: https://lore.kernel.org/r/20230815142042.2459048-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Коммит
3c78dbf251
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@ -121,7 +121,7 @@
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};
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};
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pm8150l-thermal {
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pm8150l-pcb-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&pm8150l_adc_tm 1>;
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@ -153,8 +153,8 @@
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vreg_l4c: ldo4 {
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regulator-name = "vreg_l4c";
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1300000>;
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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/*
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* FIXME: This should have regulator-allow-set-load but
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@ -3120,8 +3120,8 @@
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reg = <0 0x0ae94400 0 0x200>,
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<0 0x0ae94600 0 0x280>,
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<0 0x0ae94a00 0 0x1e0>;
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reg-names = "dsi0_phy",
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"dsi0_phy_lane",
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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#clock-cells = <1>;
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@ -3561,7 +3561,7 @@
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};
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osm_l3: interconnect@18321000 {
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compatible = "qcom,sc8180x-osm-l3";
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compatible = "qcom,sc8180x-osm-l3", "qcom,osm-l3";
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reg = <0 0x18321000 0 0x1400>;
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
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@ -56,7 +56,7 @@
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qcom,freq-domain = <&cpufreq_hw 0>;
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operating-points-v2 = <&cpu0_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
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<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
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<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
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power-domains = <&CPU_PD0>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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@ -85,7 +85,7 @@
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qcom,freq-domain = <&cpufreq_hw 0>;
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operating-points-v2 = <&cpu0_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
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<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
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<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
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power-domains = <&CPU_PD1>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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@ -109,7 +109,7 @@
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qcom,freq-domain = <&cpufreq_hw 0>;
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operating-points-v2 = <&cpu0_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
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<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
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<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
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power-domains = <&CPU_PD2>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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@ -133,7 +133,7 @@
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qcom,freq-domain = <&cpufreq_hw 0>;
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operating-points-v2 = <&cpu0_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
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<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
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<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
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power-domains = <&CPU_PD3>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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@ -157,7 +157,7 @@
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qcom,freq-domain = <&cpufreq_hw 1>;
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operating-points-v2 = <&cpu4_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
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<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
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<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
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power-domains = <&CPU_PD4>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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@ -181,7 +181,7 @@
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qcom,freq-domain = <&cpufreq_hw 1>;
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operating-points-v2 = <&cpu4_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
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<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
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<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
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power-domains = <&CPU_PD5>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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@ -205,7 +205,7 @@
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qcom,freq-domain = <&cpufreq_hw 1>;
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operating-points-v2 = <&cpu4_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
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<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
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<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
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power-domains = <&CPU_PD6>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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@ -229,7 +229,7 @@
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qcom,freq-domain = <&cpufreq_hw 2>;
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operating-points-v2 = <&cpu7_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
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<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
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<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
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power-domains = <&CPU_PD7>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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@ -4342,7 +4342,7 @@
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
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clock-names = "xo", "alternate";
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#interconnect-cells = <2>;
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#interconnect-cells = <1>;
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};
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cpufreq_hw: cpufreq@18323000 {
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@ -107,7 +107,7 @@
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qcom,freq-domain = <&cpufreq_hw 0>;
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operating-points-v2 = <&cpu0_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
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<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
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<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
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#cooling-cells = <2>;
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L2_0: l2-cache {
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compatible = "cache";
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@ -138,7 +138,7 @@
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qcom,freq-domain = <&cpufreq_hw 0>;
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operating-points-v2 = <&cpu0_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
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<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
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<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
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#cooling-cells = <2>;
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L2_100: l2-cache {
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compatible = "cache";
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@ -163,7 +163,7 @@
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qcom,freq-domain = <&cpufreq_hw 0>;
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operating-points-v2 = <&cpu0_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
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<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
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<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
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#cooling-cells = <2>;
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L2_200: l2-cache {
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compatible = "cache";
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qcom,freq-domain = <&cpufreq_hw 0>;
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operating-points-v2 = <&cpu0_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
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<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
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<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
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#cooling-cells = <2>;
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L2_300: l2-cache {
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compatible = "cache";
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qcom,freq-domain = <&cpufreq_hw 1>;
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operating-points-v2 = <&cpu4_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
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<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
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<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
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#cooling-cells = <2>;
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L2_400: l2-cache {
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compatible = "cache";
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qcom,freq-domain = <&cpufreq_hw 1>;
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operating-points-v2 = <&cpu4_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
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<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
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<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
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#cooling-cells = <2>;
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L2_500: l2-cache {
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compatible = "cache";
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@ -263,7 +263,7 @@
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qcom,freq-domain = <&cpufreq_hw 1>;
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operating-points-v2 = <&cpu4_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
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<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
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<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
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#cooling-cells = <2>;
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L2_600: l2-cache {
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compatible = "cache";
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@ -288,7 +288,7 @@
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qcom,freq-domain = <&cpufreq_hw 2>;
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operating-points-v2 = <&cpu7_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
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<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
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<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
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#cooling-cells = <2>;
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L2_700: l2-cache {
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compatible = "cache";
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@ -5679,7 +5679,7 @@
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
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clock-names = "xo", "alternate";
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#interconnect-cells = <2>;
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#interconnect-cells = <1>;
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};
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cpufreq_hw: cpufreq@18591000 {
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@ -1744,6 +1744,8 @@
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qcom,controlled-remotely;
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iommus = <&apps_smmu 0x594 0x0011>,
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<&apps_smmu 0x596 0x0011>;
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/* FIXME: Probing BAM DMA causes some abort and system hang */
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status = "fail";
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};
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crypto: crypto@1dfa000 {
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@ -1755,6 +1757,8 @@
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<&apps_smmu 0x596 0x0011>;
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interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
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interconnect-names = "memory";
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/* FIXME: dependency BAM DMA is disabled */
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status = "disabled";
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};
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ipa: ipa@1e40000 {
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