x86: c_p_a() fix: reorder TLB / cache flushes to follow Intel recommendation
Intel recommends to first flush the TLBs and then the caches on caching attribute changes. c_p_a() previously did it the other way round. Reorder that. The procedure is still not fully compliant to the Intel documentation because Intel recommends a all CPU synchronization step between the TLB flushes and the cache flushes. However on all new Intel CPUs this is now meaningless anyways because they support Self-Snoop and can skip the cache flush step anyway. [ mingo@elte.hu: decoupled from clflush and ported it to x86.git ] Signed-off-by: Andi Kleen <ak@suse.de> Acked-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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@ -87,6 +87,12 @@ static void flush_kernel_map(void *arg)
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struct list_head *lh = (struct list_head *)arg;
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struct page *p;
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/*
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* Flush all to work around Errata in early athlons regarding
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* large page flushing.
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*/
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__flush_tlb_all();
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/* High level code is not ready for clflush yet */
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if (0 && cpu_has_clflush) {
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list_for_each_entry(p, lh, lru)
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@ -95,12 +101,6 @@ static void flush_kernel_map(void *arg)
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if (boot_cpu_data.x86_model >= 4)
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wbinvd();
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}
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/*
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* Flush all to work around Errata in early athlons regarding
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* large page flushing.
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*/
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__flush_tlb_all();
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}
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static void set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
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@ -82,6 +82,8 @@ static void flush_kernel_map(void *arg)
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struct list_head *l = (struct list_head *)arg;
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struct page *pg;
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__flush_tlb_all();
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/* When clflush is available always use it because it is
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much cheaper than WBINVD. */
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/* clflush is still broken. Disable for now. */
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@ -94,7 +96,6 @@ static void flush_kernel_map(void *arg)
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clflush_cache_range(addr, PAGE_SIZE);
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}
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}
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__flush_tlb_all();
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}
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static inline void flush_map(struct list_head *l)
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