Allwinner clocks additions for 3.17
This pull request adds support for the clocks found in the newly supported Allwinner A23 clocks. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJTyYx4AAoJEBx+YmzsjxAgj9QP/2zRnM312oQ0MPPys+QG8mLg Ecsi+RVuCnfk3+JGqvvh0FRkyNinK4KHitPc2YAvK07vOjwhalYNfFRtuK4MRgmW z217GHzr67GJuu5nn6xlP1c6NYSZEtImvbksnthE4SPXrxA56fp4FME9/I4/vOR+ /+5KNWHCfngfZTBVFvjeXAh/pNXEdYBpPqe/CQCmhjDW8rxJJAVoFCAXA+Xx2ln/ StJXnSQdiJtoDLF19iaqp+W1i2xhaLF3oLUcEoqL3/ZGTTrm2ylT8dFyCb2RpIsn 6CEzVKjky6Yr851AaU+d2p/IQEUT1j35zPiLDhyZCTsEEVW91h89ykB2GjlEwH+n cPicqfP+5/y0rnGU7JDjf4eqv/l+VX2M7/BKra2H4xLUrHXqZOSFnkidF6cdE77C nLHfNXR4eyIfw5r7ccwd2ZMTofzNpEIAixt6/UjfpCun0u1uFI54/vfEoXvcyemm IggOmah8BMogMG8ZhDHgQo5ln8JFjULkackAcwQL+a1qLZW601NOsa9Ke0xuCkEE lXw+JytWUwz+D+hxB5XAvYMLNRXZ4WuIY/VO4SfNR6fdc+9bs0QN942QA7T+46g2 SvUFml/9sbGKFOBRWx+sEebxoLz0jnt7FqxRU4z0ZK0W6qLiNs4TeIOy5JpxPCAE lEAwP7hv5da8InxsSlxR =85He -----END PGP SIGNATURE----- Merge tag 'sunxi-clocks-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next-sunxi Allwinner clocks additions for 3.17 This pull request adds support for the clocks found in the newly supported Allwinner A23 clocks.
This commit is contained in:
Mike Turquette
Коммит
3cc5aba415
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@ -9,11 +9,13 @@ Required properties:
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"allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
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"allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
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"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
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"allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
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"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
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"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
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"allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
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"allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
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"allwinner,sun4i-a10-axi-clk" - for the AXI clock
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"allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
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"allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
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"allwinner,sun4i-a10-ahb-clk" - for the AHB clock
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"allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
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@ -23,13 +25,16 @@ Required properties:
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"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
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"allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
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"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
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"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
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"allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
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"allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
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"allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
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"allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
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"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
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"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
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"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
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"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
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"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
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"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
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"allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
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"allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
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@ -37,8 +42,10 @@ Required properties:
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"allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
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"allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
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"allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
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"allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
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"allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
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"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
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"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
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"allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
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"allwinner,sun7i-a20-out-clk" - for the external output clocks
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"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
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@ -6,4 +6,6 @@ obj-y += clk-sunxi.o clk-factors.o
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obj-y += clk-a10-hosc.o
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obj-y += clk-a20-gmac.o
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obj-$(CONFIG_MFD_SUN6I_PRCM) += clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o
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obj-$(CONFIG_MFD_SUN6I_PRCM) += \
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clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
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clk-sun8i-apb0.o
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@ -62,7 +62,7 @@ static unsigned long clk_factors_recalc_rate(struct clk_hw *hw,
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p = FACTOR_GET(config->pshift, config->pwidth, reg);
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/* Calculate the rate */
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rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
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rate = (parent_rate * (n + config->n_start) * (k + 1) >> p) / (m + 1);
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return rate;
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}
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@ -15,6 +15,7 @@ struct clk_factors_config {
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u8 mwidth;
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u8 pshift;
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u8 pwidth;
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u8 n_start;
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};
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struct clk_factors {
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@ -9,23 +9,53 @@
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#define SUN6I_APB0_GATES_MAX_SIZE 32
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struct gates_data {
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DECLARE_BITMAP(mask, SUN6I_APB0_GATES_MAX_SIZE);
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};
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static const struct gates_data sun6i_a31_apb0_gates __initconst = {
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.mask = {0x7F},
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};
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static const struct gates_data sun8i_a23_apb0_gates __initconst = {
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.mask = {0x5D},
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};
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const struct of_device_id sun6i_a31_apb0_gates_clk_dt_ids[] = {
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{ .compatible = "allwinner,sun6i-a31-apb0-gates-clk", .data = &sun6i_a31_apb0_gates },
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{ .compatible = "allwinner,sun8i-a23-apb0-gates-clk", .data = &sun8i_a23_apb0_gates },
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{ /* sentinel */ }
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};
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static int sun6i_a31_apb0_gates_clk_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct clk_onecell_data *clk_data;
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const struct of_device_id *device;
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const struct gates_data *data;
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const char *clk_parent;
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const char *clk_name;
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struct resource *r;
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void __iomem *reg;
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int gate_id;
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int ngates;
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int i;
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int j = 0;
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if (!np)
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return -ENODEV;
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device = of_match_device(sun6i_a31_apb0_gates_clk_dt_ids, &pdev->dev);
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if (!device)
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return -ENODEV;
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data = device->data;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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reg = devm_ioremap_resource(&pdev->dev, r);
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@ -36,54 +66,36 @@ static int sun6i_a31_apb0_gates_clk_probe(struct platform_device *pdev)
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if (!clk_parent)
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return -EINVAL;
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ngates = of_property_count_strings(np, "clock-output-names");
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if (ngates < 0)
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return ngates;
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if (!ngates || ngates > SUN6I_APB0_GATES_MAX_SIZE)
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return -EINVAL;
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clk_data = devm_kzalloc(&pdev->dev, sizeof(struct clk_onecell_data),
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GFP_KERNEL);
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if (!clk_data)
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return -ENOMEM;
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clk_data->clks = devm_kzalloc(&pdev->dev,
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SUN6I_APB0_GATES_MAX_SIZE *
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sizeof(struct clk *),
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GFP_KERNEL);
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/* Worst-case size approximation and memory allocation */
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ngates = find_last_bit(data->mask, SUN6I_APB0_GATES_MAX_SIZE);
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clk_data->clks = devm_kcalloc(&pdev->dev, (ngates + 1),
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sizeof(struct clk *), GFP_KERNEL);
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if (!clk_data->clks)
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return -ENOMEM;
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for (i = 0; i < ngates; i++) {
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for_each_set_bit(i, data->mask, SUN6I_APB0_GATES_MAX_SIZE) {
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of_property_read_string_index(np, "clock-output-names",
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i, &clk_name);
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j, &clk_name);
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gate_id = i;
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of_property_read_u32_index(np, "clock-indices", i, &gate_id);
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clk_data->clks[i] = clk_register_gate(&pdev->dev, clk_name,
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clk_parent, 0, reg, i,
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0, NULL);
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WARN_ON(IS_ERR(clk_data->clks[i]));
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clk_register_clkdev(clk_data->clks[i], clk_name, NULL);
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WARN_ON(gate_id >= SUN6I_APB0_GATES_MAX_SIZE);
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if (gate_id >= SUN6I_APB0_GATES_MAX_SIZE)
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continue;
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clk_data->clks[gate_id] = clk_register_gate(&pdev->dev,
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clk_name,
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clk_parent, 0,
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reg, gate_id,
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0, NULL);
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WARN_ON(IS_ERR(clk_data->clks[gate_id]));
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j++;
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}
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clk_data->clk_num = ngates;
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clk_data->clk_num = ngates + 1;
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return of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
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}
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const struct of_device_id sun6i_a31_apb0_gates_clk_dt_ids[] = {
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{ .compatible = "allwinner,sun6i-a31-apb0-gates-clk" },
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{ /* sentinel */ }
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};
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static struct platform_driver sun6i_a31_apb0_gates_clk_driver = {
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.driver = {
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.name = "sun6i-a31-apb0-gates-clk",
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@ -0,0 +1,68 @@
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/*
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* Copyright (C) 2014 Chen-Yu Tsai
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* Author: Chen-Yu Tsai <wens@csie.org>
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*
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* Allwinner A23 APB0 clock driver
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*
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* License Terms: GNU General Public License v2
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*
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* Based on clk-sun6i-apb0.c
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* Allwinner A31 APB0 clock driver
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*
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* Copyright (C) 2014 Free Electrons
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* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
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*
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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static int sun8i_a23_apb0_clk_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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const char *clk_name = np->name;
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const char *clk_parent;
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struct resource *r;
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void __iomem *reg;
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struct clk *clk;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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reg = devm_ioremap_resource(&pdev->dev, r);
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if (IS_ERR(reg))
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return PTR_ERR(reg);
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clk_parent = of_clk_get_parent_name(np, 0);
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if (!clk_parent)
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return -EINVAL;
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of_property_read_string(np, "clock-output-names", &clk_name);
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/* The A23 APB0 clock is a standard 2 bit wide divider clock */
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clk = clk_register_divider(&pdev->dev, clk_name, clk_parent, 0, reg,
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0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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return of_clk_add_provider(np, of_clk_src_simple_get, clk);
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}
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const struct of_device_id sun8i_a23_apb0_clk_dt_ids[] = {
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{ .compatible = "allwinner,sun8i-a23-apb0-clk" },
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{ /* sentinel */ }
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};
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static struct platform_driver sun8i_a23_apb0_clk_driver = {
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.driver = {
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.name = "sun8i-a23-apb0-clk",
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.owner = THIS_MODULE,
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.of_match_table = sun8i_a23_apb0_clk_dt_ids,
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},
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.probe = sun8i_a23_apb0_clk_probe,
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};
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module_platform_driver(sun8i_a23_apb0_clk_driver);
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MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
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MODULE_DESCRIPTION("Allwinner A23 APB0 clock Driver");
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MODULE_LICENSE("GPL v2");
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@ -163,6 +163,54 @@ static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
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}
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}
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/**
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* sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1
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* PLL1 rate is calculated as follows
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* rate = (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1);
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* parent_rate is always 24Mhz
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*/
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static void sun8i_a23_get_pll1_factors(u32 *freq, u32 parent_rate,
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u8 *n, u8 *k, u8 *m, u8 *p)
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{
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u8 div;
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/* Normalize value to a 6M multiple */
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div = *freq / 6000000;
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*freq = 6000000 * div;
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/* we were called to round the frequency, we can now return */
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if (n == NULL)
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return;
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/* m is always zero for pll1 */
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*m = 0;
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/* k is 1 only on these cases */
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if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
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*k = 1;
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else
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*k = 0;
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/* p will be 2 for divs under 20 and odd divs under 32 */
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if (div < 20 || (div < 32 && (div & 1)))
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*p = 2;
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/* p will be 1 for even divs under 32, divs under 40 and odd pairs
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* of divs between 40-62 */
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else if (div < 40 || (div < 64 && (div & 2)))
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*p = 1;
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/* any other entries have p = 0 */
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else
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*p = 0;
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/* calculate a suitable n based on k and p */
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div <<= *p;
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div /= (*k + 1);
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*n = div / 4 - 1;
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}
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/**
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* sun4i_get_pll5_factors() - calculates n, k factors for PLL5
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* PLL5 rate is calculated as follows
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@ -422,6 +470,18 @@ static struct clk_factors_config sun6i_a31_pll1_config = {
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.mwidth = 2,
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};
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static struct clk_factors_config sun8i_a23_pll1_config = {
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.nshift = 8,
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.nwidth = 5,
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.kshift = 4,
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.kwidth = 2,
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.mshift = 0,
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.mwidth = 2,
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.pshift = 16,
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.pwidth = 2,
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.n_start = 1,
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};
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static struct clk_factors_config sun4i_pll5_config = {
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.nshift = 8,
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.nwidth = 5,
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@ -471,6 +531,12 @@ static const struct factors_data sun6i_a31_pll1_data __initconst = {
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.getter = sun6i_a31_get_pll1_factors,
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};
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static const struct factors_data sun8i_a23_pll1_data __initconst = {
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.enable = 31,
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.table = &sun8i_a23_pll1_config,
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.getter = sun8i_a23_get_pll1_factors,
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};
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static const struct factors_data sun7i_a20_pll4_data __initconst = {
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.enable = 31,
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.table = &sun4i_pll5_config,
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@ -664,6 +730,7 @@ struct div_data {
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u8 shift;
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u8 pow;
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u8 width;
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const struct clk_div_table *table;
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};
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static const struct div_data sun4i_axi_data __initconst = {
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@ -672,6 +739,23 @@ static const struct div_data sun4i_axi_data __initconst = {
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.width = 2,
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};
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static const struct clk_div_table sun8i_a23_axi_table[] __initconst = {
|
||||
{ .val = 0, .div = 1 },
|
||||
{ .val = 1, .div = 2 },
|
||||
{ .val = 2, .div = 3 },
|
||||
{ .val = 3, .div = 4 },
|
||||
{ .val = 4, .div = 4 },
|
||||
{ .val = 5, .div = 4 },
|
||||
{ .val = 6, .div = 4 },
|
||||
{ .val = 7, .div = 4 },
|
||||
{ } /* sentinel */
|
||||
};
|
||||
|
||||
static const struct div_data sun8i_a23_axi_data __initconst = {
|
||||
.width = 3,
|
||||
.table = sun8i_a23_axi_table,
|
||||
};
|
||||
|
||||
static const struct div_data sun4i_ahb_data __initconst = {
|
||||
.shift = 4,
|
||||
.pow = 1,
|
||||
|
|
@ -704,10 +788,10 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
|
|||
|
||||
of_property_read_string(node, "clock-output-names", &clk_name);
|
||||
|
||||
clk = clk_register_divider(NULL, clk_name, clk_parent, 0,
|
||||
reg, data->shift, data->width,
|
||||
data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
|
||||
&clk_lock);
|
||||
clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0,
|
||||
reg, data->shift, data->width,
|
||||
data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
|
||||
data->table, &clk_lock);
|
||||
if (clk) {
|
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
clk_register_clkdev(clk, clk_name, NULL);
|
||||
|
|
@ -804,6 +888,10 @@ static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
|
|||
.mask = { 0x12f77fff, 0x16ff3f },
|
||||
};
|
||||
|
||||
static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
|
||||
.mask = {0x25386742, 0x2505111},
|
||||
};
|
||||
|
||||
static const struct gates_data sun4i_apb0_gates_data __initconst = {
|
||||
.mask = {0x4EF},
|
||||
};
|
||||
|
|
@ -836,6 +924,10 @@ static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
|
|||
.mask = {0x3031},
|
||||
};
|
||||
|
||||
static const struct gates_data sun8i_a23_apb1_gates_data __initconst = {
|
||||
.mask = {0x3021},
|
||||
};
|
||||
|
||||
static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
|
||||
.mask = {0x3F000F},
|
||||
};
|
||||
|
|
@ -844,6 +936,10 @@ static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
|
|||
.mask = { 0xff80ff },
|
||||
};
|
||||
|
||||
static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
|
||||
.mask = {0x1F0007},
|
||||
};
|
||||
|
||||
static const struct gates_data sun4i_a10_usb_gates_data __initconst = {
|
||||
.mask = {0x1C0},
|
||||
.reset_mask = 0x07,
|
||||
|
|
@ -870,7 +966,6 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
|
|||
int qty;
|
||||
int i = 0;
|
||||
int j = 0;
|
||||
int ignore;
|
||||
|
||||
reg = of_iomap(node, 0);
|
||||
|
||||
|
|
@ -891,14 +986,12 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
|
|||
of_property_read_string_index(node, "clock-output-names",
|
||||
j, &clk_name);
|
||||
|
||||
/* No driver claims this clock, but it should remain gated */
|
||||
ignore = !strcmp("ahb_sdram", clk_name) ? CLK_IGNORE_UNUSED : 0;
|
||||
|
||||
clk_data->clks[i] = clk_register_gate(NULL, clk_name,
|
||||
clk_parent, ignore,
|
||||
clk_parent, 0,
|
||||
reg + 4 * (i/32), i % 32,
|
||||
0, &clk_lock);
|
||||
WARN_ON(IS_ERR(clk_data->clks[i]));
|
||||
clk_register_clkdev(clk_data->clks[i], clk_name, NULL);
|
||||
|
||||
j++;
|
||||
}
|
||||
|
|
@ -1102,6 +1195,7 @@ free_clkdata:
|
|||
static const struct of_device_id clk_factors_match[] __initconst = {
|
||||
{.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,},
|
||||
{.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
|
||||
{.compatible = "allwinner,sun8i-a23-pll1-clk", .data = &sun8i_a23_pll1_data,},
|
||||
{.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
|
||||
{.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
|
||||
{.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
|
||||
|
|
@ -1113,6 +1207,7 @@ static const struct of_device_id clk_factors_match[] __initconst = {
|
|||
/* Matches for divider clocks */
|
||||
static const struct of_device_id clk_div_match[] __initconst = {
|
||||
{.compatible = "allwinner,sun4i-a10-axi-clk", .data = &sun4i_axi_data,},
|
||||
{.compatible = "allwinner,sun8i-a23-axi-clk", .data = &sun8i_a23_axi_data,},
|
||||
{.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,},
|
||||
{.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,},
|
||||
{.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,},
|
||||
|
|
@ -1142,6 +1237,7 @@ static const struct of_device_id clk_gates_match[] __initconst = {
|
|||
{.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
|
||||
{.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
|
||||
{.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
|
||||
{.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,},
|
||||
{.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
|
||||
{.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
|
||||
{.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
|
||||
|
|
@ -1151,7 +1247,9 @@ static const struct of_device_id clk_gates_match[] __initconst = {
|
|||
{.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
|
||||
{.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
|
||||
{.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
|
||||
{.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,},
|
||||
{.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
|
||||
{.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
|
||||
{.compatible = "allwinner,sun4i-a10-usb-clk", .data = &sun4i_a10_usb_gates_data,},
|
||||
{.compatible = "allwinner,sun5i-a13-usb-clk", .data = &sun5i_a13_usb_gates_data,},
|
||||
{.compatible = "allwinner,sun6i-a31-usb-clk", .data = &sun6i_a31_usb_gates_data,},
|
||||
|
|
@ -1202,6 +1300,7 @@ static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
|
|||
|
||||
static const char *sun4i_a10_critical_clocks[] __initdata = {
|
||||
"pll5_ddr",
|
||||
"ahb_sdram",
|
||||
};
|
||||
|
||||
static void __init sun4i_a10_init_clocks(struct device_node *node)
|
||||
|
|
@ -1214,6 +1313,7 @@ CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks)
|
|||
static const char *sun5i_critical_clocks[] __initdata = {
|
||||
"mbus",
|
||||
"pll5_ddr",
|
||||
"ahb_sdram",
|
||||
};
|
||||
|
||||
static void __init sun5i_init_clocks(struct device_node *node)
|
||||
|
|
@ -1236,3 +1336,4 @@ static void __init sun6i_init_clocks(struct device_node *node)
|
|||
ARRAY_SIZE(sun6i_critical_clocks));
|
||||
}
|
||||
CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
|
||||
CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
|
||||
|
|
|
|||
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