drm/nouveau/disp/nv50-: simplify definition of base channels

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild

@@ -73,11 +73,7 @@ nvkm-y += nvkm/engine/disp/dmacgp102.o
 
 nvkm-y += nvkm/engine/disp/basenv50.o
 nvkm-y += nvkm/engine/disp/baseg84.o
-nvkm-y += nvkm/engine/disp/basegt200.o
-nvkm-y += nvkm/engine/disp/basegt215.o
 nvkm-y += nvkm/engine/disp/basegf119.o
-nvkm-y += nvkm/engine/disp/basegk104.o
-nvkm-y += nvkm/engine/disp/basegk110.o
 nvkm-y += nvkm/engine/disp/basegp102.o
 
 nvkm-y += nvkm/engine/disp/corenv50.o

drivers/gpu/drm/nouveau/nvkm/engine/disp/baseg84.c

@@ -22,9 +22,6 @@
  * Authors: Ben Skeggs
  */
 #include "dmacnv50.h"
-#include "rootnv50.h"
-
-#include <nvif/class.h>
 
 static const struct nv50_disp_mthd_list
 g84_disp_base_mthd_base = {
@@ -56,8 +53,8 @@ g84_disp_base_mthd_base = {
 	}
 };
 
-const struct nv50_disp_chan_mthd
+static const struct nv50_disp_chan_mthd
-g84_disp_base_chan_mthd = {
+g84_disp_base_mthd = {
 	.name = "Base",
 	.addr = 0x000540,
 	.prev = 0x000004,
@@ -68,13 +65,10 @@ g84_disp_base_chan_mthd = {
 	}
 };
 
-const struct nv50_disp_dmac_oclass
+int
-g84_disp_base_oclass = {
+g84_disp_base_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
-	.base.oclass = G82_DISP_BASE_CHANNEL_DMA,
+		  struct nv50_disp *disp, struct nvkm_object **pobject)
-	.base.minver = 0,
+{
-	.base.maxver = 0,
+	return nv50_disp_base_new_(&nv50_disp_dmac_func, &g84_disp_base_mthd,
-	.ctor = nv50_disp_base_new,
+				   disp, 1, oclass, argv, argc, pobject);
-	.func = &nv50_disp_dmac_func,
+}
-	.mthd = &g84_disp_base_chan_mthd,
-	.chid = 1,
-};

drivers/gpu/drm/nouveau/nvkm/engine/disp/basegf119.c

@@ -22,9 +22,6 @@
  * Authors: Ben Skeggs
  */
 #include "dmacnv50.h"
-#include "rootnv50.h"
-
-#include <nvif/class.h>
 
 static const struct nv50_disp_mthd_list
 gf119_disp_base_mthd_base = {
@@ -91,7 +88,7 @@ gf119_disp_base_mthd_image = {
 };
 
 const struct nv50_disp_chan_mthd
-gf119_disp_base_chan_mthd = {
+gf119_disp_base_mthd = {
 	.name = "Base",
 	.addr = 0x001000,
 	.prev = -0x020000,
@@ -102,13 +99,10 @@ gf119_disp_base_chan_mthd = {
 	}
 };
 
-const struct nv50_disp_dmac_oclass
+int
-gf119_disp_base_oclass = {
+gf119_disp_base_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
-	.base.oclass = GF110_DISP_BASE_CHANNEL_DMA,
+		    struct nv50_disp *disp, struct nvkm_object **pobject)
-	.base.minver = 0,
+{
-	.base.maxver = 0,
+	return nv50_disp_base_new_(&gf119_disp_dmac_func, &gf119_disp_base_mthd,
-	.ctor = nv50_disp_base_new,
+				   disp, 1, oclass, argv, argc, pobject);
-	.func = &gf119_disp_dmac_func,
+}
-	.mthd = &gf119_disp_base_chan_mthd,
-	.chid = 1,
-};

drivers/gpu/drm/nouveau/nvkm/engine/disp/basegk104.c

@@ -1,38 +0,0 @@
-/*
- * Copyright 2015 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-#include "dmacnv50.h"
-#include "rootnv50.h"
-
-#include <nvif/class.h>
-
-const struct nv50_disp_dmac_oclass
-gk104_disp_base_oclass = {
-	.base.oclass = GK104_DISP_BASE_CHANNEL_DMA,
-	.base.minver = 0,
-	.base.maxver = 0,
-	.ctor = nv50_disp_base_new,
-	.func = &gf119_disp_dmac_func,
-	.mthd = &gf119_disp_base_chan_mthd,
-	.chid = 1,
-};

drivers/gpu/drm/nouveau/nvkm/engine/disp/basegk110.c

@@ -1,38 +0,0 @@
-/*
- * Copyright 2015 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-#include "dmacnv50.h"
-#include "rootnv50.h"
-
-#include <nvif/class.h>
-
-const struct nv50_disp_dmac_oclass
-gk110_disp_base_oclass = {
-	.base.oclass = GK110_DISP_BASE_CHANNEL_DMA,
-	.base.minver = 0,
-	.base.maxver = 0,
-	.ctor = nv50_disp_base_new,
-	.func = &gf119_disp_dmac_func,
-	.mthd = &gf119_disp_base_chan_mthd,
-	.chid = 1,
-};

drivers/gpu/drm/nouveau/nvkm/engine/disp/basegp102.c

@@ -22,17 +22,11 @@
  * Authors: Ben Skeggs <bskeggs@redhat.com>
  */
 #include "dmacnv50.h"
-#include "rootnv50.h"
 
-#include <nvif/class.h>
+int
-
+gp102_disp_base_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
-const struct nv50_disp_dmac_oclass
+		    struct nv50_disp *disp, struct nvkm_object **pobject)
-gp102_disp_base_oclass = {
+{
-	.base.oclass = GK110_DISP_BASE_CHANNEL_DMA,
+	return nv50_disp_base_new_(&gp102_disp_dmac_func, &gf119_disp_base_mthd,
-	.base.minver = 0,
+				   disp, 1, oclass, argv, argc, pobject);
-	.base.maxver = 0,
+}
-	.ctor = nv50_disp_base_new,
-	.func = &gp102_disp_dmac_func,
-	.mthd = &gf119_disp_base_chan_mthd,
-	.chid = 1,
-};

drivers/gpu/drm/nouveau/nvkm/engine/disp/basegt200.c

@@ -1,38 +0,0 @@
-/*
- * Copyright 2015 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-#include "dmacnv50.h"
-#include "rootnv50.h"
-
-#include <nvif/class.h>
-
-const struct nv50_disp_dmac_oclass
-gt200_disp_base_oclass = {
-	.base.oclass = GT200_DISP_BASE_CHANNEL_DMA,
-	.base.minver = 0,
-	.base.maxver = 0,
-	.ctor = nv50_disp_base_new,
-	.func = &nv50_disp_dmac_func,
-	.mthd = &g84_disp_base_chan_mthd,
-	.chid = 1,
-};

drivers/gpu/drm/nouveau/nvkm/engine/disp/basegt215.c

@@ -1,38 +0,0 @@
-/*
- * Copyright 2015 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-#include "dmacnv50.h"
-#include "rootnv50.h"
-
-#include <nvif/class.h>
-
-const struct nv50_disp_dmac_oclass
-gt215_disp_base_oclass = {
-	.base.oclass = GT214_DISP_BASE_CHANNEL_DMA,
-	.base.minver = 0,
-	.base.maxver = 0,
-	.ctor = nv50_disp_base_new,
-	.func = &nv50_disp_dmac_func,
-	.mthd = &g84_disp_base_chan_mthd,
-	.chid = 1,
-};

drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c

@@ -23,31 +23,28 @@
  */
 #include "dmacnv50.h"
 #include "head.h"
-#include "rootnv50.h"
 
 #include <core/client.h>
 
-#include <nvif/class.h>
 #include <nvif/cl507c.h>
 #include <nvif/unpack.h>
 
 int
-nv50_disp_base_new(const struct nv50_disp_dmac_func *func,
+nv50_disp_base_new_(const struct nv50_disp_dmac_func *func,
-		   const struct nv50_disp_chan_mthd *mthd,
+		    const struct nv50_disp_chan_mthd *mthd,
-		   struct nv50_disp_root *root, int chid,
+		    struct nv50_disp *disp, int chid,
-		   const struct nvkm_oclass *oclass, void *data, u32 size,
+		    const struct nvkm_oclass *oclass, void *argv, u32 argc,
-		   struct nvkm_object **pobject)
+		    struct nvkm_object **pobject)
 {
 	union {
 		struct nv50_disp_base_channel_dma_v0 v0;
-	} *args = data;
+	} *args = argv;
 	struct nvkm_object *parent = oclass->parent;
-	struct nv50_disp *disp = root->disp;
 	int head, ret = -ENOSYS;
 	u64 push;
 
-	nvif_ioctl(parent, "create disp base channel dma size %d\n", size);
+	nvif_ioctl(parent, "create disp base channel dma size %d\n", argc);
-	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
+	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
 		nvif_ioctl(parent, "create disp base channel dma vers %d "
 				   "pushbuf %016llx head %d\n",
 			   args->v0.version, args->v0.pushbuf, args->v0.head);
@@ -102,7 +99,7 @@ nv50_disp_base_mthd_image = {
 };
 
 static const struct nv50_disp_chan_mthd
-nv50_disp_base_chan_mthd = {
+nv50_disp_base_mthd = {
 	.name = "Base",
 	.addr = 0x000540,
 	.prev = 0x000004,
@@ -113,13 +110,10 @@ nv50_disp_base_chan_mthd = {
 	}
 };
 
-const struct nv50_disp_dmac_oclass
+int
-nv50_disp_base_oclass = {
+nv50_disp_base_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
-	.base.oclass = NV50_DISP_BASE_CHANNEL_DMA,
+		   struct nv50_disp *disp, struct nvkm_object **pobject)
-	.base.minver = 0,
+{
-	.base.maxver = 0,
+	return nv50_disp_base_new_(&nv50_disp_dmac_func, &nv50_disp_base_mthd,
-	.ctor = nv50_disp_base_new,
+				   disp, 1, oclass, argv, argc, pobject);
-	.func = &nv50_disp_dmac_func,
+}
-	.mthd = &nv50_disp_base_chan_mthd,
-	.chid = 1,
-};

drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h

@@ -54,6 +54,11 @@ int nv50_disp_oimm_new_(const struct nv50_disp_chan_func *,
 			struct nv50_disp *, int ctrl, int user,
 			const struct nvkm_oclass *, void *argv, u32 argc,
 			struct nvkm_object **);
+int nv50_disp_base_new_(const struct nv50_disp_dmac_func *,
+			const struct nv50_disp_chan_mthd *,
+			struct nv50_disp *, int chid,
+			const struct nvkm_oclass *, void *argv, u32 argc,
+			struct nvkm_object **);
 int nv50_disp_ovly_new_(const struct nv50_disp_dmac_func *,
 			const struct nv50_disp_chan_mthd *,
 			struct nv50_disp *, int chid,
@@ -62,9 +67,13 @@ int nv50_disp_ovly_new_(const struct nv50_disp_dmac_func *,
 
 int nv50_disp_oimm_new(const struct nvkm_oclass *, void *, u32,
 		       struct nv50_disp *, struct nvkm_object **);
+int nv50_disp_base_new(const struct nvkm_oclass *, void *, u32,
+		       struct nv50_disp *, struct nvkm_object **);
 int nv50_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
 		       struct nv50_disp *, struct nvkm_object **);
 
+int g84_disp_base_new(const struct nvkm_oclass *, void *, u32,
+		      struct nv50_disp *, struct nvkm_object **);
 int g84_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
 		      struct nv50_disp *, struct nvkm_object **);
 
@@ -73,6 +82,8 @@ int gt200_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
 
 int gf119_disp_oimm_new(const struct nvkm_oclass *, void *, u32,
 			struct nv50_disp *, struct nvkm_object **);
+int gf119_disp_base_new(const struct nvkm_oclass *, void *, u32,
+			struct nv50_disp *, struct nvkm_object **);
 int gf119_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
 			struct nv50_disp *, struct nvkm_object **);
 
@@ -81,6 +92,8 @@ int gk104_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
 
 int gp102_disp_oimm_new(const struct nvkm_oclass *, void *, u32,
 			struct nv50_disp *, struct nvkm_object **);
+int gp102_disp_base_new(const struct nvkm_oclass *, void *, u32,
+			struct nv50_disp *, struct nvkm_object **);
 int gp102_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
 			struct nv50_disp *, struct nvkm_object **);
 
@@ -115,7 +128,6 @@ extern const struct nv50_disp_mthd_list nv50_disp_base_mthd_image;
 extern const struct nv50_disp_chan_mthd g84_disp_core_chan_mthd;
 extern const struct nv50_disp_mthd_list g84_disp_core_mthd_dac;
 extern const struct nv50_disp_mthd_list g84_disp_core_mthd_head;
-extern const struct nv50_disp_chan_mthd g84_disp_base_chan_mthd;
 
 extern const struct nv50_disp_chan_mthd g94_disp_core_chan_mthd;
 
@@ -123,7 +135,7 @@ extern const struct nv50_disp_mthd_list gf119_disp_core_mthd_base;
 extern const struct nv50_disp_mthd_list gf119_disp_core_mthd_dac;
 extern const struct nv50_disp_mthd_list gf119_disp_core_mthd_sor;
 extern const struct nv50_disp_mthd_list gf119_disp_core_mthd_pior;
-extern const struct nv50_disp_chan_mthd gf119_disp_base_chan_mthd;
+extern const struct nv50_disp_chan_mthd gf119_disp_base_mthd;
 
 extern const struct nv50_disp_chan_mthd gk104_disp_core_chan_mthd;
 extern const struct nv50_disp_chan_mthd gk104_disp_ovly_mthd;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.h

@@ -50,34 +50,22 @@ int nv50_disp_core_new(const struct nv50_disp_dmac_func *,
 		       struct nv50_disp_root *, int chid,
 		       const struct nvkm_oclass *oclass, void *data, u32 size,
 		       struct nvkm_object **);
-int nv50_disp_base_new(const struct nv50_disp_dmac_func *,
-		       const struct nv50_disp_chan_mthd *,
-		       struct nv50_disp_root *, int chid,
-		       const struct nvkm_oclass *oclass, void *data, u32 size,
-		       struct nvkm_object **);
 
 extern const struct nv50_disp_dmac_oclass nv50_disp_core_oclass;
-extern const struct nv50_disp_dmac_oclass nv50_disp_base_oclass;
 
 extern const struct nv50_disp_dmac_oclass g84_disp_core_oclass;
-extern const struct nv50_disp_dmac_oclass g84_disp_base_oclass;
 
 extern const struct nv50_disp_dmac_oclass g94_disp_core_oclass;
 
 extern const struct nv50_disp_dmac_oclass gt200_disp_core_oclass;
-extern const struct nv50_disp_dmac_oclass gt200_disp_base_oclass;
 
 extern const struct nv50_disp_dmac_oclass gt215_disp_core_oclass;
-extern const struct nv50_disp_dmac_oclass gt215_disp_base_oclass;
 
 extern const struct nv50_disp_dmac_oclass gf119_disp_core_oclass;
-extern const struct nv50_disp_dmac_oclass gf119_disp_base_oclass;
 
 extern const struct nv50_disp_dmac_oclass gk104_disp_core_oclass;
-extern const struct nv50_disp_dmac_oclass gk104_disp_base_oclass;
 
 extern const struct nv50_disp_dmac_oclass gk110_disp_core_oclass;
-extern const struct nv50_disp_dmac_oclass gk110_disp_base_oclass;
 
 extern const struct nv50_disp_dmac_oclass gm107_disp_core_oclass;
 
@@ -86,5 +74,4 @@ extern const struct nv50_disp_dmac_oclass gm200_disp_core_oclass;
 extern const struct nv50_disp_dmac_oclass gp100_disp_core_oclass;
 
 extern const struct nv50_disp_dmac_oclass gp102_disp_core_oclass;
-extern const struct nv50_disp_dmac_oclass gp102_disp_base_oclass;
 #endif

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg84.c

@@ -30,13 +30,13 @@ static const struct nv50_disp_root_func
 g84_disp_root = {
 	.dmac = {
 		&g84_disp_core_oclass,
-		&g84_disp_base_oclass,
 	},
 	.pioc = {
 		&g84_disp_curs_oclass,
 	},
 	.user = {
 		{{0,0,G82_DISP_OVERLAY            }, nv50_disp_oimm_new },
+		{{0,0,G82_DISP_BASE_CHANNEL_DMA   },  g84_disp_base_new },
 		{{0,0,G82_DISP_OVERLAY_CHANNEL_DMA},  g84_disp_ovly_new },
 		{}
 	},

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg94.c

@@ -30,13 +30,13 @@ static const struct nv50_disp_root_func
 g94_disp_root = {
 	.dmac = {
 		&g94_disp_core_oclass,
-		&gt200_disp_base_oclass,
 	},
 	.pioc = {
 		&g84_disp_curs_oclass,
 	},
 	.user = {
 		{{0,0,  G82_DISP_OVERLAY            },  nv50_disp_oimm_new },
+		{{0,0,GT200_DISP_BASE_CHANNEL_DMA   },   g84_disp_base_new },
 		{{0,0,GT200_DISP_OVERLAY_CHANNEL_DMA}, gt200_disp_ovly_new },
 		{}
 	},

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgf119.c

@@ -30,13 +30,13 @@ static const struct nv50_disp_root_func
 gf119_disp_root = {
 	.dmac = {
 		&gf119_disp_core_oclass,
-		&gf119_disp_base_oclass,
 	},
 	.pioc = {
 		&gf119_disp_curs_oclass,
 	},
 	.user = {
 		{{0,0,GF110_DISP_OVERLAY            }, gf119_disp_oimm_new },
+		{{0,0,GF110_DISP_BASE_CHANNEL_DMA   }, gf119_disp_base_new },
 		{{0,0,GF110_DISP_OVERLAY_CONTROL_DMA}, gf119_disp_ovly_new },
 		{}
 	},

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk104.c

@@ -30,13 +30,13 @@ static const struct nv50_disp_root_func
 gk104_disp_root = {
 	.dmac = {
 		&gk104_disp_core_oclass,
-		&gk104_disp_base_oclass,
 	},
 	.pioc = {
 		&gk104_disp_curs_oclass,
 	},
 	.user = {
 		{{0,0,GK104_DISP_OVERLAY            }, gf119_disp_oimm_new },
+		{{0,0,GK104_DISP_BASE_CHANNEL_DMA   }, gf119_disp_base_new },
 		{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
 		{}
 	},

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk110.c

@@ -30,13 +30,13 @@ static const struct nv50_disp_root_func
 gk110_disp_root = {
 	.dmac = {
 		&gk110_disp_core_oclass,
-		&gk110_disp_base_oclass,
 	},
 	.pioc = {
 		&gk104_disp_curs_oclass,
 	},
 	.user = {
 		{{0,0,GK104_DISP_OVERLAY            }, gf119_disp_oimm_new },
+		{{0,0,GK110_DISP_BASE_CHANNEL_DMA   }, gf119_disp_base_new },
 		{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
 		{}
 	},

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm107.c

@@ -30,13 +30,13 @@ static const struct nv50_disp_root_func
 gm107_disp_root = {
 	.dmac = {
 		&gm107_disp_core_oclass,
-		&gk110_disp_base_oclass,
 	},
 	.pioc = {
 		&gk104_disp_curs_oclass,
 	},
 	.user = {
 		{{0,0,GK104_DISP_OVERLAY            }, gf119_disp_oimm_new },
+		{{0,0,GK110_DISP_BASE_CHANNEL_DMA   }, gf119_disp_base_new },
 		{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
 		{}
 	},

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm200.c

@@ -30,13 +30,13 @@ static const struct nv50_disp_root_func
 gm200_disp_root = {
 	.dmac = {
 		&gm200_disp_core_oclass,
-		&gk110_disp_base_oclass,
 	},
 	.pioc = {
 		&gk104_disp_curs_oclass,
 	},
 	.user = {
 		{{0,0,GK104_DISP_OVERLAY            }, gf119_disp_oimm_new },
+		{{0,0,GK110_DISP_BASE_CHANNEL_DMA   }, gf119_disp_base_new },
 		{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
 		{}
 	},

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp100.c

@@ -30,13 +30,13 @@ static const struct nv50_disp_root_func
 gp100_disp_root = {
 	.dmac = {
 		&gp100_disp_core_oclass,
-		&gk110_disp_base_oclass,
 	},
 	.pioc = {
 		&gk104_disp_curs_oclass,
 	},
 	.user = {
 		{{0,0,GK104_DISP_OVERLAY            }, gf119_disp_oimm_new },
+		{{0,0,GK110_DISP_BASE_CHANNEL_DMA   }, gf119_disp_base_new },
 		{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
 		{}
 	},

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp102.c

@@ -30,13 +30,13 @@ static const struct nv50_disp_root_func
 gp102_disp_root = {
 	.dmac = {
 		&gp102_disp_core_oclass,
-		&gp102_disp_base_oclass,
 	},
 	.pioc = {
 		&gp102_disp_curs_oclass,
 	},
 	.user = {
 		{{0,0,GK104_DISP_OVERLAY            }, gp102_disp_oimm_new },
+		{{0,0,GK110_DISP_BASE_CHANNEL_DMA   }, gp102_disp_base_new },
 		{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gp102_disp_ovly_new },
 		{}
 	},

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt200.c

@@ -30,13 +30,13 @@ static const struct nv50_disp_root_func
 gt200_disp_root = {
 	.dmac = {
 		&gt200_disp_core_oclass,
-		&gt200_disp_base_oclass,
 	},
 	.pioc = {
 		&g84_disp_curs_oclass,
 	},
 	.user = {
 		{{0,0,  G82_DISP_OVERLAY            },  nv50_disp_oimm_new },
+		{{0,0,GT200_DISP_BASE_CHANNEL_DMA   },   g84_disp_base_new },
 		{{0,0,GT200_DISP_OVERLAY_CHANNEL_DMA}, gt200_disp_ovly_new },
 		{}
 	},

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt215.c

@@ -30,13 +30,13 @@ static const struct nv50_disp_root_func
 gt215_disp_root = {
 	.dmac = {
 		&gt215_disp_core_oclass,
-		&gt215_disp_base_oclass,
 	},
 	.pioc = {
 		&gt215_disp_curs_oclass,
 	},
 	.user = {
 		{{0,0,GT214_DISP_OVERLAY            },  nv50_disp_oimm_new },
+		{{0,0,GT214_DISP_BASE_CHANNEL_DMA   },   g84_disp_base_new },
 		{{0,0,GT214_DISP_OVERLAY_CHANNEL_DMA},   g84_disp_ovly_new },
 		{}
 	},

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c

@@ -368,13 +368,13 @@ static const struct nv50_disp_root_func
 nv50_disp_root = {
 	.dmac = {
 		&nv50_disp_core_oclass,
-		&nv50_disp_base_oclass,
 	},
 	.pioc = {
 		&nv50_disp_curs_oclass,
 	},
 	.user = {
 		{{0,0,NV50_DISP_OVERLAY            }, nv50_disp_oimm_new },
+		{{0,0,NV50_DISP_BASE_CHANNEL_DMA   }, nv50_disp_base_new },
 		{{0,0,NV50_DISP_OVERLAY_CHANNEL_DMA}, nv50_disp_ovly_new },
 		{}
 	},

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.h

@@ -13,7 +13,7 @@ struct nv50_disp_root {
 };
 
 struct nv50_disp_root_func {
-	const struct nv50_disp_dmac_oclass *dmac[2];
+	const struct nv50_disp_dmac_oclass *dmac[1];
 	const struct nv50_disp_pioc_oclass *pioc[1];
 	struct nv50_disp_user {
 		struct nvkm_sclass base;