KVM: arm64: PMU: Move the ID_AA64DFR0_EL1.PMUver limit to VM creation
As further patches will enable the selection of a PMU revision from userspace, sample the supported PMU revision at VM creation time, rather than building each time the ID_AA64DFR0_EL1 register is accessed. This shouldn't result in any change in behaviour. Reviewed-by: Reiji Watanabe <reijiw@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20221113163832.3154370-11-maz@kernel.org
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@ -163,6 +163,10 @@ struct kvm_arch {
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u8 pfr0_csv2;
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u8 pfr0_csv3;
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struct {
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u8 imp:4;
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u8 unimp:4;
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} dfr0_pmuver;
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/* Hypercall features firmware registers' descriptor */
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struct kvm_smccc_features smccc_feat;
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@ -164,6 +164,12 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
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set_default_spectre(kvm);
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kvm_arm_init_hypercalls(kvm);
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/*
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* Initialise the default PMUver before there is a chance to
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* create an actual PMU.
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*/
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kvm->arch.dfr0_pmuver.imp = kvm_arm_pmu_get_pmuver_limit();
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return ret;
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out_free_stage2_pgd:
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kvm_free_stage2_pgd(&kvm->arch.mmu);
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@ -1047,3 +1047,14 @@ int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr)
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return -ENXIO;
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}
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u8 kvm_arm_pmu_get_pmuver_limit(void)
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{
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u64 tmp;
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tmp = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
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tmp = cpuid_feature_cap_perfmon_field(tmp,
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ID_AA64DFR0_EL1_PMUVer_SHIFT,
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ID_AA64DFR0_EL1_PMUVer_V3P4);
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return FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), tmp);
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}
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@ -1062,6 +1062,27 @@ static bool access_arch_timer(struct kvm_vcpu *vcpu,
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return true;
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}
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static u8 vcpu_pmuver(const struct kvm_vcpu *vcpu)
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{
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if (kvm_vcpu_has_pmu(vcpu))
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return vcpu->kvm->arch.dfr0_pmuver.imp;
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return vcpu->kvm->arch.dfr0_pmuver.unimp;
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}
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static u8 pmuver_to_perfmon(u8 pmuver)
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{
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switch (pmuver) {
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case ID_AA64DFR0_EL1_PMUVer_IMP:
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return ID_DFR0_PERFMON_8_0;
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case ID_AA64DFR0_EL1_PMUVer_IMP_DEF:
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return ID_DFR0_PERFMON_IMP_DEF;
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default:
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/* Anything ARMv8.1+ and NI have the same value. For now. */
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return pmuver;
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}
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}
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/* Read a sanitised cpufeature ID register by sys_reg_desc */
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static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r)
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{
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@ -1111,18 +1132,17 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r
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/* Limit debug to ARMv8.0 */
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val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer);
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val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), 6);
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/* Limit guests to PMUv3 for ARMv8.4 */
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val = cpuid_feature_cap_perfmon_field(val,
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ID_AA64DFR0_EL1_PMUVer_SHIFT,
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kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_EL1_PMUVer_V3P4 : 0);
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/* Set PMUver to the required version */
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val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
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val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer),
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vcpu_pmuver(vcpu));
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/* Hide SPE from guests */
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val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer);
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break;
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case SYS_ID_DFR0_EL1:
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/* Limit guests to PMUv3 for ARMv8.4 */
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val = cpuid_feature_cap_perfmon_field(val,
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ID_DFR0_PERFMON_SHIFT,
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kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0);
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val &= ~ARM64_FEATURE_MASK(ID_DFR0_PERFMON);
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val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_DFR0_PERFMON),
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pmuver_to_perfmon(vcpu_pmuver(vcpu)));
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break;
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}
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@ -89,6 +89,8 @@ void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu);
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vcpu->arch.pmu.events = *kvm_get_pmu_events(); \
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} while (0)
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u8 kvm_arm_pmu_get_pmuver_limit(void);
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#else
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struct kvm_pmu {
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};
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@ -154,6 +156,10 @@ static inline u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1)
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static inline void kvm_pmu_update_vcpu_events(struct kvm_vcpu *vcpu) {}
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static inline void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu) {}
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static inline void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu) {}
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static inline u8 kvm_arm_pmu_get_pmuver_limit(void)
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{
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return 0;
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}
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#endif
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