drm/amdkfd: Use generic defines in new amd headers
This patch makes use of the new amd headers (that are part of the new amdgpu driver), instead of private defines. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
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d7b8f73ea0
Коммит
3d30b28be8
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@ -65,17 +65,6 @@
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#define AQL_ENABLE 1
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#define SDMA_RB_VMID(x) (x << 24)
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#define SDMA_RB_ENABLE (1 << 0)
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#define SDMA_RB_SIZE(x) ((x) << 1) /* log2 */
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#define SDMA_RPTR_WRITEBACK_ENABLE (1 << 12)
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#define SDMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
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#define SDMA_OFFSET(x) (x << 0)
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#define SDMA_DB_ENABLE (1 << 28)
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#define SDMA_ATC (1 << 0)
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#define SDMA_VA_PTR32 (1 << 4)
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#define SDMA_VA_SHARED_BASE(x) (x << 8)
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#define GRBM_GFX_INDEX 0x30800
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#define ATC_VMID_PASID_MAPPING_VALID (1U << 31)
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@ -23,6 +23,7 @@
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#include "kfd_device_queue_manager.h"
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#include "cik_regs.h"
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#include "oss/oss_2_4_sh_mask.h"
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static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm,
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struct qcm_process_device *qpd,
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@ -135,13 +136,16 @@ static int register_process_cik(struct device_queue_manager *dqm,
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static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
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struct qcm_process_device *qpd)
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{
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uint32_t value = SDMA_ATC;
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uint32_t value = (1 << SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT);
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if (q->process->is_32bit_user_mode)
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value |= SDMA_VA_PTR32 | get_sh_mem_bases_32(qpd_to_pdd(qpd));
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value |= (1 << SDMA0_RLC0_VIRTUAL_ADDR__PTR32__SHIFT) |
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get_sh_mem_bases_32(qpd_to_pdd(qpd));
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else
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value |= SDMA_VA_SHARED_BASE(get_sh_mem_bases_nybble_64(
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qpd_to_pdd(qpd)));
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value |= ((get_sh_mem_bases_nybble_64(qpd_to_pdd(qpd))) <<
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SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT) &&
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SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK;
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q->properties.sdma_vm_addr = value;
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}
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@ -27,6 +27,7 @@
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#include "kfd_mqd_manager.h"
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#include "cik_regs.h"
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#include "cik_structs.h"
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#include "oss/oss_2_4_sh_mask.h"
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static inline struct cik_mqd *get_mqd(void *mqd)
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{
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@ -214,17 +215,20 @@ static int update_mqd_sdma(struct mqd_manager *mm, void *mqd,
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BUG_ON(!mm || !mqd || !q);
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m = get_sdma_mqd(mqd);
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m->sdma_rlc_rb_cntl =
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SDMA_RB_SIZE((ffs(q->queue_size / sizeof(unsigned int)))) |
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SDMA_RB_VMID(q->vmid) |
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SDMA_RPTR_WRITEBACK_ENABLE |
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SDMA_RPTR_WRITEBACK_TIMER(6);
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m->sdma_rlc_rb_cntl = ffs(q->queue_size / sizeof(unsigned int)) <<
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SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
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q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
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1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
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6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
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m->sdma_rlc_rb_base = lower_32_bits(q->queue_address >> 8);
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m->sdma_rlc_rb_base_hi = upper_32_bits(q->queue_address >> 8);
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m->sdma_rlc_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
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m->sdma_rlc_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
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m->sdma_rlc_doorbell = SDMA_OFFSET(q->doorbell_off) | SDMA_DB_ENABLE;
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m->sdma_rlc_doorbell = q->doorbell_off <<
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SDMA0_RLC0_DOORBELL__OFFSET__SHIFT |
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1 << SDMA0_RLC0_DOORBELL__ENABLE__SHIFT;
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m->sdma_rlc_virtual_addr = q->sdma_vm_addr;
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m->sdma_engine_id = q->sdma_engine_id;
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@ -234,7 +238,9 @@ static int update_mqd_sdma(struct mqd_manager *mm, void *mqd,
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if (q->queue_size > 0 &&
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q->queue_address != 0 &&
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q->queue_percent > 0) {
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m->sdma_rlc_rb_cntl |= SDMA_RB_ENABLE;
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m->sdma_rlc_rb_cntl |=
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1 << SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT;
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q->is_active = true;
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}
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