drivers/perf: hisi: Add PMU version for uncore PMU drivers.
For HiSilicon uncore PMU, more versions are supported and some variables shall be added suffix to distinguish the version which are prepared for the new drivers. Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will@kernel.org> Cc: John Garry <john.garry@huawei.com> Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: John Garry <john.garry@huawei.com> Co-developed-by: Qi Liu <liuqi115@huawei.com> Signed-off-by: Qi Liu <liuqi115@huawei.com> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com> Link: https://lore.kernel.org/r/1615186237-22263-4-git-send-email-zhangshaokun@hisilicon.com Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Shaokun Zhang
Will Deacon
Родитель
baff06c315
Коммит
3da582df57
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@ -36,7 +36,8 @@
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/* DDRC has 8-counters */
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#define DDRC_NR_COUNTERS 0x8
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#define DDRC_PERF_CTRL_EN 0x2
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#define DDRC_V1_PERF_CTRL_EN 0x2
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#define DDRC_V1_NR_EVENTS 0x7
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/*
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* For DDRC PMU, there are eight-events and every event has been mapped
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@ -53,26 +54,26 @@ static const u32 ddrc_reg_off[] = {
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/*
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* Select the counter register offset using the counter index.
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* In DDRC there are no programmable counter, the count
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* is readed form the statistics counter register itself.
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* In PMU v1, there are no programmable counter, the count
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* is read form the statistics counter register itself.
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*/
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static u32 hisi_ddrc_pmu_get_counter_offset(int cntr_idx)
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static u32 hisi_ddrc_pmu_v1_get_counter_offset(int cntr_idx)
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{
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return ddrc_reg_off[cntr_idx];
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}
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static u64 hisi_ddrc_pmu_read_counter(struct hisi_pmu *ddrc_pmu,
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static u64 hisi_ddrc_pmu_v1_read_counter(struct hisi_pmu *ddrc_pmu,
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struct hw_perf_event *hwc)
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{
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return readl(ddrc_pmu->base +
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hisi_ddrc_pmu_get_counter_offset(hwc->idx));
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hisi_ddrc_pmu_v1_get_counter_offset(hwc->idx));
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}
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static void hisi_ddrc_pmu_write_counter(struct hisi_pmu *ddrc_pmu,
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static void hisi_ddrc_pmu_v1_write_counter(struct hisi_pmu *ddrc_pmu,
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struct hw_perf_event *hwc, u64 val)
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{
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writel((u32)val,
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ddrc_pmu->base + hisi_ddrc_pmu_get_counter_offset(hwc->idx));
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ddrc_pmu->base + hisi_ddrc_pmu_v1_get_counter_offset(hwc->idx));
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}
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/*
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@ -84,27 +85,27 @@ static void hisi_ddrc_pmu_write_evtype(struct hisi_pmu *hha_pmu, int idx,
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{
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}
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static void hisi_ddrc_pmu_start_counters(struct hisi_pmu *ddrc_pmu)
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static void hisi_ddrc_pmu_v1_start_counters(struct hisi_pmu *ddrc_pmu)
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{
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u32 val;
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/* Set perf_enable in DDRC_PERF_CTRL to start event counting */
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val = readl(ddrc_pmu->base + DDRC_PERF_CTRL);
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val |= DDRC_PERF_CTRL_EN;
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val |= DDRC_V1_PERF_CTRL_EN;
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writel(val, ddrc_pmu->base + DDRC_PERF_CTRL);
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}
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static void hisi_ddrc_pmu_stop_counters(struct hisi_pmu *ddrc_pmu)
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static void hisi_ddrc_pmu_v1_stop_counters(struct hisi_pmu *ddrc_pmu)
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{
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u32 val;
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/* Clear perf_enable in DDRC_PERF_CTRL to stop event counting */
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val = readl(ddrc_pmu->base + DDRC_PERF_CTRL);
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val &= ~DDRC_PERF_CTRL_EN;
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val &= ~DDRC_V1_PERF_CTRL_EN;
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writel(val, ddrc_pmu->base + DDRC_PERF_CTRL);
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}
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static void hisi_ddrc_pmu_enable_counter(struct hisi_pmu *ddrc_pmu,
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static void hisi_ddrc_pmu_v1_enable_counter(struct hisi_pmu *ddrc_pmu,
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struct hw_perf_event *hwc)
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{
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u32 val;
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@ -115,7 +116,7 @@ static void hisi_ddrc_pmu_enable_counter(struct hisi_pmu *ddrc_pmu,
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writel(val, ddrc_pmu->base + DDRC_EVENT_CTRL);
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}
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static void hisi_ddrc_pmu_disable_counter(struct hisi_pmu *ddrc_pmu,
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static void hisi_ddrc_pmu_v1_disable_counter(struct hisi_pmu *ddrc_pmu,
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struct hw_perf_event *hwc)
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{
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u32 val;
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@ -126,7 +127,7 @@ static void hisi_ddrc_pmu_disable_counter(struct hisi_pmu *ddrc_pmu,
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writel(val, ddrc_pmu->base + DDRC_EVENT_CTRL);
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}
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static int hisi_ddrc_pmu_get_event_idx(struct perf_event *event)
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static int hisi_ddrc_pmu_v1_get_event_idx(struct perf_event *event)
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{
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struct hisi_pmu *ddrc_pmu = to_hisi_pmu(event->pmu);
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unsigned long *used_mask = ddrc_pmu->pmu_events.used_mask;
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@ -142,7 +143,7 @@ static int hisi_ddrc_pmu_get_event_idx(struct perf_event *event)
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return idx;
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}
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static void hisi_ddrc_pmu_enable_counter_int(struct hisi_pmu *ddrc_pmu,
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static void hisi_ddrc_pmu_v1_enable_counter_int(struct hisi_pmu *ddrc_pmu,
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struct hw_perf_event *hwc)
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{
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u32 val;
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@ -153,7 +154,7 @@ static void hisi_ddrc_pmu_enable_counter_int(struct hisi_pmu *ddrc_pmu,
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writel(val, ddrc_pmu->base + DDRC_INT_MASK);
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}
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static void hisi_ddrc_pmu_disable_counter_int(struct hisi_pmu *ddrc_pmu,
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static void hisi_ddrc_pmu_v1_disable_counter_int(struct hisi_pmu *ddrc_pmu,
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struct hw_perf_event *hwc)
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{
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u32 val;
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@ -164,12 +165,13 @@ static void hisi_ddrc_pmu_disable_counter_int(struct hisi_pmu *ddrc_pmu,
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writel(val, ddrc_pmu->base + DDRC_INT_MASK);
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}
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static u32 hisi_ddrc_pmu_get_int_status(struct hisi_pmu *ddrc_pmu)
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static u32 hisi_ddrc_pmu_v1_get_int_status(struct hisi_pmu *ddrc_pmu)
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{
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return readl(ddrc_pmu->base + DDRC_INT_STATUS);
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}
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static void hisi_ddrc_pmu_clear_int_status(struct hisi_pmu *ddrc_pmu, int idx)
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static void hisi_ddrc_pmu_v1_clear_int_status(struct hisi_pmu *ddrc_pmu,
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int idx)
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{
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writel(1 << idx, ddrc_pmu->base + DDRC_INT_CLEAR);
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}
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@ -212,17 +214,17 @@ static int hisi_ddrc_pmu_init_data(struct platform_device *pdev,
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return 0;
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}
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static struct attribute *hisi_ddrc_pmu_format_attr[] = {
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static struct attribute *hisi_ddrc_pmu_v1_format_attr[] = {
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HISI_PMU_FORMAT_ATTR(event, "config:0-4"),
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NULL,
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};
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static const struct attribute_group hisi_ddrc_pmu_format_group = {
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static const struct attribute_group hisi_ddrc_pmu_v1_format_group = {
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.name = "format",
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.attrs = hisi_ddrc_pmu_format_attr,
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.attrs = hisi_ddrc_pmu_v1_format_attr,
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};
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static struct attribute *hisi_ddrc_pmu_events_attr[] = {
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static struct attribute *hisi_ddrc_pmu_v1_events_attr[] = {
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HISI_PMU_EVENT_ATTR(flux_wr, 0x00),
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HISI_PMU_EVENT_ATTR(flux_rd, 0x01),
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HISI_PMU_EVENT_ATTR(flux_wcmd, 0x02),
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@ -234,9 +236,9 @@ static struct attribute *hisi_ddrc_pmu_events_attr[] = {
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NULL,
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};
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static const struct attribute_group hisi_ddrc_pmu_events_group = {
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static const struct attribute_group hisi_ddrc_pmu_v1_events_group = {
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.name = "events",
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.attrs = hisi_ddrc_pmu_events_attr,
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.attrs = hisi_ddrc_pmu_v1_events_attr,
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};
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static DEVICE_ATTR(cpumask, 0444, hisi_cpumask_sysfs_show, NULL);
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@ -262,27 +264,27 @@ static const struct attribute_group hisi_ddrc_pmu_identifier_group = {
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.attrs = hisi_ddrc_pmu_identifier_attrs,
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};
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static const struct attribute_group *hisi_ddrc_pmu_attr_groups[] = {
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&hisi_ddrc_pmu_format_group,
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&hisi_ddrc_pmu_events_group,
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static const struct attribute_group *hisi_ddrc_pmu_v1_attr_groups[] = {
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&hisi_ddrc_pmu_v1_format_group,
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&hisi_ddrc_pmu_v1_events_group,
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&hisi_ddrc_pmu_cpumask_attr_group,
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&hisi_ddrc_pmu_identifier_group,
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NULL,
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};
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static const struct hisi_uncore_ops hisi_uncore_ddrc_ops = {
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static const struct hisi_uncore_ops hisi_uncore_ddrc_v1_ops = {
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.write_evtype = hisi_ddrc_pmu_write_evtype,
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.get_event_idx = hisi_ddrc_pmu_get_event_idx,
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.start_counters = hisi_ddrc_pmu_start_counters,
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.stop_counters = hisi_ddrc_pmu_stop_counters,
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.enable_counter = hisi_ddrc_pmu_enable_counter,
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.disable_counter = hisi_ddrc_pmu_disable_counter,
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.enable_counter_int = hisi_ddrc_pmu_enable_counter_int,
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.disable_counter_int = hisi_ddrc_pmu_disable_counter_int,
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.write_counter = hisi_ddrc_pmu_write_counter,
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.read_counter = hisi_ddrc_pmu_read_counter,
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.get_int_status = hisi_ddrc_pmu_get_int_status,
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.clear_int_status = hisi_ddrc_pmu_clear_int_status,
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.get_event_idx = hisi_ddrc_pmu_v1_get_event_idx,
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.start_counters = hisi_ddrc_pmu_v1_start_counters,
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.stop_counters = hisi_ddrc_pmu_v1_stop_counters,
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.enable_counter = hisi_ddrc_pmu_v1_enable_counter,
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.disable_counter = hisi_ddrc_pmu_v1_disable_counter,
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.enable_counter_int = hisi_ddrc_pmu_v1_enable_counter_int,
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.disable_counter_int = hisi_ddrc_pmu_v1_disable_counter_int,
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.write_counter = hisi_ddrc_pmu_v1_write_counter,
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.read_counter = hisi_ddrc_pmu_v1_read_counter,
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.get_int_status = hisi_ddrc_pmu_v1_get_int_status,
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.clear_int_status = hisi_ddrc_pmu_v1_clear_int_status,
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};
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static int hisi_ddrc_pmu_dev_probe(struct platform_device *pdev,
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@ -300,10 +302,10 @@ static int hisi_ddrc_pmu_dev_probe(struct platform_device *pdev,
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ddrc_pmu->num_counters = DDRC_NR_COUNTERS;
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ddrc_pmu->counter_bits = 32;
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ddrc_pmu->ops = &hisi_uncore_ddrc_ops;
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ddrc_pmu->ops = &hisi_uncore_ddrc_v1_ops;
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ddrc_pmu->dev = &pdev->dev;
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ddrc_pmu->on_cpu = -1;
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ddrc_pmu->check_event = 7;
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ddrc_pmu->check_event = DDRC_V1_NR_EVENTS;
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return 0;
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}
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@ -345,7 +347,7 @@ static int hisi_ddrc_pmu_probe(struct platform_device *pdev)
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.start = hisi_uncore_pmu_start,
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.stop = hisi_uncore_pmu_stop,
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.read = hisi_uncore_pmu_read,
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.attr_groups = hisi_ddrc_pmu_attr_groups,
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.attr_groups = hisi_ddrc_pmu_v1_attr_groups,
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.capabilities = PERF_PMU_CAP_NO_EXCLUDE,
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};
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@ -33,10 +33,11 @@
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#define HHA_CNT0_LOWER 0x1F00
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/* HHA has 16-counters */
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#define HHA_NR_COUNTERS 0x10
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#define HHA_V1_NR_COUNTERS 0x10
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#define HHA_PERF_CTRL_EN 0x1
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#define HHA_EVTYPE_NONE 0xff
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#define HHA_V1_NR_EVENT 0x65
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/*
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* Select the counter register offset using the counter index
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@ -206,17 +207,17 @@ static int hisi_hha_pmu_init_data(struct platform_device *pdev,
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return 0;
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}
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static struct attribute *hisi_hha_pmu_format_attr[] = {
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static struct attribute *hisi_hha_pmu_v1_format_attr[] = {
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HISI_PMU_FORMAT_ATTR(event, "config:0-7"),
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NULL,
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};
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static const struct attribute_group hisi_hha_pmu_format_group = {
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static const struct attribute_group hisi_hha_pmu_v1_format_group = {
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.name = "format",
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.attrs = hisi_hha_pmu_format_attr,
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.attrs = hisi_hha_pmu_v1_format_attr,
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};
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static struct attribute *hisi_hha_pmu_events_attr[] = {
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static struct attribute *hisi_hha_pmu_v1_events_attr[] = {
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HISI_PMU_EVENT_ATTR(rx_ops_num, 0x00),
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HISI_PMU_EVENT_ATTR(rx_outer, 0x01),
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HISI_PMU_EVENT_ATTR(rx_sccl, 0x02),
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@ -246,9 +247,9 @@ static struct attribute *hisi_hha_pmu_events_attr[] = {
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NULL,
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};
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static const struct attribute_group hisi_hha_pmu_events_group = {
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static const struct attribute_group hisi_hha_pmu_v1_events_group = {
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.name = "events",
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.attrs = hisi_hha_pmu_events_attr,
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.attrs = hisi_hha_pmu_v1_events_attr,
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};
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static DEVICE_ATTR(cpumask, 0444, hisi_cpumask_sysfs_show, NULL);
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@ -274,9 +275,9 @@ static const struct attribute_group hisi_hha_pmu_identifier_group = {
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.attrs = hisi_hha_pmu_identifier_attrs,
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};
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static const struct attribute_group *hisi_hha_pmu_attr_groups[] = {
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&hisi_hha_pmu_format_group,
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&hisi_hha_pmu_events_group,
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static const struct attribute_group *hisi_hha_pmu_v1_attr_groups[] = {
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&hisi_hha_pmu_v1_format_group,
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&hisi_hha_pmu_v1_events_group,
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&hisi_hha_pmu_cpumask_attr_group,
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&hisi_hha_pmu_identifier_group,
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NULL,
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@ -310,12 +311,12 @@ static int hisi_hha_pmu_dev_probe(struct platform_device *pdev,
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if (ret)
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return ret;
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hha_pmu->num_counters = HHA_NR_COUNTERS;
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hha_pmu->num_counters = HHA_V1_NR_COUNTERS;
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hha_pmu->counter_bits = 48;
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hha_pmu->ops = &hisi_uncore_hha_ops;
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hha_pmu->dev = &pdev->dev;
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hha_pmu->on_cpu = -1;
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hha_pmu->check_event = 0x65;
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hha_pmu->check_event = HHA_V1_NR_EVENT;
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return 0;
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}
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@ -357,7 +358,7 @@ static int hisi_hha_pmu_probe(struct platform_device *pdev)
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.start = hisi_uncore_pmu_start,
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.stop = hisi_uncore_pmu_stop,
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.read = hisi_uncore_pmu_read,
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.attr_groups = hisi_hha_pmu_attr_groups,
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.attr_groups = hisi_hha_pmu_v1_attr_groups,
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.capabilities = PERF_PMU_CAP_NO_EXCLUDE,
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};
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@ -37,6 +37,7 @@
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#define L3C_PERF_CTRL_EN 0x10000
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#define L3C_EVTYPE_NONE 0xff
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#define L3C_V1_NR_EVENTS 0x59
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/*
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* Select the counter register offset using the counter index
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@ -209,17 +210,17 @@ static int hisi_l3c_pmu_init_data(struct platform_device *pdev,
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return 0;
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}
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static struct attribute *hisi_l3c_pmu_format_attr[] = {
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static struct attribute *hisi_l3c_pmu_v1_format_attr[] = {
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HISI_PMU_FORMAT_ATTR(event, "config:0-7"),
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NULL,
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};
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static const struct attribute_group hisi_l3c_pmu_format_group = {
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static const struct attribute_group hisi_l3c_pmu_v1_format_group = {
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.name = "format",
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.attrs = hisi_l3c_pmu_format_attr,
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.attrs = hisi_l3c_pmu_v1_format_attr,
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};
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static struct attribute *hisi_l3c_pmu_events_attr[] = {
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static struct attribute *hisi_l3c_pmu_v1_events_attr[] = {
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HISI_PMU_EVENT_ATTR(rd_cpipe, 0x00),
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HISI_PMU_EVENT_ATTR(wr_cpipe, 0x01),
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HISI_PMU_EVENT_ATTR(rd_hit_cpipe, 0x02),
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@ -236,9 +237,9 @@ static struct attribute *hisi_l3c_pmu_events_attr[] = {
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NULL,
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};
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||||
static const struct attribute_group hisi_l3c_pmu_events_group = {
|
||||
static const struct attribute_group hisi_l3c_pmu_v1_events_group = {
|
||||
.name = "events",
|
||||
.attrs = hisi_l3c_pmu_events_attr,
|
||||
.attrs = hisi_l3c_pmu_v1_events_attr,
|
||||
};
|
||||
|
||||
static DEVICE_ATTR(cpumask, 0444, hisi_cpumask_sysfs_show, NULL);
|
||||
|
|
@ -264,9 +265,9 @@ static const struct attribute_group hisi_l3c_pmu_identifier_group = {
|
|||
.attrs = hisi_l3c_pmu_identifier_attrs,
|
||||
};
|
||||
|
||||
static const struct attribute_group *hisi_l3c_pmu_attr_groups[] = {
|
||||
&hisi_l3c_pmu_format_group,
|
||||
&hisi_l3c_pmu_events_group,
|
||||
static const struct attribute_group *hisi_l3c_pmu_v1_attr_groups[] = {
|
||||
&hisi_l3c_pmu_v1_format_group,
|
||||
&hisi_l3c_pmu_v1_events_group,
|
||||
&hisi_l3c_pmu_cpumask_attr_group,
|
||||
&hisi_l3c_pmu_identifier_group,
|
||||
NULL,
|
||||
|
|
@ -305,7 +306,7 @@ static int hisi_l3c_pmu_dev_probe(struct platform_device *pdev,
|
|||
l3c_pmu->ops = &hisi_uncore_l3c_ops;
|
||||
l3c_pmu->dev = &pdev->dev;
|
||||
l3c_pmu->on_cpu = -1;
|
||||
l3c_pmu->check_event = 0x59;
|
||||
l3c_pmu->check_event = L3C_V1_NR_EVENTS;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -347,7 +348,7 @@ static int hisi_l3c_pmu_probe(struct platform_device *pdev)
|
|||
.start = hisi_uncore_pmu_start,
|
||||
.stop = hisi_uncore_pmu_stop,
|
||||
.read = hisi_uncore_pmu_read,
|
||||
.attr_groups = hisi_l3c_pmu_attr_groups,
|
||||
.attr_groups = hisi_l3c_pmu_v1_attr_groups,
|
||||
.capabilities = PERF_PMU_CAP_NO_EXCLUDE,
|
||||
};
|
||||
|
||||
|
|
|
|||
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