drm/amdgpu: allow get_vm_pde to change flags as well
And also provide the level for which we need a PDE. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -346,7 +346,8 @@ struct amdgpu_gart_funcs {
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uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
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uint32_t flags);
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/* get the pde for a given mc addr */
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u64 (*get_vm_pde)(struct amdgpu_device *adev, u64 addr);
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void (*get_vm_pde)(struct amdgpu_device *adev, int level,
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u64 *dst, u64 *flags);
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uint32_t (*get_invalidate_req)(unsigned int vm_id);
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};
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@ -1826,7 +1827,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
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#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
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#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
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#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
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#define amdgpu_gart_get_vm_pde(adev, addr) (adev)->gart.gart_funcs->get_vm_pde((adev), (addr))
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#define amdgpu_gart_get_vm_pde(adev, level, dst, flags) (adev)->gart.gart_funcs->get_vm_pde((adev), (level), (dst), (flags))
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#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
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#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
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#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
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@ -1070,9 +1070,10 @@ static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params,
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struct amdgpu_vm_pt *parent,
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struct amdgpu_vm_pt *entry)
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{
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struct amdgpu_bo *bo = entry->base.bo, *shadow = NULL;
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struct amdgpu_bo *bo = entry->base.bo, *shadow = NULL, *pbo;
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uint64_t pd_addr, shadow_addr = 0;
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uint64_t pde, pt;
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uint64_t pde, pt, flags;
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unsigned level;
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/* Don't update huge pages here */
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if (entry->huge)
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@ -1087,15 +1088,19 @@ static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params,
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shadow_addr = amdgpu_bo_gpu_offset(shadow);
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}
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for (level = 0, pbo = parent->base.bo->parent; pbo; ++level)
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pbo = pbo->parent;
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pt = amdgpu_bo_gpu_offset(bo);
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pt = amdgpu_gart_get_vm_pde(params->adev, pt);
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flags = AMDGPU_PTE_VALID;
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amdgpu_gart_get_vm_pde(params->adev, level, &pt, &flags);
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if (shadow) {
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pde = shadow_addr + (entry - parent->entries) * 8;
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params->func(params, pde, pt, 1, 0, AMDGPU_PTE_VALID);
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params->func(params, pde, pt, 1, 0, flags);
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}
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pde = pd_addr + (entry - parent->entries) * 8;
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params->func(params, pde, pt, 1, 0, AMDGPU_PTE_VALID);
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params->func(params, pde, pt, 1, 0, flags);
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}
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/*
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@ -1305,7 +1310,6 @@ static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p,
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!(flags & AMDGPU_PTE_VALID)) {
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dst = amdgpu_bo_gpu_offset(entry->base.bo);
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dst = amdgpu_gart_get_vm_pde(p->adev, dst);
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flags = AMDGPU_PTE_VALID;
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} else {
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/* Set the huge page flag to stop scanning at this PDE */
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@ -1314,9 +1318,11 @@ static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p,
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if (!entry->huge && !(flags & AMDGPU_PDE_PTE))
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return;
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entry->huge = !!(flags & AMDGPU_PDE_PTE);
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amdgpu_gart_get_vm_pde(p->adev, p->adev->vm_manager.num_level - 1,
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&dst, &flags);
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if (use_cpu_update) {
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/* In case a huge page is replaced with a system
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* memory mapping, p->pages_addr != NULL and
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@ -3686,10 +3686,11 @@ static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
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struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
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int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
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uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
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uint64_t flags = AMDGPU_PTE_VALID;
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unsigned eng = ring->vm_inv_eng;
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pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
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pd_addr |= AMDGPU_PTE_VALID;
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amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
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pd_addr |= flags;
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gfx_v9_0_write_data_to_reg(ring, usepfp, true,
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hub->ctx0_ptb_addr_lo32 + (2 * vm_id),
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@ -395,10 +395,10 @@ static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device *adev,
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return pte_flag;
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}
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static uint64_t gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr)
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static void gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, int level,
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uint64_t *addr, uint64_t *flags)
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{
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BUG_ON(addr & 0xFFFFFF0000000FFFULL);
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return addr;
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BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
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}
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static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
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@ -480,10 +480,10 @@ static uint64_t gmc_v7_0_get_vm_pte_flags(struct amdgpu_device *adev,
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return pte_flag;
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}
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static uint64_t gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr)
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static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level,
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uint64_t *addr, uint64_t *flags)
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{
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BUG_ON(addr & 0xFFFFFF0000000FFFULL);
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return addr;
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BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
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}
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/**
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@ -677,10 +677,10 @@ static uint64_t gmc_v8_0_get_vm_pte_flags(struct amdgpu_device *adev,
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return pte_flag;
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}
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static uint64_t gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr)
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static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level,
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uint64_t *addr, uint64_t *flags)
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{
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BUG_ON(addr & 0xFFFFFF0000000FFFULL);
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return addr;
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BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
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}
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/**
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@ -474,11 +474,13 @@ static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
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return pte_flag;
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}
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static u64 gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, u64 addr)
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static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
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uint64_t *addr, uint64_t *flags)
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{
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addr = adev->vm_manager.vram_base_offset + addr - adev->mc.vram_start;
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BUG_ON(addr & 0xFFFF00000000003FULL);
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return addr;
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if (!(*flags & AMDGPU_PDE_PTE))
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*addr = adev->vm_manager.vram_base_offset + *addr -
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adev->mc.vram_start;
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BUG_ON(*addr & 0xFFFF00000000003FULL);
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}
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static const struct amdgpu_gart_funcs gmc_v9_0_gart_funcs = {
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@ -1146,10 +1146,11 @@ static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
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{
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struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
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uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
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uint64_t flags = AMDGPU_PTE_VALID;
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unsigned eng = ring->vm_inv_eng;
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pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
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pd_addr |= AMDGPU_PTE_VALID;
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amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
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pd_addr |= flags;
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amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
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SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
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@ -1295,11 +1295,12 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
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{
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struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
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uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
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uint32_t data0, data1, mask;
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uint64_t flags = AMDGPU_PTE_VALID;
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unsigned eng = ring->vm_inv_eng;
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uint32_t data0, data1, mask;
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pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
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pd_addr |= AMDGPU_PTE_VALID;
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amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
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pd_addr |= flags;
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data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2;
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data1 = upper_32_bits(pd_addr);
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@ -1346,10 +1347,11 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
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{
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struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
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uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
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uint64_t flags = AMDGPU_PTE_VALID;
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unsigned eng = ring->vm_inv_eng;
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pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
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pd_addr |= AMDGPU_PTE_VALID;
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amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
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pd_addr |= flags;
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amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
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amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2);
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@ -969,10 +969,11 @@ static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring,
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{
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struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
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uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
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uint64_t flags = AMDGPU_PTE_VALID;
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unsigned eng = ring->vm_inv_eng;
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pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
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pd_addr |= AMDGPU_PTE_VALID;
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amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
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pd_addr |= flags;
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amdgpu_ring_write(ring, VCE_CMD_REG_WRITE);
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amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2);
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@ -892,11 +892,12 @@ static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
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{
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struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
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uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
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uint32_t data0, data1, mask;
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uint64_t flags = AMDGPU_PTE_VALID;
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unsigned eng = ring->vm_inv_eng;
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uint32_t data0, data1, mask;
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pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
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pd_addr |= AMDGPU_PTE_VALID;
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amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
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pd_addr |= flags;
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data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2;
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data1 = upper_32_bits(pd_addr);
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@ -1024,10 +1025,11 @@ static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
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{
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struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
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uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
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uint64_t flags = AMDGPU_PTE_VALID;
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unsigned eng = ring->vm_inv_eng;
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pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
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pd_addr |= AMDGPU_PTE_VALID;
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amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
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pd_addr |= flags;
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amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
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amdgpu_ring_write(ring,
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