ath9k: Implement integer mode for AR9485
This fixes random disconnect. Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Vasanthakumar Thiagarajan
John W. Linville
Родитель
228bdfca9a
Коммит
3dfd7f6066
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@ -75,9 +75,18 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
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freq = centers.synth_center;
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if (freq < 4800) { /* 2 GHz, fractional mode */
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if (AR_SREV_9485(ah))
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channelSel = CHANSEL_2G_9485(freq);
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else
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if (AR_SREV_9485(ah)) {
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u32 chan_frac;
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/*
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* freq_ref = 40 / (refdiva >> amoderefsel); where refdiva=1 and amoderefsel=0
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* ndiv = ((chan_mhz * 4) / 3) / freq_ref;
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* chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
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*/
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channelSel = (freq * 4) / 120;
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chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
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channelSel = (channelSel << 17) | chan_frac;
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} else
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channelSel = CHANSEL_2G(freq);
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/* Set to 2G mode */
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bMode = 1;
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@ -676,42 +676,55 @@ unsigned long ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
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}
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EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
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#define DPLL2_KD_VAL 0x3D
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#define DPLL2_KI_VAL 0x06
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#define DPLL3_PHASE_SHIFT_VAL 0x1
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#define DPLL3_PHASE_SHIFT_VAL 0x1
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static void ath9k_hw_init_pll(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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u32 pll;
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if (AR_SREV_9485(ah)) {
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REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666);
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REG_WRITE(ah, AR_CH0_DDR_DPLL2, 0x19e82f01);
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REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
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AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL);
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/* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
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REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
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AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
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REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
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AR_CH0_DPLL2_KD, 0x40);
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REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
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AR_CH0_DPLL2_KI, 0x4);
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REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
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REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
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AR_CH0_BB_DPLL1_REFDIV, 0x5);
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REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
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AR_CH0_BB_DPLL1_NINI, 0x58);
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REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
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AR_CH0_BB_DPLL1_NFRAC, 0x0);
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REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
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AR_CH0_BB_DPLL2_OUTDIV, 0x1);
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REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
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AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
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REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
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AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
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/* program BB PLL phase_shift to 0x6 */
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REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
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AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
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REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
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AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
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udelay(1000);
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REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666);
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REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
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AR_CH0_DPLL2_KD, DPLL2_KD_VAL);
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REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
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AR_CH0_DPLL2_KI, DPLL2_KI_VAL);
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REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
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AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL);
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REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x142c);
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udelay(1000);
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}
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pll = ath9k_hw_compute_pll_control(ah, chan);
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REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
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if (AR_SREV_9485(ah))
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udelay(1000);
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/* Switch the core clock for ar9271 to 117Mhz */
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if (AR_SREV_9271(ah)) {
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udelay(500);
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@ -19,7 +19,6 @@
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#define CHANSEL_DIV 15
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#define CHANSEL_2G(_freq) (((_freq) * 0x10000) / CHANSEL_DIV)
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#define CHANSEL_2G_9485(_freq) ((((_freq) * 0x10000) - 215) / CHANSEL_DIV)
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#define CHANSEL_5G(_freq) (((_freq) * 0x8000) / CHANSEL_DIV)
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#define AR_PHY_BASE 0x9800
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@ -1086,14 +1086,35 @@ enum {
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#define AR_ENT_OTP 0x40d8
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#define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000
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#define AR_ENT_OTP_MPSD 0x00800000
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#define AR_CH0_BB_DPLL2 0x16184
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#define AR_CH0_BB_DPLL3 0x16188
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#define AR_CH0_DDR_DPLL2 0x16244
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#define AR_CH0_DDR_DPLL3 0x16248
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#define AR_CH0_DPLL2_KD 0x03F80000
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#define AR_CH0_DPLL2_KD_S 19
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#define AR_CH0_BB_DPLL1 0x16180
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#define AR_CH0_BB_DPLL1_REFDIV 0xF8000000
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#define AR_CH0_BB_DPLL1_REFDIV_S 27
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#define AR_CH0_BB_DPLL1_NINI 0x07FC0000
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#define AR_CH0_BB_DPLL1_NINI_S 18
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#define AR_CH0_BB_DPLL1_NFRAC 0x0003FFFF
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#define AR_CH0_BB_DPLL1_NFRAC_S 0
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#define AR_CH0_BB_DPLL2 0x16184
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#define AR_CH0_BB_DPLL2_LOCAL_PLL 0x40000000
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#define AR_CH0_BB_DPLL2_LOCAL_PLL_S 30
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#define AR_CH0_DPLL2_KI 0x3C000000
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#define AR_CH0_DPLL2_KI_S 26
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#define AR_CH0_DPLL2_KD 0x03F80000
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#define AR_CH0_DPLL2_KD_S 19
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#define AR_CH0_BB_DPLL2_EN_NEGTRIG 0x00040000
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#define AR_CH0_BB_DPLL2_EN_NEGTRIG_S 18
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#define AR_CH0_BB_DPLL2_PLL_PWD 0x00010000
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#define AR_CH0_BB_DPLL2_PLL_PWD_S 16
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#define AR_CH0_BB_DPLL2_OUTDIV 0x0000E000
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#define AR_CH0_BB_DPLL2_OUTDIV_S 13
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#define AR_CH0_BB_DPLL3 0x16188
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#define AR_CH0_BB_DPLL3_PHASE_SHIFT 0x3F800000
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#define AR_CH0_BB_DPLL3_PHASE_SHIFT_S 23
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#define AR_CH0_DDR_DPLL2 0x16244
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#define AR_CH0_DDR_DPLL3 0x16248
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#define AR_CH0_DPLL3_PHASE_SHIFT 0x3F800000
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#define AR_CH0_DPLL3_PHASE_SHIFT_S 23
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#define AR_PHY_CCA_NOM_VAL_2GHZ -118
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