[MIPS] IP27: Remove #if 0'ed code.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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3e0ba410a5
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@ -69,13 +69,6 @@ typedef s32 klconf_off_t;
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/*
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* Some IMPORTANT OFFSETS. These are the offsets on all NODES.
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*/
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#if 0
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#define RAMBASE 0
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#define ARCSSPB_OFF 0x1000 /* shift it to sys/arcs/spb.h */
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#define OFF_HWGRAPH 0
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#endif
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#define MAX_MODULE_ID 255
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#define SIZE_PAD 4096 /* 4k padding for structures */
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/*
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@ -164,10 +157,6 @@ typedef struct kl_config_hdr {
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#define KL_CONFIG_HDR(_nasid) ((kl_config_hdr_t *)(KLCONFIG_ADDR(_nasid)))
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#if 0
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#define KL_CONFIG_MALLOC_HDR(_nasid) \
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(KL_CONFIG_HDR(_nasid)->ch_malloc_hdr)
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#endif
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#define KL_CONFIG_INFO_OFFSET(_nasid) \
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(KL_CONFIG_HDR(_nasid)->ch_board_info)
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#define KL_CONFIG_INFO_SET_OFFSET(_nasid, _off) \
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@ -601,18 +590,6 @@ typedef struct klport_s {
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klconf_off_t port_offset;
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} klport_t;
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#if 0
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/*
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* This is very similar to the klport_s but instead of having a componant
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* offset it has a board offset.
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*/
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typedef struct klxbow_port_s {
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nasid_t port_nasid;
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unsigned char port_flag;
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klconf_off_t board_offset;
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} klxbow_port_t;
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#endif
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typedef struct klcpu_s { /* CPU */
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klinfo_t cpu_info;
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unsigned short cpu_prid; /* Processor PRID value */
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@ -486,22 +486,6 @@ typedef union h1_icrba_u {
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#define ICRBN_A_CERR_SHFT 54
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#define ICRBN_A_ERR_MASK 0x3ff
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#if 0 /* Disabled, this causes namespace polution and break allmodconfig */
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/*
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* Easy access macros.
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*/
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#define a_error icrba_fields_s.error
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#define a_ecode icrba_fields_s.ecode
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#define a_lnetuce icrba_fields_s.lnetuce
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#define a_mark icrba_fields_s.mark
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#define a_xerr icrba_fields_s.xerr
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#define a_sidn icrba_fields_s.sidn
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#define a_tnum icrba_fields_s.tnum
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#define a_addr icrba_fields_s.addr
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#define a_valid icrba_fields_s.valid
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#define a_iow icrba_fields_s.iow
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#endif
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#endif /* !__ASSEMBLY__ */
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#define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */
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@ -398,24 +398,6 @@ typedef u64 rtc_time_t;
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/* PI_RT_FILTER_CTRL mask and shift definitions */
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#if 0
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/*
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* XXX - This register's definition has changed, but it's only implemented
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* in Hub 2.
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*/
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#define PRFC_DROP_COUNT_SHFT 27
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#define PRFC_DROP_COUNT_MASK (UINT64_CAST 0x3ff << 27)
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#define PRFC_DROP_CTR_SHFT 18
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#define PRFC_DROP_CTR_MASK (UINT64_CAST 0x1ff << 18)
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#define PRFC_MASK_ENABLE_SHFT 10
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#define PRFC_MASK_ENABLE_MASK (UINT64_CAST 0x7f << 10)
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#define PRFC_MASK_CTR_SHFT 2
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#define PRFC_MASK_CTR_MASK (UINT64_CAST 0xff << 2)
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#define PRFC_OFFSET_SHFT 0
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#define PRFC_OFFSET_MASK (UINT64_CAST 3)
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#endif /* 0 */
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/*
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* Bits for NACK_CNT_A/B and NACK_CMP
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*/
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