PCI: Tidy up pci/probe.c comments
No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Bjorn Helgaas
Родитель
1291a0d504
Коммит
3e466e2d3a
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@ -69,8 +69,8 @@ static int find_anything(struct device *dev, void *data)
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}
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/*
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* Some device drivers need know if pci is initiated.
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* Basically, we think pci is not initiated when there
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* Some device drivers need know if PCI is initiated.
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* Basically, we think PCI is not initiated when there
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* is no device to be found on the pci_bus_type.
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*/
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int no_pci_devices(void)
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@ -116,12 +116,16 @@ static u64 pci_size(u64 base, u64 maxbase, u64 mask)
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if (!size)
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return 0;
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/* Get the lowest of them to find the decode size, and
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from that the extent. */
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/*
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* Get the lowest of them to find the decode size, and from that
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* the extent.
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*/
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size = (size & ~(size-1)) - 1;
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/* base == maxbase can be valid only if the BAR has
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already been programmed with all 1s. */
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/*
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* base == maxbase can be valid only if the BAR has already been
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* programmed with all 1s.
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*/
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if (base == maxbase && ((base | size) & mask) != mask)
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return 0;
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@ -164,7 +168,7 @@ static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
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#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
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/**
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* pci_read_base - read a PCI BAR
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* pci_read_base - Read a PCI BAR
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* @dev: the PCI device
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* @type: type of the BAR
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* @res: resource buffer to be filled in
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@ -764,7 +768,7 @@ static int pci_register_host_bridge(struct pci_host_bridge *bridge)
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bridge->bus = bus;
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/* temporarily move resources off the list */
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/* Temporarily move resources off the list */
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list_splice_init(&bridge->windows, &resources);
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bus->sysdata = bridge->sysdata;
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bus->msi = bridge->msi;
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@ -776,7 +780,7 @@ static int pci_register_host_bridge(struct pci_host_bridge *bridge)
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b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
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if (b) {
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/* If we already got to this bus through a different bridge, ignore it */
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/* Ignore it if we already got here via a different bridge */
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dev_dbg(&b->dev, "bus already known\n");
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err = -EEXIST;
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goto free;
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@ -869,9 +873,7 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
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int i;
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int ret;
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/*
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* Allocate a new bus, and inherit stuff from the parent..
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*/
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/* Allocate a new bus and inherit stuff from the parent */
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child = pci_alloc_bus(parent);
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if (!child)
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return NULL;
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@ -882,16 +884,14 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
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child->sysdata = parent->sysdata;
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child->bus_flags = parent->bus_flags;
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/* initialize some portions of the bus device, but don't register it
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* now as the parent is not properly set up yet.
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/*
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* Initialize some portions of the bus device, but don't register
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* it now as the parent is not properly set up yet.
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*/
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child->dev.class = &pcibus_class;
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dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
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/*
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* Set up the primary, secondary and subordinate
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* bus numbers.
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*/
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/* Set up the primary, secondary and subordinate bus numbers */
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child->number = child->busn_res.start = busnr;
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child->primary = parent->busn_res.start;
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child->busn_res.end = 0xff;
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@ -907,7 +907,7 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
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pci_set_bus_of_node(child);
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pci_set_bus_speed(child);
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/* Set up default resource pointers and names.. */
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/* Set up default resource pointers and names */
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for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
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child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
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child->resource[i]->name = child->name;
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@ -1022,8 +1022,10 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
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broken = 1;
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}
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/* Disable MasterAbortMode during probing to avoid reporting
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of bus errors (in some architectures) */
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/*
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* Disable Master-Abort Mode during probing to avoid reporting of
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* bus errors in some architectures.
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*/
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pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
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pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
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bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
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@ -1033,18 +1035,19 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
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if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
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!is_cardbus && !broken) {
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unsigned int cmax;
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/*
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* Bus already configured by firmware, process it in the first
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* pass and just note the configuration.
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* Bus already configured by firmware, process it in the
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* first pass and just note the configuration.
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*/
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if (pass)
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goto out;
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/*
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* The bus might already exist for two reasons: Either we are
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* rescanning the bus or the bus is reachable through more than
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* one bridge. The second case can happen with the i450NX
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* chipset.
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* The bus might already exist for two reasons: Either we
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* are rescanning the bus or the bus is reachable through
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* more than one bridge. The second case can happen with
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* the i450NX chipset.
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*/
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child = pci_find_bus(pci_domain_nr(bus), secondary);
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if (!child) {
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@ -1060,22 +1063,27 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
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if (cmax > subordinate)
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dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
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subordinate, cmax);
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/* subordinate should equal child->busn_res.end */
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/* Subordinate should equal child->busn_res.end */
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if (subordinate > max)
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max = subordinate;
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} else {
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/*
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* We need to assign a number to this bus which we always
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* do in the second pass.
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*/
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if (!pass) {
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if (pcibios_assign_all_busses() || broken || is_cardbus)
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/* Temporarily disable forwarding of the
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configuration cycles on all bridges in
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this bus segment to avoid possible
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conflicts in the second pass between two
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bridges programmed with overlapping
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bus ranges. */
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/*
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* Temporarily disable forwarding of the
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* configuration cycles on all bridges in
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* this bus segment to avoid possible
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* conflicts in the second pass between two
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* bridges programmed with overlapping bus
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* ranges.
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*/
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pci_write_config_dword(dev, PCI_PRIMARY_BUS,
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buses & ~0xffffff);
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goto out;
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@ -1084,9 +1092,11 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
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/* Clear errors */
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pci_write_config_word(dev, PCI_STATUS, 0xffff);
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/* Prevent assigning a bus number that already exists.
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* This can happen when a bridge is hot-plugged, so in
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* this case we only re-scan this bus. */
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/*
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* Prevent assigning a bus number that already exists.
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* This can happen when a bridge is hot-plugged, so in this
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* case we only re-scan this bus.
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*/
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child = pci_find_bus(pci_domain_nr(bus), max+1);
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if (!child) {
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child = pci_add_new_bus(bus, dev, max+1);
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@ -1113,19 +1123,18 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
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buses |= CARDBUS_LATENCY_TIMER << 24;
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}
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/*
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* We need to blast all three values with a single write.
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*/
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/* We need to blast all three values with a single write */
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pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
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if (!is_cardbus) {
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child->bridge_ctl = bctl;
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max = pci_scan_child_bus_extend(child, available_buses);
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} else {
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/*
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* For CardBus bridges, we leave 4 bus numbers
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* as cards with a PCI-to-PCI bridge can be
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* inserted later.
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* For CardBus bridges, we leave 4 bus numbers as
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* cards with a PCI-to-PCI bridge can be inserted
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* later.
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*/
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for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
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struct pci_bus *parent = bus;
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@ -1141,10 +1150,11 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
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parent = parent->parent;
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}
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if (j) {
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/*
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* Often, there are two cardbus bridges
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* -- try to leave one valid bus number
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* for each one.
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* Often, there are two CardBus
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* bridges -- try to leave one
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* valid bus number for each one.
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*/
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i /= 2;
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break;
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@ -1152,9 +1162,8 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
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}
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max += i;
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}
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/*
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* Set the subordinate bus number to its real value.
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*/
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/* Set subordinate bus number to its real value */
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pci_bus_update_busn_res_end(child, max);
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pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
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}
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@ -1295,7 +1304,7 @@ static void set_pcie_thunderbolt(struct pci_dev *dev)
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}
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/**
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* pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
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* pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
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* @dev: PCI device
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*
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* PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
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@ -1332,7 +1341,7 @@ static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
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}
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/**
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* pci_cfg_space_size - get the configuration space size of the PCI device.
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* pci_cfg_space_size - Get the configuration space size of the PCI device
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* @dev: PCI device
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*
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* Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
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@ -1398,7 +1407,7 @@ static void pci_msi_setup_pci_dev(struct pci_dev *dev)
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}
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/**
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* pci_intx_mask_broken - test PCI_COMMAND_INTX_DISABLE writability
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* pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
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* @dev: PCI device
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*
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* Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this
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@ -1426,11 +1435,11 @@ static int pci_intx_mask_broken(struct pci_dev *dev)
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}
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/**
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* pci_setup_device - fill in class and map information of a device
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* pci_setup_device - Fill in class and map information of a device
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* @dev: the device structure to fill
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*
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* Initialize the device structure with information about the device's
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* vendor,class,memory and IO-space addresses,IRQ lines etc.
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* vendor,class,memory and IO-space addresses, IRQ lines etc.
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* Called at initialisation of the PCI subsystem and by CardBus services.
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* Returns 0 on success and negative if unknown type of device (not normal,
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* bridge or CardBus).
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@ -1456,8 +1465,11 @@ int pci_setup_device(struct pci_dev *dev)
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set_pcie_port_type(dev);
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pci_dev_assign_slot(dev);
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/* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
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set this higher, assuming the system even supports it. */
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/*
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* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
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* set this higher, assuming the system even supports it.
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*/
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dev->dma_mask = 0xffffffff;
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dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
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@ -1471,10 +1483,10 @@ int pci_setup_device(struct pci_dev *dev)
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dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
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dev->vendor, dev->device, dev->hdr_type, dev->class);
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/* need to have dev->class ready */
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/* Need to have dev->class ready */
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dev->cfg_size = pci_cfg_space_size(dev);
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/* need to have dev->cfg_size ready */
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/* Need to have dev->cfg_size ready */
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set_pcie_thunderbolt(dev);
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/* "Unknown power state" */
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@ -1482,7 +1494,8 @@ int pci_setup_device(struct pci_dev *dev)
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/* Early fixups, before probing the BARs */
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pci_fixup_device(pci_fixup_early, dev);
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/* device class may be changed after fixup */
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/* Device class may be changed after fixup */
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class = dev->class >> 8;
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if (dev->non_compliant_bars) {
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@ -1553,9 +1566,12 @@ int pci_setup_device(struct pci_dev *dev)
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case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
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if (class != PCI_CLASS_BRIDGE_PCI)
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goto bad;
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/* The PCI-to-PCI bridge spec requires that subtractive
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decoding (i.e. transparent) bridge must have programming
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interface code of 0x01. */
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/*
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* The PCI-to-PCI bridge spec requires that subtractive
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* decoding (i.e. transparent) bridge must have programming
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* interface code of 0x01.
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*/
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pci_read_irq(dev);
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dev->transparent = ((dev->class & 0xff) == 1);
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pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
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@ -1772,6 +1788,7 @@ static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
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/* Initialize Advanced Error Capabilities and Control Register */
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pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
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reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
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/* Don't enable ECRC generation or checking if unsupported */
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if (!(reg32 & PCI_ERR_CAP_ECRC_GENC))
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reg32 &= ~PCI_ERR_CAP_ECRC_GENE;
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@ -1902,10 +1919,11 @@ static void pci_release_capabilities(struct pci_dev *dev)
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}
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/**
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* pci_release_dev - free a pci device structure when all users of it are finished.
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* pci_release_dev - Free a PCI device structure when all users of it are
|
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* finished
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* @dev: device that's been disconnected
|
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*
|
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* Will be called only by the device core when all users of this pci device are
|
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* Will be called only by the device core when all users of this PCI device are
|
||||
* done.
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||||
*/
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static void pci_release_dev(struct device *dev)
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@ -1993,7 +2011,7 @@ bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
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if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
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return false;
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/* some broken boards return 0 or ~0 if a slot is empty: */
|
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/* Some broken boards return 0 or ~0 if a slot is empty: */
|
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if (*l == 0xffffffff || *l == 0x00000000 ||
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*l == 0x0000ffff || *l == 0xffff0000)
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return false;
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|
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@ -2006,8 +2024,8 @@ bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
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EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
|
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|
||||
/*
|
||||
* Read the config data for a PCI device, sanity-check it
|
||||
* and fill in the dev structure...
|
||||
* Read the config data for a PCI device, sanity-check it,
|
||||
* and fill in the dev structure.
|
||||
*/
|
||||
static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
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{
|
||||
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@ -2073,7 +2091,7 @@ static void pci_init_capabilities(struct pci_dev *dev)
|
|||
}
|
||||
|
||||
/*
|
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* This is the equivalent of pci_host_bridge_msi_domain that acts on
|
||||
* This is the equivalent of pci_host_bridge_msi_domain() that acts on
|
||||
* devices. Firmware interfaces that can select the MSI domain on a
|
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* per-device basis should be called from here.
|
||||
*/
|
||||
|
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@ -2082,7 +2100,7 @@ static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
|
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struct irq_domain *d;
|
||||
|
||||
/*
|
||||
* If a domain has been set through the pcibios_add_device
|
||||
* If a domain has been set through the pcibios_add_device()
|
||||
* callback, then this is the one (platform code knows best).
|
||||
*/
|
||||
d = dev_get_msi_domain(&dev->dev);
|
||||
|
|
@ -2136,10 +2154,10 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
|
|||
/* Fix up broken headers */
|
||||
pci_fixup_device(pci_fixup_header, dev);
|
||||
|
||||
/* moved out from quirk header fixup code */
|
||||
/* Moved out from quirk header fixup code */
|
||||
pci_reassigndev_resource_alignment(dev);
|
||||
|
||||
/* Clear the state_saved flag. */
|
||||
/* Clear the state_saved flag */
|
||||
dev->state_saved = false;
|
||||
|
||||
/* Initialize various capabilities */
|
||||
|
|
@ -2156,7 +2174,7 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
|
|||
ret = pcibios_add_device(dev);
|
||||
WARN_ON(ret < 0);
|
||||
|
||||
/* Setup MSI irq domain */
|
||||
/* Set up MSI IRQ domain */
|
||||
pci_set_msi_domain(dev);
|
||||
|
||||
/* Notifier could use PCI capabilities */
|
||||
|
|
@ -2235,9 +2253,9 @@ static int only_one_child(struct pci_bus *bus)
|
|||
}
|
||||
|
||||
/**
|
||||
* pci_scan_slot - scan a PCI slot on a bus for devices.
|
||||
* pci_scan_slot - Scan a PCI slot on a bus for devices
|
||||
* @bus: PCI bus to scan
|
||||
* @devfn: slot number to scan (must have zero function.)
|
||||
* @devfn: slot number to scan (must have zero function)
|
||||
*
|
||||
* Scan a PCI slot on the specified PCI bus for devices, adding
|
||||
* discovered devices to the @bus->devices list. New devices
|
||||
|
|
@ -2268,7 +2286,7 @@ int pci_scan_slot(struct pci_bus *bus, int devfn)
|
|||
}
|
||||
}
|
||||
|
||||
/* only one slot has pcie device */
|
||||
/* Only one slot has PCIe device */
|
||||
if (bus->self && nr)
|
||||
pcie_aspm_init_link_state(bus->self);
|
||||
|
||||
|
|
@ -2317,7 +2335,9 @@ static void pcie_write_mps(struct pci_dev *dev, int mps)
|
|||
|
||||
if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
|
||||
dev->bus->self)
|
||||
/* For "Performance", the assumption is made that
|
||||
|
||||
/*
|
||||
* For "Performance", the assumption is made that
|
||||
* downstream communication will never be larger than
|
||||
* the MRRS. So, the MPS only needs to be configured
|
||||
* for the upstream communication. This being the case,
|
||||
|
|
@ -2341,20 +2361,23 @@ static void pcie_write_mrrs(struct pci_dev *dev)
|
|||
{
|
||||
int rc, mrrs;
|
||||
|
||||
/* In the "safe" case, do not configure the MRRS. There appear to be
|
||||
/*
|
||||
* In the "safe" case, do not configure the MRRS. There appear to be
|
||||
* issues with setting MRRS to 0 on a number of devices.
|
||||
*/
|
||||
if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
|
||||
return;
|
||||
|
||||
/* For Max performance, the MRRS must be set to the largest supported
|
||||
/*
|
||||
* For max performance, the MRRS must be set to the largest supported
|
||||
* value. However, it cannot be configured larger than the MPS the
|
||||
* device or the bus can support. This should already be properly
|
||||
* configured by a prior call to pcie_write_mps.
|
||||
* configured by a prior call to pcie_write_mps().
|
||||
*/
|
||||
mrrs = pcie_get_mps(dev);
|
||||
|
||||
/* MRRS is a R/W register. Invalid values can be written, but a
|
||||
/*
|
||||
* MRRS is a R/W register. Invalid values can be written, but a
|
||||
* subsequent read will verify if the value is acceptable or not.
|
||||
* If the MRRS value provided is not acceptable (e.g., too large),
|
||||
* shrink the value until it is acceptable to the HW.
|
||||
|
|
@ -2396,7 +2419,8 @@ static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
|
||||
/*
|
||||
* pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
|
||||
* parents then children fashion. If this changes, then this code will not
|
||||
* work as designed.
|
||||
*/
|
||||
|
|
@ -2410,7 +2434,8 @@ void pcie_bus_configure_settings(struct pci_bus *bus)
|
|||
if (!pci_is_pcie(bus->self))
|
||||
return;
|
||||
|
||||
/* FIXME - Peer to peer DMA is possible, though the endpoint would need
|
||||
/*
|
||||
* FIXME - Peer to peer DMA is possible, though the endpoint would need
|
||||
* to be aware of the MPS of the destination. To work around this,
|
||||
* simply force the MPS of the entire system to the smallest possible.
|
||||
*/
|
||||
|
|
@ -2464,7 +2489,7 @@ static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
|
|||
for (devfn = 0; devfn < 0x100; devfn += 8)
|
||||
pci_scan_slot(bus, devfn);
|
||||
|
||||
/* Reserve buses for SR-IOV capability. */
|
||||
/* Reserve buses for SR-IOV capability */
|
||||
used_buses = pci_iov_bus_range(bus);
|
||||
max += used_buses;
|
||||
|
||||
|
|
@ -2506,6 +2531,7 @@ static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
|
|||
unsigned int buses = 0;
|
||||
|
||||
if (!hotplug_bridges && normal_bridges == 1) {
|
||||
|
||||
/*
|
||||
* There is only one bridge on the bus (upstream
|
||||
* port) so it gets all available buses which it
|
||||
|
|
@ -2514,6 +2540,7 @@ static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
|
|||
*/
|
||||
buses = available_buses;
|
||||
} else if (dev->is_hotplug_bridge) {
|
||||
|
||||
/*
|
||||
* Distribute the extra buses between hotplug
|
||||
* bridges if any.
|
||||
|
|
@ -2572,8 +2599,8 @@ unsigned int pci_scan_child_bus(struct pci_bus *bus)
|
|||
EXPORT_SYMBOL_GPL(pci_scan_child_bus);
|
||||
|
||||
/**
|
||||
* pcibios_root_bridge_prepare - Platform-specific host bridge setup.
|
||||
* @bridge: Host bridge to set up.
|
||||
* pcibios_root_bridge_prepare - Platform-specific host bridge setup
|
||||
* @bridge: Host bridge to set up
|
||||
*
|
||||
* Default empty implementation. Replace with an architecture-specific setup
|
||||
* routine, if necessary.
|
||||
|
|
@ -2776,7 +2803,7 @@ struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
|
|||
EXPORT_SYMBOL(pci_scan_bus);
|
||||
|
||||
/**
|
||||
* pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
|
||||
* pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
|
||||
* @bridge: PCI bridge for the bus to scan
|
||||
*
|
||||
* Scan a PCI bus and child buses for new devices, add them,
|
||||
|
|
@ -2801,11 +2828,11 @@ unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
|
|||
}
|
||||
|
||||
/**
|
||||
* pci_rescan_bus - scan a PCI bus for devices.
|
||||
* pci_rescan_bus - Scan a PCI bus for devices
|
||||
* @bus: PCI bus to scan
|
||||
*
|
||||
* Scan a PCI bus and child buses for new devices, adds them,
|
||||
* and enables them.
|
||||
* Scan a PCI bus and child buses for new devices, add them,
|
||||
* and enable them.
|
||||
*
|
||||
* Returns the max number of subordinate bus discovered.
|
||||
*/
|
||||
|
|
|
|||
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