[SPARC64]: Convert SBUS over to generic iommu/strbuf structs.
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
Родитель
6687508809
Коммит
3e4d26508a
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@ -26,17 +26,9 @@
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#define MAP_BASE ((u32)0xc0000000)
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struct sbus_iommu {
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spinlock_t lock;
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struct iommu_arena arena;
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iopte_t *page_table;
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unsigned long strbuf_regs;
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unsigned long iommu_regs;
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unsigned long sbus_control_reg;
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volatile unsigned long strbuf_flushflag;
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struct sbus_info {
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struct iommu iommu;
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struct strbuf strbuf;
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};
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/* Offsets from iommu_regs */
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@ -52,16 +44,17 @@ struct sbus_iommu {
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#define IOMMU_DRAM_VALID (1UL << 30UL)
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static void __iommu_flushall(struct sbus_iommu *iommu)
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static void __iommu_flushall(struct iommu *iommu)
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{
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unsigned long tag = iommu->iommu_regs + IOMMU_TAGDIAG;
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unsigned long tag;
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int entry;
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tag = iommu->iommu_control + (IOMMU_TAGDIAG - IOMMU_CONTROL);
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for (entry = 0; entry < 16; entry++) {
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upa_writeq(0, tag);
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tag += 8UL;
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}
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upa_readq(iommu->sbus_control_reg);
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upa_readq(iommu->write_complete_reg);
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}
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/* Offsets from strbuf_regs */
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@ -76,15 +69,14 @@ static void __iommu_flushall(struct sbus_iommu *iommu)
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#define STRBUF_TAG_VALID 0x02UL
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static void sbus_strbuf_flush(struct sbus_iommu *iommu, u32 base, unsigned long npages, int direction)
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static void sbus_strbuf_flush(struct iommu *iommu, struct strbuf *strbuf, u32 base, unsigned long npages, int direction)
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{
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unsigned long n;
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int limit;
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n = npages;
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while (n--)
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upa_writeq(base + (n << IO_PAGE_SHIFT),
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iommu->strbuf_regs + STRBUF_PFLUSH);
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upa_writeq(base + (n << IO_PAGE_SHIFT), strbuf->strbuf_pflush);
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/* If the device could not have possibly put dirty data into
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* the streaming cache, no flush-flag synchronization needs
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@ -93,15 +85,14 @@ static void sbus_strbuf_flush(struct sbus_iommu *iommu, u32 base, unsigned long
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if (direction == SBUS_DMA_TODEVICE)
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return;
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iommu->strbuf_flushflag = 0UL;
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*(strbuf->strbuf_flushflag) = 0UL;
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/* Whoopee cushion! */
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upa_writeq(__pa(&iommu->strbuf_flushflag),
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iommu->strbuf_regs + STRBUF_FSYNC);
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upa_readq(iommu->sbus_control_reg);
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upa_writeq(strbuf->strbuf_flushflag_pa, strbuf->strbuf_fsync);
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upa_readq(iommu->write_complete_reg);
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limit = 100000;
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while (iommu->strbuf_flushflag == 0UL) {
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while (*(strbuf->strbuf_flushflag) == 0UL) {
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limit--;
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if (!limit)
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break;
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@ -115,7 +106,7 @@ static void sbus_strbuf_flush(struct sbus_iommu *iommu, u32 base, unsigned long
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}
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/* Based largely upon the ppc64 iommu allocator. */
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static long sbus_arena_alloc(struct sbus_iommu *iommu, unsigned long npages)
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static long sbus_arena_alloc(struct iommu *iommu, unsigned long npages)
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{
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struct iommu_arena *arena = &iommu->arena;
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unsigned long n, i, start, end, limit;
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@ -164,7 +155,7 @@ static void sbus_arena_free(struct iommu_arena *arena, unsigned long base, unsig
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__clear_bit(i, arena->map);
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}
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static void sbus_iommu_table_init(struct sbus_iommu *iommu, unsigned int tsbsize)
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static void sbus_iommu_table_init(struct iommu *iommu, unsigned int tsbsize)
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{
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unsigned long tsbbase, order, sz, num_tsb_entries;
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@ -172,13 +163,14 @@ static void sbus_iommu_table_init(struct sbus_iommu *iommu, unsigned int tsbsize
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/* Setup initial software IOMMU state. */
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spin_lock_init(&iommu->lock);
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iommu->page_table_map_base = MAP_BASE;
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/* Allocate and initialize the free area map. */
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sz = num_tsb_entries / 8;
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sz = (sz + 7UL) & ~7UL;
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iommu->arena.map = kzalloc(sz, GFP_KERNEL);
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if (!iommu->arena.map) {
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prom_printf("PCI_IOMMU: Error, kmalloc(arena.map) failed.\n");
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prom_printf("SBUS_IOMMU: Error, kmalloc(arena.map) failed.\n");
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prom_halt();
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}
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iommu->arena.limit = num_tsb_entries;
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@ -194,7 +186,7 @@ static void sbus_iommu_table_init(struct sbus_iommu *iommu, unsigned int tsbsize
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memset(iommu->page_table, 0, tsbsize);
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}
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static inline iopte_t *alloc_npages(struct sbus_iommu *iommu, unsigned long npages)
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static inline iopte_t *alloc_npages(struct iommu *iommu, unsigned long npages)
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{
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long entry;
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@ -205,14 +197,15 @@ static inline iopte_t *alloc_npages(struct sbus_iommu *iommu, unsigned long npag
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return iommu->page_table + entry;
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}
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static inline void free_npages(struct sbus_iommu *iommu, dma_addr_t base, unsigned long npages)
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static inline void free_npages(struct iommu *iommu, dma_addr_t base, unsigned long npages)
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{
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sbus_arena_free(&iommu->arena, base >> IO_PAGE_SHIFT, npages);
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}
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void *sbus_alloc_consistent(struct sbus_dev *sdev, size_t size, dma_addr_t *dvma_addr)
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{
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struct sbus_iommu *iommu;
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struct sbus_info *info;
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struct iommu *iommu;
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iopte_t *iopte;
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unsigned long flags, order, first_page;
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void *ret;
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@ -228,7 +221,8 @@ void *sbus_alloc_consistent(struct sbus_dev *sdev, size_t size, dma_addr_t *dvma
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return NULL;
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memset((char *)first_page, 0, PAGE_SIZE << order);
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iommu = sdev->bus->iommu;
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info = sdev->bus->iommu;
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iommu = &info->iommu;
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spin_lock_irqsave(&iommu->lock, flags);
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iopte = alloc_npages(iommu, size >> IO_PAGE_SHIFT);
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@ -239,7 +233,7 @@ void *sbus_alloc_consistent(struct sbus_dev *sdev, size_t size, dma_addr_t *dvma
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return NULL;
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}
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*dvma_addr = (MAP_BASE +
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*dvma_addr = (iommu->page_table_map_base +
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((iopte - iommu->page_table) << IO_PAGE_SHIFT));
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ret = (void *) first_page;
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npages = size >> IO_PAGE_SHIFT;
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@ -257,18 +251,20 @@ void *sbus_alloc_consistent(struct sbus_dev *sdev, size_t size, dma_addr_t *dvma
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void sbus_free_consistent(struct sbus_dev *sdev, size_t size, void *cpu, dma_addr_t dvma)
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{
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struct sbus_iommu *iommu;
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struct sbus_info *info;
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struct iommu *iommu;
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iopte_t *iopte;
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unsigned long flags, order, npages;
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npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
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iommu = sdev->bus->iommu;
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info = sdev->bus->iommu;
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iommu = &info->iommu;
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iopte = iommu->page_table +
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((dvma - MAP_BASE) >> IO_PAGE_SHIFT);
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((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
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spin_lock_irqsave(&iommu->lock, flags);
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free_npages(iommu, dvma - MAP_BASE, npages);
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free_npages(iommu, dvma - iommu->page_table_map_base, npages);
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spin_unlock_irqrestore(&iommu->lock, flags);
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@ -279,14 +275,16 @@ void sbus_free_consistent(struct sbus_dev *sdev, size_t size, void *cpu, dma_add
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dma_addr_t sbus_map_single(struct sbus_dev *sdev, void *ptr, size_t sz, int direction)
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{
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struct sbus_iommu *iommu;
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struct sbus_info *info;
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struct iommu *iommu;
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iopte_t *base;
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unsigned long flags, npages, oaddr;
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unsigned long i, base_paddr;
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u32 bus_addr, ret;
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unsigned long iopte_protection;
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iommu = sdev->bus->iommu;
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info = sdev->bus->iommu;
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iommu = &info->iommu;
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if (unlikely(direction == SBUS_DMA_NONE))
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BUG();
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@ -302,7 +300,7 @@ dma_addr_t sbus_map_single(struct sbus_dev *sdev, void *ptr, size_t sz, int dire
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if (unlikely(!base))
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BUG();
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bus_addr = (MAP_BASE +
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bus_addr = (iommu->page_table_map_base +
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((base - iommu->page_table) << IO_PAGE_SHIFT));
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ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
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base_paddr = __pa(oaddr & IO_PAGE_MASK);
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@ -319,7 +317,9 @@ dma_addr_t sbus_map_single(struct sbus_dev *sdev, void *ptr, size_t sz, int dire
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void sbus_unmap_single(struct sbus_dev *sdev, dma_addr_t bus_addr, size_t sz, int direction)
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{
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struct sbus_iommu *iommu = sdev->bus->iommu;
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struct sbus_info *info = sdev->bus->iommu;
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struct iommu *iommu = &info->iommu;
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struct strbuf *strbuf = &info->strbuf;
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iopte_t *base;
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unsigned long flags, npages, i;
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@ -329,15 +329,15 @@ void sbus_unmap_single(struct sbus_dev *sdev, dma_addr_t bus_addr, size_t sz, in
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npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
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npages >>= IO_PAGE_SHIFT;
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base = iommu->page_table +
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((bus_addr - MAP_BASE) >> IO_PAGE_SHIFT);
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((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
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bus_addr &= IO_PAGE_MASK;
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spin_lock_irqsave(&iommu->lock, flags);
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sbus_strbuf_flush(iommu, bus_addr, npages, direction);
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sbus_strbuf_flush(iommu, strbuf, bus_addr, npages, direction);
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for (i = 0; i < npages; i++)
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iopte_val(base[i]) = 0UL;
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free_npages(iommu, bus_addr - MAP_BASE, npages);
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free_npages(iommu, bus_addr - iommu->page_table_map_base, npages);
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spin_unlock_irqrestore(&iommu->lock, flags);
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}
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@ -419,7 +419,8 @@ static inline void fill_sg(iopte_t *iopte, struct scatterlist *sg,
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int sbus_map_sg(struct sbus_dev *sdev, struct scatterlist *sglist, int nelems, int direction)
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{
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struct sbus_iommu *iommu;
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struct sbus_info *info;
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struct iommu *iommu;
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unsigned long flags, npages, iopte_protection;
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iopte_t *base;
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u32 dma_base;
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@ -436,7 +437,8 @@ int sbus_map_sg(struct sbus_dev *sdev, struct scatterlist *sglist, int nelems, i
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return 1;
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}
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iommu = sdev->bus->iommu;
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info = sdev->bus->iommu;
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iommu = &info->iommu;
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if (unlikely(direction == SBUS_DMA_NONE))
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BUG();
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@ -450,7 +452,7 @@ int sbus_map_sg(struct sbus_dev *sdev, struct scatterlist *sglist, int nelems, i
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if (unlikely(base == NULL))
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BUG();
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dma_base = MAP_BASE +
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dma_base = iommu->page_table_map_base +
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((base - iommu->page_table) << IO_PAGE_SHIFT);
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/* Normalize DVMA addresses. */
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@ -479,7 +481,9 @@ int sbus_map_sg(struct sbus_dev *sdev, struct scatterlist *sglist, int nelems, i
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void sbus_unmap_sg(struct sbus_dev *sdev, struct scatterlist *sglist, int nelems, int direction)
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{
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struct sbus_iommu *iommu;
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struct sbus_info *info;
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struct iommu *iommu;
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struct strbuf *strbuf;
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iopte_t *base;
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unsigned long flags, i, npages;
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u32 bus_addr;
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@ -487,7 +491,9 @@ void sbus_unmap_sg(struct sbus_dev *sdev, struct scatterlist *sglist, int nelems
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if (unlikely(direction == SBUS_DMA_NONE))
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BUG();
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iommu = sdev->bus->iommu;
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info = sdev->bus->iommu;
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iommu = &info->iommu;
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strbuf = &info->strbuf;
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bus_addr = sglist->dma_address & IO_PAGE_MASK;
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@ -499,29 +505,33 @@ void sbus_unmap_sg(struct sbus_dev *sdev, struct scatterlist *sglist, int nelems
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bus_addr) >> IO_PAGE_SHIFT;
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base = iommu->page_table +
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((bus_addr - MAP_BASE) >> IO_PAGE_SHIFT);
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((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
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spin_lock_irqsave(&iommu->lock, flags);
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sbus_strbuf_flush(iommu, bus_addr, npages, direction);
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sbus_strbuf_flush(iommu, strbuf, bus_addr, npages, direction);
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for (i = 0; i < npages; i++)
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iopte_val(base[i]) = 0UL;
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free_npages(iommu, bus_addr - MAP_BASE, npages);
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free_npages(iommu, bus_addr - iommu->page_table_map_base, npages);
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spin_unlock_irqrestore(&iommu->lock, flags);
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}
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void sbus_dma_sync_single_for_cpu(struct sbus_dev *sdev, dma_addr_t bus_addr, size_t sz, int direction)
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{
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struct sbus_iommu *iommu;
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struct sbus_info *info;
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struct iommu *iommu;
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struct strbuf *strbuf;
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unsigned long flags, npages;
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iommu = sdev->bus->iommu;
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info = sdev->bus->iommu;
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iommu = &info->iommu;
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strbuf = &info->strbuf;
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npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
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npages >>= IO_PAGE_SHIFT;
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bus_addr &= IO_PAGE_MASK;
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spin_lock_irqsave(&iommu->lock, flags);
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sbus_strbuf_flush(iommu, bus_addr, npages, direction);
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sbus_strbuf_flush(iommu, strbuf, bus_addr, npages, direction);
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spin_unlock_irqrestore(&iommu->lock, flags);
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}
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@ -531,11 +541,15 @@ void sbus_dma_sync_single_for_device(struct sbus_dev *sdev, dma_addr_t base, siz
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void sbus_dma_sync_sg_for_cpu(struct sbus_dev *sdev, struct scatterlist *sglist, int nelems, int direction)
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{
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struct sbus_iommu *iommu;
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struct sbus_info *info;
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struct iommu *iommu;
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struct strbuf *strbuf;
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unsigned long flags, npages, i;
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u32 bus_addr;
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iommu = sdev->bus->iommu;
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info = sdev->bus->iommu;
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iommu = &info->iommu;
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strbuf = &info->strbuf;
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bus_addr = sglist[0].dma_address & IO_PAGE_MASK;
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for (i = 0; i < nelems; i++) {
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@ -547,7 +561,7 @@ void sbus_dma_sync_sg_for_cpu(struct sbus_dev *sdev, struct scatterlist *sglist,
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- bus_addr) >> IO_PAGE_SHIFT;
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spin_lock_irqsave(&iommu->lock, flags);
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sbus_strbuf_flush(iommu, bus_addr, npages, direction);
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sbus_strbuf_flush(iommu, strbuf, bus_addr, npages, direction);
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spin_unlock_irqrestore(&iommu->lock, flags);
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}
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@ -558,12 +572,13 @@ void sbus_dma_sync_sg_for_device(struct sbus_dev *sdev, struct scatterlist *sg,
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/* Enable 64-bit DVMA mode for the given device. */
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void sbus_set_sbus64(struct sbus_dev *sdev, int bursts)
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{
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struct sbus_iommu *iommu = sdev->bus->iommu;
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struct sbus_info *info = sdev->bus->iommu;
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struct iommu *iommu = &info->iommu;
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int slot = sdev->slot;
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unsigned long cfg_reg;
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u64 val;
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cfg_reg = iommu->sbus_control_reg;
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cfg_reg = iommu->write_complete_reg;
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switch (slot) {
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case 0:
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cfg_reg += 0x20UL;
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@ -698,8 +713,9 @@ static unsigned long sysio_imap_to_iclr(unsigned long imap)
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unsigned int sbus_build_irq(void *buscookie, unsigned int ino)
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{
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struct sbus_bus *sbus = (struct sbus_bus *)buscookie;
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struct sbus_iommu *iommu = sbus->iommu;
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unsigned long reg_base = iommu->sbus_control_reg - 0x2000UL;
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struct sbus_info *info = sbus->iommu;
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struct iommu *iommu = &info->iommu;
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unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
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unsigned long imap, iclr;
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int sbus_level = 0;
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@ -760,8 +776,9 @@ unsigned int sbus_build_irq(void *buscookie, unsigned int ino)
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static irqreturn_t sysio_ue_handler(int irq, void *dev_id)
|
||||
{
|
||||
struct sbus_bus *sbus = dev_id;
|
||||
struct sbus_iommu *iommu = sbus->iommu;
|
||||
unsigned long reg_base = iommu->sbus_control_reg - 0x2000UL;
|
||||
struct sbus_info *info = sbus->iommu;
|
||||
struct iommu *iommu = &info->iommu;
|
||||
unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
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unsigned long afsr_reg, afar_reg;
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unsigned long afsr, afar, error_bits;
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int reported;
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@ -832,8 +849,9 @@ static irqreturn_t sysio_ue_handler(int irq, void *dev_id)
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static irqreturn_t sysio_ce_handler(int irq, void *dev_id)
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{
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struct sbus_bus *sbus = dev_id;
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struct sbus_iommu *iommu = sbus->iommu;
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unsigned long reg_base = iommu->sbus_control_reg - 0x2000UL;
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struct sbus_info *info = sbus->iommu;
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struct iommu *iommu = &info->iommu;
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unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
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unsigned long afsr_reg, afar_reg;
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unsigned long afsr, afar, error_bits;
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int reported;
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@ -909,12 +927,13 @@ static irqreturn_t sysio_ce_handler(int irq, void *dev_id)
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static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id)
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{
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struct sbus_bus *sbus = dev_id;
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struct sbus_iommu *iommu = sbus->iommu;
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struct sbus_info *info = sbus->iommu;
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struct iommu *iommu = &info->iommu;
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unsigned long afsr_reg, afar_reg, reg_base;
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unsigned long afsr, afar, error_bits;
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int reported;
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reg_base = iommu->sbus_control_reg - 0x2000UL;
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reg_base = iommu->write_complete_reg - 0x2000UL;
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afsr_reg = reg_base + SYSIO_SBUS_AFSR;
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afar_reg = reg_base + SYSIO_SBUS_AFAR;
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@ -976,8 +995,9 @@ static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id)
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|
||||
static void __init sysio_register_error_handlers(struct sbus_bus *sbus)
|
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{
|
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struct sbus_iommu *iommu = sbus->iommu;
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unsigned long reg_base = iommu->sbus_control_reg - 0x2000UL;
|
||||
struct sbus_info *info = sbus->iommu;
|
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struct iommu *iommu = &info->iommu;
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unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
|
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unsigned int irq;
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u64 control;
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|
||||
|
|
@ -1011,9 +1031,9 @@ static void __init sysio_register_error_handlers(struct sbus_bus *sbus)
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|||
SYSIO_ECNTRL_CEEN),
|
||||
reg_base + ECC_CONTROL);
|
||||
|
||||
control = upa_readq(iommu->sbus_control_reg);
|
||||
control = upa_readq(iommu->write_complete_reg);
|
||||
control |= 0x100UL; /* SBUS Error Interrupt Enable */
|
||||
upa_writeq(control, iommu->sbus_control_reg);
|
||||
upa_writeq(control, iommu->write_complete_reg);
|
||||
}
|
||||
|
||||
/* Boot time initialization. */
|
||||
|
|
@ -1021,8 +1041,10 @@ static void __init sbus_iommu_init(int __node, struct sbus_bus *sbus)
|
|||
{
|
||||
const struct linux_prom64_registers *pr;
|
||||
struct device_node *dp;
|
||||
struct sbus_iommu *iommu;
|
||||
unsigned long regs;
|
||||
struct sbus_info *info;
|
||||
struct iommu *iommu;
|
||||
struct strbuf *strbuf;
|
||||
unsigned long regs, reg_base;
|
||||
u64 control;
|
||||
int i;
|
||||
|
||||
|
|
@ -1037,33 +1059,42 @@ static void __init sbus_iommu_init(int __node, struct sbus_bus *sbus)
|
|||
}
|
||||
regs = pr->phys_addr;
|
||||
|
||||
iommu = kmalloc(sizeof(*iommu) + SMP_CACHE_BYTES, GFP_ATOMIC);
|
||||
if (iommu == NULL) {
|
||||
prom_printf("sbus_iommu_init: Fatal error, kmalloc(iommu) failed\n");
|
||||
info = kzalloc(sizeof(*info), GFP_ATOMIC);
|
||||
if (info == NULL) {
|
||||
prom_printf("sbus_iommu_init: Fatal error, "
|
||||
"kmalloc(info) failed\n");
|
||||
prom_halt();
|
||||
}
|
||||
|
||||
/* Align on E$ line boundary. */
|
||||
iommu = (struct sbus_iommu *)
|
||||
(((unsigned long)iommu + (SMP_CACHE_BYTES - 1UL)) &
|
||||
~(SMP_CACHE_BYTES - 1UL));
|
||||
iommu = &info->iommu;
|
||||
strbuf = &info->strbuf;
|
||||
|
||||
memset(iommu, 0, sizeof(*iommu));
|
||||
reg_base = regs + SYSIO_IOMMUREG_BASE;
|
||||
iommu->iommu_control = reg_base + IOMMU_CONTROL;
|
||||
iommu->iommu_tsbbase = reg_base + IOMMU_TSBBASE;
|
||||
iommu->iommu_flush = reg_base + IOMMU_FLUSH;
|
||||
|
||||
/* Setup spinlock. */
|
||||
spin_lock_init(&iommu->lock);
|
||||
reg_base = regs + SYSIO_STRBUFREG_BASE;
|
||||
strbuf->strbuf_control = reg_base + STRBUF_CONTROL;
|
||||
strbuf->strbuf_pflush = reg_base + STRBUF_PFLUSH;
|
||||
strbuf->strbuf_fsync = reg_base + STRBUF_FSYNC;
|
||||
|
||||
/* Init register offsets. */
|
||||
iommu->iommu_regs = regs + SYSIO_IOMMUREG_BASE;
|
||||
iommu->strbuf_regs = regs + SYSIO_STRBUFREG_BASE;
|
||||
strbuf->strbuf_enabled = 1;
|
||||
|
||||
strbuf->strbuf_flushflag = (volatile unsigned long *)
|
||||
((((unsigned long)&strbuf->__flushflag_buf[0])
|
||||
+ 63UL)
|
||||
& ~63UL);
|
||||
strbuf->strbuf_flushflag_pa = (unsigned long)
|
||||
__pa(strbuf->strbuf_flushflag);
|
||||
|
||||
/* The SYSIO SBUS control register is used for dummy reads
|
||||
* in order to ensure write completion.
|
||||
*/
|
||||
iommu->sbus_control_reg = regs + 0x2000UL;
|
||||
iommu->write_complete_reg = regs + 0x2000UL;
|
||||
|
||||
/* Link into SYSIO software state. */
|
||||
sbus->iommu = iommu;
|
||||
sbus->iommu = info;
|
||||
|
||||
printk("SYSIO: UPA portID %x, at %016lx\n",
|
||||
sbus->portid, regs);
|
||||
|
|
@ -1071,40 +1102,44 @@ static void __init sbus_iommu_init(int __node, struct sbus_bus *sbus)
|
|||
/* Setup for TSB_SIZE=7, TBW_SIZE=0, MMU_DE=1, MMU_EN=1 */
|
||||
sbus_iommu_table_init(iommu, IO_TSB_SIZE);
|
||||
|
||||
control = upa_readq(iommu->iommu_regs + IOMMU_CONTROL);
|
||||
control = upa_readq(iommu->iommu_control);
|
||||
control = ((7UL << 16UL) |
|
||||
(0UL << 2UL) |
|
||||
(1UL << 1UL) |
|
||||
(1UL << 0UL));
|
||||
upa_writeq(control, iommu->iommu_regs + IOMMU_CONTROL);
|
||||
upa_writeq(control, iommu->iommu_control);
|
||||
|
||||
/* Clean out any cruft in the IOMMU using
|
||||
* diagnostic accesses.
|
||||
*/
|
||||
for (i = 0; i < 16; i++) {
|
||||
unsigned long dram = iommu->iommu_regs + IOMMU_DRAMDIAG;
|
||||
unsigned long tag = iommu->iommu_regs + IOMMU_TAGDIAG;
|
||||
unsigned long dram, tag;
|
||||
|
||||
dram = iommu->iommu_control + (IOMMU_DRAMDIAG - IOMMU_CONTROL);
|
||||
tag = iommu->iommu_control + (IOMMU_TAGDIAG - IOMMU_CONTROL);
|
||||
|
||||
dram += (unsigned long)i * 8UL;
|
||||
tag += (unsigned long)i * 8UL;
|
||||
upa_writeq(0, dram);
|
||||
upa_writeq(0, tag);
|
||||
}
|
||||
upa_readq(iommu->sbus_control_reg);
|
||||
upa_readq(iommu->write_complete_reg);
|
||||
|
||||
/* Give the TSB to SYSIO. */
|
||||
upa_writeq(__pa(iommu->page_table), iommu->iommu_regs + IOMMU_TSBBASE);
|
||||
upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase);
|
||||
|
||||
/* Setup streaming buffer, DE=1 SB_EN=1 */
|
||||
control = (1UL << 1UL) | (1UL << 0UL);
|
||||
upa_writeq(control, iommu->strbuf_regs + STRBUF_CONTROL);
|
||||
upa_writeq(control, strbuf->strbuf_control);
|
||||
|
||||
/* Clear out the tags using diagnostics. */
|
||||
for (i = 0; i < 16; i++) {
|
||||
unsigned long ptag, ltag;
|
||||
|
||||
ptag = iommu->strbuf_regs + STRBUF_PTAGDIAG;
|
||||
ltag = iommu->strbuf_regs + STRBUF_LTAGDIAG;
|
||||
ptag = strbuf->strbuf_control +
|
||||
(STRBUF_PTAGDIAG - STRBUF_CONTROL);
|
||||
ltag = strbuf->strbuf_control +
|
||||
(STRBUF_LTAGDIAG - STRBUF_CONTROL);
|
||||
ptag += (unsigned long)i * 8UL;
|
||||
ltag += (unsigned long)i * 8UL;
|
||||
|
||||
|
|
@ -1113,9 +1148,9 @@ static void __init sbus_iommu_init(int __node, struct sbus_bus *sbus)
|
|||
}
|
||||
|
||||
/* Enable DVMA arbitration for all devices/slots. */
|
||||
control = upa_readq(iommu->sbus_control_reg);
|
||||
control = upa_readq(iommu->write_complete_reg);
|
||||
control |= 0x3fUL;
|
||||
upa_writeq(control, iommu->sbus_control_reg);
|
||||
upa_writeq(control, iommu->write_complete_reg);
|
||||
|
||||
/* Now some Xfire specific grot... */
|
||||
if (this_is_starfire)
|
||||
|
|
|
|||
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