dt-bindings: pwm: mediatek: Convert pwm-mediatek to DT schema
This converts pwm-mediatek.txt to mediatek,mt2712-pwm.yaml schema; while at it, the clock names were clarified as previously they were documented as "pwmX-Y", but valid names are "pwmN" only. Also, the example was changed to use "mediatek,mt2712-pwm" instead for consistency with the schema filename. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
This commit is contained in:
AngeloGioacchino Del Regno
Thierry Reding
Родитель
3066bc2d58
Коммит
3e98855ca0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pwm/mediatek,mt2712-pwm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek PWM Controller
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maintainers:
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- John Crispin <john@phrozen.org>
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allOf:
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- $ref: pwm.yaml#
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properties:
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compatible:
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oneOf:
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- enum:
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- mediatek,mt2712-pwm
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- mediatek,mt6795-pwm
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- mediatek,mt7622-pwm
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- mediatek,mt7623-pwm
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- mediatek,mt7628-pwm
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- mediatek,mt7629-pwm
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- mediatek,mt8183-pwm
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- mediatek,mt8365-pwm
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- mediatek,mt8516-pwm
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- items:
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- enum:
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- mediatek,mt8195-pwm
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- const: mediatek,mt8183-pwm
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reg:
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maxItems: 1
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"#pwm-cells":
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const: 2
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interrupts:
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maxItems: 1
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clocks:
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minItems: 2
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maxItems: 10
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clock-names:
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description:
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This controller needs two input clocks for its core and one
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clock for each PWM output.
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minItems: 2
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items:
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- const: top
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- const: main
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- const: pwm1
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- const: pwm2
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- const: pwm3
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- const: pwm4
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- const: pwm5
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- const: pwm6
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- const: pwm7
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- const: pwm8
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required:
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- compatible
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- reg
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- "#pwm-cells"
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt2712-clk.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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pwm0: pwm@11006000 {
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compatible = "mediatek,mt2712-pwm";
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reg = <0x11006000 0x1000>;
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#pwm-cells = <2>;
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_PWM_SEL>, <&pericfg CLK_PERI_PWM>,
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<&pericfg CLK_PERI_PWM0>, <&pericfg CLK_PERI_PWM1>,
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<&pericfg CLK_PERI_PWM2>, <&pericfg CLK_PERI_PWM3>,
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<&pericfg CLK_PERI_PWM4>, <&pericfg CLK_PERI_PWM5>,
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<&pericfg CLK_PERI_PWM6>, <&pericfg CLK_PERI_PWM7>;
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clock-names = "top", "main",
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"pwm1", "pwm2",
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"pwm3", "pwm4",
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"pwm5", "pwm6",
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"pwm7", "pwm8";
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};
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@ -1,52 +0,0 @@
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MediaTek PWM controller
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Required properties:
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- compatible: should be "mediatek,<name>-pwm":
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- "mediatek,mt2712-pwm": found on mt2712 SoC.
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- "mediatek,mt6795-pwm": found on mt6795 SoC.
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- "mediatek,mt7622-pwm": found on mt7622 SoC.
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- "mediatek,mt7623-pwm": found on mt7623 SoC.
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- "mediatek,mt7628-pwm": found on mt7628 SoC.
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- "mediatek,mt7629-pwm": found on mt7629 SoC.
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- "mediatek,mt8183-pwm": found on mt8183 SoC.
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- "mediatek,mt8195-pwm", "mediatek,mt8183-pwm": found on mt8195 SoC.
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- "mediatek,mt8365-pwm": found on mt8365 SoC.
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- "mediatek,mt8516-pwm": found on mt8516 SoC.
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- reg: physical base address and length of the controller's registers.
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- #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
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the cell format.
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- clocks: phandle and clock specifier of the PWM reference clock.
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- clock-names: must contain the following, except for MT7628 which
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has no clocks
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- "top": the top clock generator
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- "main": clock used by the PWM core
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- "pwm1-3": the three per PWM clocks for mt8365
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- "pwm1-8": the eight per PWM clocks for mt2712
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- "pwm1-6": the six per PWM clocks for mt7622
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- "pwm1-5": the five per PWM clocks for mt7623
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- "pwm1" : the PWM1 clock for mt7629
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- pinctrl-names: Must contain a "default" entry.
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- pinctrl-0: One property must exist for each entry in pinctrl-names.
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See pinctrl/pinctrl-bindings.txt for details of the property values.
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Optional properties:
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- assigned-clocks: Reference to the PWM clock entries.
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- assigned-clock-parents: The phandle of the parent clock of PWM clock.
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Example:
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pwm0: pwm@11006000 {
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compatible = "mediatek,mt7623-pwm";
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reg = <0 0x11006000 0 0x1000>;
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#pwm-cells = <2>;
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clocks = <&topckgen CLK_TOP_PWM_SEL>,
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<&pericfg CLK_PERI_PWM>,
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<&pericfg CLK_PERI_PWM1>,
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<&pericfg CLK_PERI_PWM2>,
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<&pericfg CLK_PERI_PWM3>,
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<&pericfg CLK_PERI_PWM4>,
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<&pericfg CLK_PERI_PWM5>;
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clock-names = "top", "main", "pwm1", "pwm2",
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"pwm3", "pwm4", "pwm5";
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pinctrl-names = "default";
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pinctrl-0 = <&pwm0_pins>;
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};
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