From f9875d1a3630de80240a40c180f0871bee40298a Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Mon, 8 Mar 2021 12:05:47 +0530 Subject: [PATCH 1/4] dt-bindings: PCI: ti,j721e: Add binding to represent refclk to the connector Add binding to represent refclk to the PCIe connector. Link: https://lore.kernel.org/r/20210308063550.6227-2-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Lorenzo Pieralisi Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index 0880a613ece6..963f90816645 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -46,12 +46,17 @@ properties: maxItems: 1 clocks: - maxItems: 1 - description: clock-specifier to represent input to the PCIe + minItems: 1 + maxItems: 2 + description: |+ + clock-specifier to represent input to the PCIe for 1 item. + 2nd item if present represents reference clock to the connector. clock-names: + minItems: 1 items: - const: fck + - const: pcie_refclk vendor-id: const: 0x104c From 3201f355e9a92114d440f05c0c4410173ef7042c Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Mon, 8 Mar 2021 12:05:48 +0530 Subject: [PATCH 2/4] dt-bindings: PCI: ti,j721e: Add host mode dt-bindings for TI's AM64 SoC Add host mode dt-bindings for TI's AM64 SoC. This is the same IP used in J7200, however AM64 is a non-coherent architecture. Link: https://lore.kernel.org/r/20210308063550.6227-3-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Lorenzo Pieralisi Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index 963f90816645..cc900202df29 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -16,13 +16,15 @@ allOf: properties: compatible: oneOf: + - const: ti,j721e-pcie-host + - description: PCIe controller in AM64 + items: + - const: ti,am64-pcie-host + - const: ti,j721e-pcie-host - description: PCIe controller in J7200 items: - const: ti,j7200-pcie-host - const: ti,j721e-pcie-host - - description: PCIe controller in J721E - items: - - const: ti,j721e-pcie-host reg: maxItems: 4 @@ -67,6 +69,8 @@ properties: - const: 0xb00d - items: - const: 0xb00f + - items: + - const: 0xb010 msi-map: true @@ -83,7 +87,6 @@ required: - vendor-id - device-id - msi-map - - dma-coherent - dma-ranges - ranges - reset-gpios From 6b7d5394c21d0f0a98a9a9ecc11c8e0f264e9e4b Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Mon, 8 Mar 2021 12:05:49 +0530 Subject: [PATCH 3/4] dt-bindings: PCI: ti,j721e: Add endpoint mode dt-bindings for TI's AM64 SoC Add endpoint mode dt-bindings for TI's AM64 SoC. This is the same IP used in J7200, however AM64 is a non-coherent architecture. Link: https://lore.kernel.org/r/20210308063550.6227-4-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Lorenzo Pieralisi Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml index d06f0c4464c6..aed437dac363 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml @@ -16,13 +16,15 @@ allOf: properties: compatible: oneOf: + - const: ti,j721e-pcie-ep + - description: PCIe EP controller in AM64 + items: + - const: ti,am64-pcie-ep + - const: ti,j721e-pcie-ep - description: PCIe EP controller in J7200 items: - const: ti,j7200-pcie-ep - const: ti,j721e-pcie-ep - - description: PCIe EP controller in J721E - items: - - const: ti,j721e-pcie-ep reg: maxItems: 4 @@ -66,7 +68,6 @@ required: - power-domains - clocks - clock-names - - dma-coherent - max-functions - phys - phy-names From 49e0efdce791256fef94c3940aea77a0a6b0622e Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Mon, 8 Mar 2021 12:05:50 +0530 Subject: [PATCH 4/4] PCI: j721e: Add support to provide refclk to PCIe connector Add support to provide refclk to PCIe connector. Link: https://lore.kernel.org/r/20210308063550.6227-5-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Lorenzo Pieralisi --- drivers/pci/controller/cadence/pci-j721e.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index 849f1e416ea5..9c102efc306a 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -6,6 +6,7 @@ * Author: Kishon Vijay Abraham I */ +#include #include #include #include @@ -50,6 +51,7 @@ enum link_status { struct j721e_pcie { struct device *dev; + struct clk *refclk; u32 mode; u32 num_lanes; struct cdns_pcie *cdns_pcie; @@ -312,6 +314,7 @@ static int j721e_pcie_probe(struct platform_device *pdev) struct cdns_pcie_ep *ep; struct gpio_desc *gpiod; void __iomem *base; + struct clk *clk; u32 num_lanes; u32 mode; int ret; @@ -411,6 +414,20 @@ static int j721e_pcie_probe(struct platform_device *pdev) goto err_get_sync; } + clk = devm_clk_get_optional(dev, "pcie_refclk"); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + dev_err(dev, "failed to get pcie_refclk\n"); + goto err_pcie_setup; + } + + ret = clk_prepare_enable(clk); + if (ret) { + dev_err(dev, "failed to enable pcie_refclk\n"); + goto err_get_sync; + } + pcie->refclk = clk; + /* * "Power Sequencing and Reset Signal Timings" table in * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0 @@ -425,8 +442,10 @@ static int j721e_pcie_probe(struct platform_device *pdev) } ret = cdns_pcie_host_setup(rc); - if (ret < 0) + if (ret < 0) { + clk_disable_unprepare(pcie->refclk); goto err_pcie_setup; + } break; case PCI_MODE_EP: @@ -479,6 +498,7 @@ static int j721e_pcie_remove(struct platform_device *pdev) struct cdns_pcie *cdns_pcie = pcie->cdns_pcie; struct device *dev = &pdev->dev; + clk_disable_unprepare(pcie->refclk); cdns_pcie_disable_phy(cdns_pcie); pm_runtime_put(dev); pm_runtime_disable(dev);