fbdev: s1d13xxxfb: add accelerated bitblt functions
Add accelerated bitblt functions to s1d13xxx based video chipsets, more specificly functions copyarea and fillrect. It has only been tested and activated for 13506 chipsets but is expected to work for the majority of s1d13xxx based chips. This patch also cleans up the driver with respect of whitespaces and other formatting issues. We update the current status comments. [akpm@linux-foundation.org: coding-style fixes] Signed-off-by: Kristoffer Ericson <kristoffer.ericson@gmail.com> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Krzysztof Helt <krzysztof.h1@poczta.fm> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Kristoffer Ericson
Linus Torvalds
Родитель
fe3a1aa239
Коммит
3ed167af96
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@ -2,6 +2,7 @@
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*
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* (c) 2004 Simtec Electronics
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* (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
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* (c) 2009 Kristoffer Ericson <kristoffer.ericson@gmail.com>
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*
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* Driver for Epson S1D13xxx series framebuffer chips
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*
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@ -10,18 +11,10 @@
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* linux/drivers/video/epson1355fb.c
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* linux/drivers/video/epson/s1d13xxxfb.c (2.4 driver by Epson)
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*
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* Note, currently only tested on S1D13806 with 16bit CRT.
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* As such, this driver might still contain some hardcoded bits relating to
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* S1D13806.
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* Making it work on other S1D13XXX chips should merely be a matter of adding
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* a few switch()s, some missing glue here and there maybe, and split header
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* files.
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*
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* TODO: - handle dual screen display (CRT and LCD at the same time).
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* - check_var(), mode change, etc.
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* - PM untested.
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* - Accelerated interfaces.
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* - Probably not SMP safe :)
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* - probably not SMP safe :)
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* - support all bitblt operations on all cards
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive for
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@ -31,19 +24,24 @@
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/mm.h>
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#include <linux/mman.h>
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#include <linux/fb.h>
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#include <linux/spinlock_types.h>
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#include <linux/spinlock.h>
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#include <asm/io.h>
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#include <video/s1d13xxxfb.h>
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#define PFX "s1d13xxxfb: "
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#define PFX "s1d13xxxfb: "
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#define BLIT "s1d13xxxfb_bitblt: "
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/*
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* set this to enable debugging on general functions
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*/
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#if 0
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#define dbg(fmt, args...) do { printk(KERN_INFO fmt, ## args); } while(0)
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#else
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@ -51,7 +49,21 @@
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#endif
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/*
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* List of card production ids
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* set this to enable debugging on 2D acceleration
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*/
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#if 0
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#define dbg_blit(fmt, args...) do { printk(KERN_INFO BLIT fmt, ## args); } while (0)
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#else
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#define dbg_blit(fmt, args...) do { } while (0)
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#endif
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/*
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* we make sure only one bitblt operation is running
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*/
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static DEFINE_SPINLOCK(s1d13xxxfb_bitblt_lock);
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/*
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* list of card production ids
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*/
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static const int s1d13xxxfb_prod_ids[] = {
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S1D13505_PROD_ID,
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@ -69,7 +81,7 @@ static const char *s1d13xxxfb_prod_names[] = {
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};
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/*
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* Here we define the default struct fb_fix_screeninfo
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* here we define the default struct fb_fix_screeninfo
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*/
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static struct fb_fix_screeninfo __devinitdata s1d13xxxfb_fix = {
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.id = S1D_FBID,
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@ -145,8 +157,10 @@ crt_enable(struct s1d13xxxfb_par *par, int enable)
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s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, mode);
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}
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/* framebuffer control routines */
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/*************************************************************
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framebuffer control functions
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*************************************************************/
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static inline void
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s1d13xxxfb_setup_pseudocolour(struct fb_info *info)
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{
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@ -242,13 +256,13 @@ s1d13xxxfb_set_par(struct fb_info *info)
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}
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/**
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* s1d13xxxfb_setcolreg - sets a color register.
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* @regno: Which register in the CLUT we are programming
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* @red: The red value which can be up to 16 bits wide
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* s1d13xxxfb_setcolreg - sets a color register.
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* @regno: Which register in the CLUT we are programming
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* @red: The red value which can be up to 16 bits wide
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* @green: The green value which can be up to 16 bits wide
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* @blue: The blue value which can be up to 16 bits wide.
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* @transp: If supported the alpha value which can be up to 16 bits wide.
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* @info: frame buffer info structure
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* @info: frame buffer info structure
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*
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* Returns negative errno on error, or zero on success.
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*/
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@ -351,15 +365,15 @@ s1d13xxxfb_blank(int blank_mode, struct fb_info *info)
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}
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/**
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* s1d13xxxfb_pan_display - Pans the display.
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* @var: frame buffer variable screen structure
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* @info: frame buffer structure that represents a single frame buffer
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* s1d13xxxfb_pan_display - Pans the display.
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* @var: frame buffer variable screen structure
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* @info: frame buffer structure that represents a single frame buffer
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*
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* Pan (or wrap, depending on the `vmode' field) the display using the
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* `yoffset' field of the `var' structure (`xoffset' not yet supported).
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* If the values don't fit, return -EINVAL.
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* `yoffset' field of the `var' structure (`xoffset' not yet supported).
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* If the values don't fit, return -EINVAL.
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*
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* Returns negative errno on error, or zero on success.
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* Returns negative errno on error, or zero on success.
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*/
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static int
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s1d13xxxfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
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@ -390,8 +404,259 @@ s1d13xxxfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
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return 0;
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}
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/* framebuffer information structures */
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/************************************************************
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functions to handle bitblt acceleration
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************************************************************/
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/**
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* bltbit_wait_bitset - waits for change in register value
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* @info : framebuffer structure
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* @bit : value expected in register
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* @timeout : ...
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*
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* waits until value changes INTO bit
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*/
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static u8
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bltbit_wait_bitset(struct fb_info *info, u8 bit, int timeout)
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{
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while (!(s1d13xxxfb_readreg(info->par, S1DREG_BBLT_CTL0) & bit)) {
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udelay(10);
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if (!--timeout) {
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dbg_blit("wait_bitset timeout\n");
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break;
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}
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}
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return timeout;
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}
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/**
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* bltbit_wait_bitclear - waits for change in register value
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* @info : frambuffer structure
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* @bit : value currently in register
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* @timeout : ...
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*
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* waits until value changes FROM bit
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*
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*/
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static u8
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bltbit_wait_bitclear(struct fb_info *info, u8 bit, int timeout)
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{
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while (s1d13xxxfb_readreg(info->par, S1DREG_BBLT_CTL0) & bit) {
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udelay(10);
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if (!--timeout) {
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dbg_blit("wait_bitclear timeout\n");
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break;
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}
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}
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return timeout;
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}
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/**
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* bltbit_fifo_status - checks the current status of the fifo
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* @info : framebuffer structure
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*
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* returns number of free words in buffer
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*/
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static u8
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bltbit_fifo_status(struct fb_info *info)
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{
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u8 status;
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status = s1d13xxxfb_readreg(info->par, S1DREG_BBLT_CTL0);
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/* its empty so room for 16 words */
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if (status & BBLT_FIFO_EMPTY)
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return 16;
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/* its full so we dont want to add */
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if (status & BBLT_FIFO_FULL)
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return 0;
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/* its atleast half full but we can add one atleast */
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if (status & BBLT_FIFO_NOT_FULL)
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return 1;
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return 0;
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}
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/*
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* s1d13xxxfb_bitblt_copyarea - accelerated copyarea function
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* @info : framebuffer structure
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* @area : fb_copyarea structure
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*
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* supports (atleast) S1D13506
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*
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*/
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static void
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s1d13xxxfb_bitblt_copyarea(struct fb_info *info, const struct fb_copyarea *area)
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{
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u32 dst, src;
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u32 stride;
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u16 reverse = 0;
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u16 sx = area->sx, sy = area->sy;
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u16 dx = area->dx, dy = area->dy;
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u16 width = area->width, height = area->height;
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u16 bpp;
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spin_lock(&s1d13xxxfb_bitblt_lock);
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/* bytes per xres line */
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bpp = (info->var.bits_per_pixel >> 3);
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stride = bpp * info->var.xres;
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/* reverse, calculate the last pixel in rectangle */
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if ((dy > sy) || ((dy == sy) && (dx >= sx))) {
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dst = (((dy + height - 1) * stride) + (bpp * (dx + width - 1)));
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src = (((sy + height - 1) * stride) + (bpp * (sx + width - 1)));
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reverse = 1;
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/* not reverse, calculate the first pixel in rectangle */
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} else { /* (y * xres) + (bpp * x) */
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dst = (dy * stride) + (bpp * dx);
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src = (sy * stride) + (bpp * sx);
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}
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/* set source adress */
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START0, (src & 0xff));
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START1, (src >> 8) & 0x00ff);
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START2, (src >> 16) & 0x00ff);
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/* set destination adress */
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START0, (dst & 0xff));
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START1, (dst >> 8) & 0x00ff);
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START2, (dst >> 16) & 0x00ff);
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/* program height and width */
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH0, (width & 0xff) - 1);
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH1, (width >> 8));
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT0, (height & 0xff) - 1);
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT1, (height >> 8));
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/* negative direction ROP */
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if (reverse == 1) {
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dbg_blit("(copyarea) negative rop\n");
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_OP, 0x03);
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} else /* positive direction ROP */ {
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_OP, 0x02);
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dbg_blit("(copyarea) positive rop\n");
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}
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/* set for rectangel mode and not linear */
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x0);
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/* setup the bpp 1 = 16bpp, 0 = 8bpp*/
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL1, (bpp >> 1));
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/* set words per xres */
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF0, (stride >> 1) & 0xff);
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF1, (stride >> 9));
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dbg_blit("(copyarea) dx=%d, dy=%d\n", dx, dy);
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dbg_blit("(copyarea) sx=%d, sy=%d\n", sx, sy);
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dbg_blit("(copyarea) width=%d, height=%d\n", width - 1, height - 1);
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dbg_blit("(copyarea) stride=%d\n", stride);
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dbg_blit("(copyarea) bpp=%d=0x0%d, mem_offset1=%d, mem_offset2=%d\n", bpp, (bpp >> 1),
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(stride >> 1) & 0xff, stride >> 9);
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CC_EXP, 0x0c);
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/* initialize the engine */
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x80);
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/* wait to complete */
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bltbit_wait_bitclear(info, 0x80, 8000);
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spin_unlock(&s1d13xxxfb_bitblt_lock);
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}
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/**
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*
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* s1d13xxxfb_bitblt_solidfill - accelerated solidfill function
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* @info : framebuffer structure
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* @rect : fb_fillrect structure
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*
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* supports (atleast 13506)
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*
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**/
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static void
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s1d13xxxfb_bitblt_solidfill(struct fb_info *info, const struct fb_fillrect *rect)
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{
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u32 screen_stride, dest;
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u32 fg;
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u16 bpp = (info->var.bits_per_pixel >> 3);
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/* grab spinlock */
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spin_lock(&s1d13xxxfb_bitblt_lock);
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/* bytes per x width */
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screen_stride = (bpp * info->var.xres);
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/* bytes to starting point */
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dest = ((rect->dy * screen_stride) + (bpp * rect->dx));
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dbg_blit("(solidfill) dx=%d, dy=%d, stride=%d, dest=%d\n"
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"(solidfill) : rect_width=%d, rect_height=%d\n",
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rect->dx, rect->dy, screen_stride, dest,
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rect->width - 1, rect->height - 1);
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dbg_blit("(solidfill) : xres=%d, yres=%d, bpp=%d\n",
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info->var.xres, info->var.yres,
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info->var.bits_per_pixel);
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dbg_blit("(solidfill) : rop=%d\n", rect->rop);
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/* We split the destination into the three registers */
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START0, (dest & 0x00ff));
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START1, ((dest >> 8) & 0x00ff));
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START2, ((dest >> 16) & 0x00ff));
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/* give information regarding rectangel width */
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH0, ((rect->width) & 0x00ff) - 1);
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH1, (rect->width >> 8));
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/* give information regarding rectangel height */
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT0, ((rect->height) & 0x00ff) - 1);
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT1, (rect->height >> 8));
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if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
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info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
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fg = ((u32 *)info->pseudo_palette)[rect->color];
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dbg_blit("(solidfill) truecolor/directcolor\n");
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dbg_blit("(solidfill) pseudo_palette[%d] = %d\n", rect->color, fg);
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} else {
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fg = rect->color;
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dbg_blit("(solidfill) color = %d\n", rect->color);
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}
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/* set foreground color */
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_FGC0, (fg & 0xff));
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_FGC1, (fg >> 8) & 0xff);
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/* set rectangual region of memory (rectangle and not linear) */
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x0);
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/* set operation mode SOLID_FILL */
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_OP, BBLT_SOLID_FILL);
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/* set bits per pixel (1 = 16bpp, 0 = 8bpp) */
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL1, (info->var.bits_per_pixel >> 4));
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/* set the memory offset for the bblt in word sizes */
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF0, (screen_stride >> 1) & 0x00ff);
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF1, (screen_stride >> 9));
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/* and away we go.... */
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x80);
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/* wait until its done */
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bltbit_wait_bitclear(info, 0x80, 8000);
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/* let others play */
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spin_unlock(&s1d13xxxfb_bitblt_lock);
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}
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/* framebuffer information structures */
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static struct fb_ops s1d13xxxfb_fbops = {
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.owner = THIS_MODULE,
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.fb_set_par = s1d13xxxfb_set_par,
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@ -400,7 +665,7 @@ static struct fb_ops s1d13xxxfb_fbops = {
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.fb_pan_display = s1d13xxxfb_pan_display,
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/* to be replaced by any acceleration we can */
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/* gets replaced at chip detection time */
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.fb_fillrect = cfb_fillrect,
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.fb_copyarea = cfb_copyarea,
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.fb_imageblit = cfb_imageblit,
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@ -412,9 +677,9 @@ static int s1d13xxxfb_width_tab[2][4] __devinitdata = {
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};
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||||
/**
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||||
* s1d13xxxfb_fetch_hw_state - Configure the framebuffer according to
|
||||
* s1d13xxxfb_fetch_hw_state - Configure the framebuffer according to
|
||||
* hardware setup.
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||||
* @info: frame buffer structure
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* @info: frame buffer structure
|
||||
*
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||||
* We setup the framebuffer structures according to the current
|
||||
* hardware setup. On some machines, the BIOS will have filled
|
||||
|
|
@ -569,7 +834,6 @@ s1d13xxxfb_probe(struct platform_device *pdev)
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|||
if (pdata && pdata->platform_init_video)
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||||
pdata->platform_init_video();
|
||||
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||||
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||||
if (pdev->num_resources != 2) {
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||||
dev_err(&pdev->dev, "invalid num_resources: %i\n",
|
||||
pdev->num_resources);
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|
@ -655,16 +919,27 @@ s1d13xxxfb_probe(struct platform_device *pdev)
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|||
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||||
info->fix = s1d13xxxfb_fix;
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||||
info->fix.mmio_start = pdev->resource[1].start;
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||||
info->fix.mmio_len = pdev->resource[1].end - pdev->resource[1].start +1;
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||||
info->fix.mmio_len = pdev->resource[1].end - pdev->resource[1].start + 1;
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||||
info->fix.smem_start = pdev->resource[0].start;
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info->fix.smem_len = pdev->resource[0].end - pdev->resource[0].start +1;
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||||
info->fix.smem_len = pdev->resource[0].end - pdev->resource[0].start + 1;
|
||||
|
||||
printk(KERN_INFO PFX "regs mapped at 0x%p, fb %d KiB mapped at 0x%p\n",
|
||||
default_par->regs, info->fix.smem_len / 1024, info->screen_base);
|
||||
|
||||
info->par = default_par;
|
||||
info->fbops = &s1d13xxxfb_fbops;
|
||||
info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
|
||||
info->fbops = &s1d13xxxfb_fbops;
|
||||
|
||||
switch(prod_id) {
|
||||
case S1D13506_PROD_ID: /* activate acceleration */
|
||||
s1d13xxxfb_fbops.fb_fillrect = s1d13xxxfb_bitblt_solidfill;
|
||||
s1d13xxxfb_fbops.fb_copyarea = s1d13xxxfb_bitblt_copyarea;
|
||||
info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN |
|
||||
FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_COPYAREA;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* perform "manual" chip initialization, if needed */
|
||||
if (pdata && pdata->initregs)
|
||||
|
|
|
|||
|
|
@ -136,6 +136,15 @@
|
|||
#define S1DREG_DELAYOFF 0xFFFE
|
||||
#define S1DREG_DELAYON 0xFFFF
|
||||
|
||||
#define BBLT_FIFO_EMPTY 0x00
|
||||
#define BBLT_FIFO_NOT_EMPTY 0x40
|
||||
#define BBLT_FIFO_NOT_FULL 0x30
|
||||
#define BBLT_FIFO_HALF_FULL 0x20
|
||||
#define BBLT_FIFO_FULL 0x10
|
||||
|
||||
#define BBLT_SOLID_FILL 0x0c
|
||||
|
||||
|
||||
/* Note: all above defines should go in separate header files
|
||||
when implementing other S1D13xxx chip support. */
|
||||
|
||||
|
|
|
|||
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