ARM: tegra: export apb dma readl/writel
Export APB DMA readl and writel. These are needed because we can't access the fuses directly on Tegra20 without potentially causing a system hang. Also have the APB DMA readl and writel return an error in case of a read failure instead of just returning zero or ignore write failures. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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3f394f8064
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@ -32,8 +32,8 @@ static u32 *tegra_apb_bb;
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static dma_addr_t tegra_apb_bb_phys;
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static DECLARE_COMPLETION(tegra_apb_wait);
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static u32 tegra_apb_readl_direct(unsigned long offset);
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static void tegra_apb_writel_direct(u32 value, unsigned long offset);
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static int tegra_apb_readl_direct(unsigned long offset, u32 *value);
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static int tegra_apb_writel_direct(u32 value, unsigned long offset);
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static struct dma_chan *tegra_apb_dma_chan;
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static struct dma_slave_config dma_sconfig;
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@ -128,58 +128,64 @@ static int do_dma_transfer(unsigned long apb_add,
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return 0;
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}
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static u32 tegra_apb_readl_using_dma(unsigned long offset)
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int tegra_apb_readl_using_dma(unsigned long offset, u32 *value)
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{
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int ret;
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if (!tegra_apb_dma_chan && !tegra_apb_dma_init())
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return tegra_apb_readl_direct(offset);
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return tegra_apb_readl_direct(offset, value);
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mutex_lock(&tegra_apb_dma_lock);
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ret = do_dma_transfer(offset, DMA_DEV_TO_MEM);
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if (ret < 0) {
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if (ret < 0)
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pr_err("error in reading offset 0x%08lx using dma\n", offset);
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*(u32 *)tegra_apb_bb = 0;
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}
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else
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*value = *tegra_apb_bb;
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mutex_unlock(&tegra_apb_dma_lock);
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return *((u32 *)tegra_apb_bb);
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return ret;
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}
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static void tegra_apb_writel_using_dma(u32 value, unsigned long offset)
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int tegra_apb_writel_using_dma(u32 value, unsigned long offset)
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{
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int ret;
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if (!tegra_apb_dma_chan && !tegra_apb_dma_init()) {
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tegra_apb_writel_direct(value, offset);
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return;
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}
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if (!tegra_apb_dma_chan && !tegra_apb_dma_init())
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return tegra_apb_writel_direct(value, offset);
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mutex_lock(&tegra_apb_dma_lock);
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*((u32 *)tegra_apb_bb) = value;
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ret = do_dma_transfer(offset, DMA_MEM_TO_DEV);
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mutex_unlock(&tegra_apb_dma_lock);
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if (ret < 0)
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pr_err("error in writing offset 0x%08lx using dma\n", offset);
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mutex_unlock(&tegra_apb_dma_lock);
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return ret;
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}
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#else
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#define tegra_apb_readl_using_dma tegra_apb_readl_direct
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#define tegra_apb_writel_using_dma tegra_apb_writel_direct
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#endif
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typedef u32 (*apbio_read_fptr)(unsigned long offset);
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typedef void (*apbio_write_fptr)(u32 value, unsigned long offset);
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typedef int (*apbio_read_fptr)(unsigned long offset, u32 *value);
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typedef int (*apbio_write_fptr)(u32 value, unsigned long offset);
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static apbio_read_fptr apbio_read;
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static apbio_write_fptr apbio_write;
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static u32 tegra_apb_readl_direct(unsigned long offset)
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static int tegra_apb_readl_direct(unsigned long offset, u32 *value)
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{
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return readl(IO_ADDRESS(offset));
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*value = readl(IO_ADDRESS(offset));
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return 0;
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}
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static void tegra_apb_writel_direct(u32 value, unsigned long offset)
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static int tegra_apb_writel_direct(u32 value, unsigned long offset)
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{
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writel(value, IO_ADDRESS(offset));
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return 0;
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}
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void tegra_apb_io_init(void)
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@ -197,7 +203,12 @@ void tegra_apb_io_init(void)
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u32 tegra_apb_readl(unsigned long offset)
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{
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return apbio_read(offset);
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u32 val;
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if (apbio_read(offset, &val) < 0)
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return 0;
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else
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return val;
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}
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void tegra_apb_writel(u32 value, unsigned long offset)
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@ -27,6 +27,20 @@
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u32 tegra_read_chipid(void);
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u8 tegra_get_chip_id(void);
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#if defined(CONFIG_TEGRA20_APB_DMA)
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int tegra_apb_readl_using_dma(unsigned long offset, u32 *value);
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int tegra_apb_writel_using_dma(u32 value, unsigned long offset);
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#else
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static inline int tegra_apb_readl_using_dma(unsigned long offset, u32 *value)
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{
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return -EINVAL;
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}
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static inline int tegra_apb_writel_using_dma(u32 value, unsigned long offset)
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{
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return -EINVAL;
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}
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#endif /* CONFIG_TEGRA20_APB_DMA */
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#endif /* __ASSEMBLY__ */
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#endif /* __SOC_TEGRA_FUSE_H__ */
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