mlx5-fixes-2017-05-23
Some TC offloads fixes from Or Gerlitz. From Erez, mlx5 IPoIB RX fix to improve GRO. From Mohamad, Command interface fix to improve mitigation against FW commands timeouts. From Tariq, Driver load Tolerance against affinity settings failures. Thanks, Saeed. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJZJD6WAAoJEEg/ir3gV/o+EJkH+gN9G9jXCkYEkuy0eADCRRMY Zs1wkJory1whkMyLScA8xO13IpSZ8AmZCp53hPi+Ak17JQrQ26D9MlzkR3WelWL4 4ABZBRDapKdFNsY2SSnGWb7U1INqCmamHF9hOIcezk6rPxKdx9RQ2pkShM5fObKL vSi+ptrUd5KuMWjikKr/P0v8BfFGYhDTcS5ToNFcITDrbs9srXRjMzgM0MFtvWit 9chXJVpudJdb9vlHjYrlY1nuJopfXyJxtvfBZqjQmviA/+LT0qJ81qkBEjaEyjxk 10Nc6eYfuZKIiDav3AC69xuSTPk73dxrrhOEBpPdqaq6sEOFl8NjpidETYVBnwQ= =GMLr -----END PGP SIGNATURE----- Merge tag 'mlx5-fixes-2017-05-23' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux Saeed Mahameed says: ==================== mlx5-fixes-2017-05-23 Some TC offloads fixes from Or Gerlitz. From Erez, mlx5 IPoIB RX fix to improve GRO. From Mohamad, Command interface fix to improve mitigation against FW commands timeouts. From Tariq, Driver load Tolerance against affinity settings failures. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
Коммит
3f6b123bcc
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@ -774,7 +774,7 @@ static void cb_timeout_handler(struct work_struct *work)
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mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
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mlx5_command_str(msg_to_opcode(ent->in)),
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msg_to_opcode(ent->in));
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mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
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mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
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}
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static void cmd_work_handler(struct work_struct *work)
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@ -804,6 +804,7 @@ static void cmd_work_handler(struct work_struct *work)
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}
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cmd->ent_arr[ent->idx] = ent;
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set_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state);
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lay = get_inst(cmd, ent->idx);
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ent->lay = lay;
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memset(lay, 0, sizeof(*lay));
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@ -825,6 +826,20 @@ static void cmd_work_handler(struct work_struct *work)
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if (ent->callback)
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schedule_delayed_work(&ent->cb_timeout_work, cb_timeout);
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/* Skip sending command to fw if internal error */
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if (pci_channel_offline(dev->pdev) ||
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dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
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u8 status = 0;
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u32 drv_synd;
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ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status);
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MLX5_SET(mbox_out, ent->out, status, status);
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MLX5_SET(mbox_out, ent->out, syndrome, drv_synd);
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mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
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return;
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}
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/* ring doorbell after the descriptor is valid */
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mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
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wmb();
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@ -835,7 +850,7 @@ static void cmd_work_handler(struct work_struct *work)
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poll_timeout(ent);
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/* make sure we read the descriptor after ownership is SW */
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rmb();
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mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
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mlx5_cmd_comp_handler(dev, 1UL << ent->idx, (ent->ret == -ETIMEDOUT));
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}
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}
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@ -879,7 +894,7 @@ static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
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wait_for_completion(&ent->done);
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} else if (!wait_for_completion_timeout(&ent->done, timeout)) {
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ent->ret = -ETIMEDOUT;
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mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
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mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
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}
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err = ent->ret;
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@ -1375,7 +1390,7 @@ static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
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}
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}
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void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec)
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void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
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{
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struct mlx5_cmd *cmd = &dev->cmd;
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struct mlx5_cmd_work_ent *ent;
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@ -1395,6 +1410,19 @@ void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec)
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struct semaphore *sem;
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ent = cmd->ent_arr[i];
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/* if we already completed the command, ignore it */
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if (!test_and_clear_bit(MLX5_CMD_ENT_STATE_PENDING_COMP,
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&ent->state)) {
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/* only real completion can free the cmd slot */
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if (!forced) {
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mlx5_core_err(dev, "Command completion arrived after timeout (entry idx = %d).\n",
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ent->idx);
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free_ent(cmd, ent->idx);
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}
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continue;
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}
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if (ent->callback)
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cancel_delayed_work(&ent->cb_timeout_work);
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if (ent->page_queue)
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@ -1417,7 +1445,10 @@ void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec)
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mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
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ent->ret, deliv_status_to_str(ent->status), ent->status);
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}
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free_ent(cmd, ent->idx);
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/* only real completion will free the entry slot */
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if (!forced)
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free_ent(cmd, ent->idx);
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if (ent->callback) {
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ds = ent->ts2 - ent->ts1;
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@ -1041,6 +1041,8 @@ void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq)
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#define MLX5_IB_GRH_BYTES 40
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#define MLX5_IPOIB_ENCAP_LEN 4
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#define MLX5_GID_SIZE 16
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#define MLX5_IPOIB_PSEUDO_LEN 20
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#define MLX5_IPOIB_HARD_LEN (MLX5_IPOIB_PSEUDO_LEN + MLX5_IPOIB_ENCAP_LEN)
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static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
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struct mlx5_cqe64 *cqe,
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@ -1048,6 +1050,7 @@ static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
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struct sk_buff *skb)
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{
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struct net_device *netdev = rq->netdev;
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char *pseudo_header;
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u8 *dgid;
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u8 g;
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@ -1076,8 +1079,11 @@ static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
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if (likely(netdev->features & NETIF_F_RXHASH))
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mlx5e_skb_set_hash(cqe, skb);
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/* 20 bytes of ipoib header and 4 for encap existing */
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pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
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memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
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skb_reset_mac_header(skb);
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skb_pull(skb, MLX5_IPOIB_ENCAP_LEN);
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skb_pull(skb, MLX5_IPOIB_HARD_LEN);
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skb->dev = netdev;
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@ -43,6 +43,7 @@
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#include <net/tc_act/tc_vlan.h>
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#include <net/tc_act/tc_tunnel_key.h>
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#include <net/tc_act/tc_pedit.h>
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#include <net/tc_act/tc_csum.h>
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#include <net/vxlan.h>
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#include <net/arp.h>
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#include "en.h"
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@ -384,7 +385,7 @@ static void mlx5e_detach_encap(struct mlx5e_priv *priv,
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if (e->flags & MLX5_ENCAP_ENTRY_VALID)
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mlx5_encap_dealloc(priv->mdev, e->encap_id);
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hlist_del_rcu(&e->encap_hlist);
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hash_del_rcu(&e->encap_hlist);
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kfree(e->encap_header);
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kfree(e);
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}
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@ -925,11 +926,11 @@ static int offload_pedit_fields(struct pedit_headers *masks,
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struct mlx5e_tc_flow_parse_attr *parse_attr)
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{
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struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
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int i, action_size, nactions, max_actions, first, last;
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int i, action_size, nactions, max_actions, first, last, first_z;
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void *s_masks_p, *a_masks_p, *vals_p;
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u32 s_mask, a_mask, val;
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struct mlx5_fields *f;
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u8 cmd, field_bsize;
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u32 s_mask, a_mask;
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unsigned long mask;
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void *action;
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@ -946,7 +947,8 @@ static int offload_pedit_fields(struct pedit_headers *masks,
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for (i = 0; i < ARRAY_SIZE(fields); i++) {
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f = &fields[i];
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/* avoid seeing bits set from previous iterations */
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s_mask = a_mask = mask = val = 0;
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s_mask = 0;
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a_mask = 0;
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s_masks_p = (void *)set_masks + f->offset;
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a_masks_p = (void *)add_masks + f->offset;
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@ -981,12 +983,12 @@ static int offload_pedit_fields(struct pedit_headers *masks,
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memset(a_masks_p, 0, f->size);
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}
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memcpy(&val, vals_p, f->size);
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field_bsize = f->size * BITS_PER_BYTE;
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first_z = find_first_zero_bit(&mask, field_bsize);
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first = find_first_bit(&mask, field_bsize);
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last = find_last_bit(&mask, field_bsize);
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if (first > 0 || last != (field_bsize - 1)) {
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if (first > 0 || last != (field_bsize - 1) || first_z < last) {
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printk(KERN_WARNING "mlx5: partial rewrite (mask %lx) is currently not offloaded\n",
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mask);
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return -EOPNOTSUPP;
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@ -1002,11 +1004,11 @@ static int offload_pedit_fields(struct pedit_headers *masks,
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}
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if (field_bsize == 32)
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MLX5_SET(set_action_in, action, data, ntohl(val));
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MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p));
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else if (field_bsize == 16)
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MLX5_SET(set_action_in, action, data, ntohs(val));
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MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p));
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else if (field_bsize == 8)
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MLX5_SET(set_action_in, action, data, val);
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MLX5_SET(set_action_in, action, data, *(u8 *)vals_p);
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action += action_size;
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nactions++;
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@ -1109,6 +1111,28 @@ out_err:
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return err;
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}
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static bool csum_offload_supported(struct mlx5e_priv *priv, u32 action, u32 update_flags)
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{
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u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
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TCA_CSUM_UPDATE_FLAG_UDP;
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/* The HW recalcs checksums only if re-writing headers */
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if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
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netdev_warn(priv->netdev,
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"TC csum action is only offloaded with pedit\n");
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return false;
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}
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if (update_flags & ~prot_flags) {
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netdev_warn(priv->netdev,
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"can't offload TC csum action for some header/s - flags %#x\n",
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update_flags);
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return false;
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}
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return true;
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}
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static int parse_tc_nic_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
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struct mlx5e_tc_flow_parse_attr *parse_attr,
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struct mlx5e_tc_flow *flow)
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@ -1149,6 +1173,14 @@ static int parse_tc_nic_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
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continue;
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}
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if (is_tcf_csum(a)) {
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if (csum_offload_supported(priv, attr->action,
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tcf_csum_update_flags(a)))
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continue;
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return -EOPNOTSUPP;
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}
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if (is_tcf_skbedit_mark(a)) {
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u32 mark = tcf_skbedit_mark(a);
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@ -1651,6 +1683,14 @@ static int parse_tc_fdb_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
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continue;
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}
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if (is_tcf_csum(a)) {
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if (csum_offload_supported(priv, attr->action,
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tcf_csum_update_flags(a)))
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continue;
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return -EOPNOTSUPP;
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}
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if (is_tcf_mirred_egress_redirect(a)) {
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int ifindex = tcf_mirred_ifindex(a);
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struct net_device *out_dev, *encap_dev = NULL;
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@ -422,7 +422,7 @@ static irqreturn_t mlx5_eq_int(int irq, void *eq_ptr)
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break;
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case MLX5_EVENT_TYPE_CMD:
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mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector));
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mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector), false);
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break;
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case MLX5_EVENT_TYPE_PORT_CHANGE:
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|
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@ -90,7 +90,7 @@ static void trigger_cmd_completions(struct mlx5_core_dev *dev)
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spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
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mlx5_core_dbg(dev, "vector 0x%llx\n", vector);
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mlx5_cmd_comp_handler(dev, vector);
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mlx5_cmd_comp_handler(dev, vector, true);
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return;
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no_trig:
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|
|
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@ -612,7 +612,6 @@ static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
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struct mlx5_priv *priv = &mdev->priv;
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struct msix_entry *msix = priv->msix_arr;
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int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
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int err;
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if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
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mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
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@ -622,18 +621,12 @@ static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
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cpumask_set_cpu(cpumask_local_spread(i, priv->numa_node),
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priv->irq_info[i].mask);
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err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
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if (err) {
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mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
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irq);
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goto err_clear_mask;
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}
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#ifdef CONFIG_SMP
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if (irq_set_affinity_hint(irq, priv->irq_info[i].mask))
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mlx5_core_warn(mdev, "irq_set_affinity_hint failed, irq 0x%.4x", irq);
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#endif
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return 0;
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err_clear_mask:
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free_cpumask_var(priv->irq_info[i].mask);
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return err;
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}
|
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static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
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|
|
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|
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@ -787,7 +787,12 @@ enum {
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typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
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enum {
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MLX5_CMD_ENT_STATE_PENDING_COMP,
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};
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|
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struct mlx5_cmd_work_ent {
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unsigned long state;
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struct mlx5_cmd_msg *in;
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struct mlx5_cmd_msg *out;
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void *uout;
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|
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@ -976,7 +981,7 @@ void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
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void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
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void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
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struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
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void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec);
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void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced);
|
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void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
|
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int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
|
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int nent, u64 mask, const char *name,
|
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|
|
|
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|
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@ -3,6 +3,7 @@
|
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|
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#include <linux/types.h>
|
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#include <net/act_api.h>
|
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#include <linux/tc_act/tc_csum.h>
|
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|
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struct tcf_csum {
|
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struct tc_action common;
|
||||
|
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@ -11,4 +12,18 @@ struct tcf_csum {
|
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};
|
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#define to_tcf_csum(a) ((struct tcf_csum *)a)
|
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|
||||
static inline bool is_tcf_csum(const struct tc_action *a)
|
||||
{
|
||||
#ifdef CONFIG_NET_CLS_ACT
|
||||
if (a->ops && a->ops->type == TCA_ACT_CSUM)
|
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return true;
|
||||
#endif
|
||||
return false;
|
||||
}
|
||||
|
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static inline u32 tcf_csum_update_flags(const struct tc_action *a)
|
||||
{
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return to_tcf_csum(a)->update_flags;
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}
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#endif /* __NET_TC_CSUM_H */
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