ARM: decompressor: switch to by-VA cache maintenance for v7 cores
Update the v7 cache_clean_flush routine to take into account the memory range passed in r0/r1, and perform cache maintenance by virtual address on this range instead of set/way maintenance, which is inappropriate for the purpose of maintaining the cached state of memory contents. Since this removes any use of the stack in the implementation of cache_clean_flush(), we can also drop some code that manages the value of the stack pointer before calling it. Tested-by: Tony Lindgren <tony@atomide.com> Tested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
This commit is contained in:
Ard Biesheuvel
Родитель
e114412f61
Коммит
401b368caa
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@ -530,11 +530,6 @@ dtb_check_done:
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mov r0, r9 @ start of relocated zImage
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add r1, sp, r6 @ end of relocated zImage
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#ifndef CONFIG_ZBOOT_ROM
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/* cache_clean_flush may use the stack, so relocate it */
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add sp, sp, r6
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#endif
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bl cache_clean_flush
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badr r0, restart
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@ -683,6 +678,24 @@ params: ldr r0, =0x10000100 @ params_phys for RPC
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.align
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#endif
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/*
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* dcache_line_size - get the minimum D-cache line size from the CTR register
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* on ARMv7.
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*/
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.macro dcache_line_size, reg, tmp
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#ifdef CONFIG_CPU_V7M
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movw \tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR
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movt \tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR
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ldr \tmp, [\tmp]
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#else
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mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
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#endif
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lsr \tmp, \tmp, #16
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and \tmp, \tmp, #0xf @ cache line size encoding
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mov \reg, #4 @ bytes per word
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mov \reg, \reg, lsl \tmp @ actual cache line size
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.endm
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/*
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* Turn on the cache. We need to setup some page tables so that we
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* can have both the I and D caches on.
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@ -1175,8 +1188,6 @@ __armv7_mmu_cache_off:
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bic r0, r0, #0x000c
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#endif
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mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
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mov r12, lr
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bl __armv7_mmu_cache_flush
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mov r0, #0
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#ifdef CONFIG_MMU
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mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
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@ -1184,7 +1195,7 @@ __armv7_mmu_cache_off:
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mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
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mcr p15, 0, r0, c7, c10, 4 @ DSB
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mcr p15, 0, r0, c7, c5, 4 @ ISB
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mov pc, r12
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mov pc, lr
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/*
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* Clean and flush the cache to maintain consistency.
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@ -1200,6 +1211,7 @@ __armv7_mmu_cache_off:
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.align 5
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cache_clean_flush:
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mov r3, #16
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mov r11, r1
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b call_cache_fn
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__armv4_mpu_cache_flush:
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@ -1250,51 +1262,16 @@ __armv7_mmu_cache_flush:
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mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
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b iflush
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hierarchical:
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mcr p15, 0, r10, c7, c10, 5 @ DMB
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stmfd sp!, {r0-r7, r9-r11}
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mrc p15, 1, r0, c0, c0, 1 @ read clidr
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ands r3, r0, #0x7000000 @ extract loc from clidr
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mov r3, r3, lsr #23 @ left align loc bit field
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beq finished @ if loc is 0, then no need to clean
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mov r10, #0 @ start clean at cache level 0
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loop1:
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add r2, r10, r10, lsr #1 @ work out 3x current cache level
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mov r1, r0, lsr r2 @ extract cache type bits from clidr
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and r1, r1, #7 @ mask of the bits for current cache only
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cmp r1, #2 @ see what cache we have at this level
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blt skip @ skip if no cache, or just i-cache
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
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mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
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and r2, r1, #7 @ extract the length of the cache lines
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add r2, r2, #4 @ add 4 (line length offset)
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ldr r4, =0x3ff
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ands r4, r4, r1, lsr #3 @ find maximum number on the way size
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clz r5, r4 @ find bit position of way size increment
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ldr r7, =0x7fff
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ands r7, r7, r1, lsr #13 @ extract max number of the index size
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loop2:
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mov r9, r4 @ create working copy of max way size
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loop3:
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ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
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ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
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THUMB( lsl r6, r9, r5 )
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THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
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THUMB( lsl r6, r7, r2 )
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THUMB( orr r11, r11, r6 ) @ factor index number into r11
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mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
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subs r9, r9, #1 @ decrement the way
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bge loop3
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subs r7, r7, #1 @ decrement the index
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bge loop2
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skip:
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add r10, r10, #2 @ increment cache number
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cmp r3, r10
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bgt loop1
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finished:
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ldmfd sp!, {r0-r7, r9-r11}
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mov r10, #0 @ switch back to cache level 0
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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dcache_line_size r1, r2 @ r1 := dcache min line size
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sub r2, r1, #1 @ r2 := line size mask
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bic r0, r0, r2 @ round down start to line size
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sub r11, r11, #1 @ end address is exclusive
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bic r11, r11, r2 @ round down end to line size
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0: cmp r0, r11 @ finished?
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bgt iflush
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mcr p15, 0, r0, c7, c14, 1 @ Dcache clean/invalidate by VA
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add r0, r0, r1
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b 0b
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iflush:
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mcr p15, 0, r10, c7, c10, 4 @ DSB
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mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
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