i2c: Support for Netlogic XLR/XLS I2C controller.
Add support for the intergrated I2C controller on Netlogic
XLR/XLS MIPS SoC.
The changes are to add a new file i2c/buses/i2c-xlr.c, containing the
i2c bus implementation, and to update i2c/buses/{Kconfig,Makefile} to
add the CONFIG_I2C_XLR option.
Signed-off-by: Ganesan Ramalingam <ganesanr@netlogicmicro.com>
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
This commit is contained in:
Ganesan Ramalingam
Wolfram Sang
Родитель
3f0e1e4bb6
Коммит
401c3434c4
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@ -681,6 +681,16 @@ config I2C_XILINX
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This driver can also be built as a module. If so, the module
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will be called xilinx_i2c.
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config I2C_XLR
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tristate "XLR I2C support"
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depends on CPU_XLR
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help
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This driver enables support for the on-chip I2C interface of
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the Netlogic XLR/XLS MIPS processors.
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This driver can also be built as a module. If so, the module
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will be called i2c-xlr.
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config I2C_EG20T
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tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) I2C"
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depends on PCI
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@ -68,6 +68,7 @@ obj-$(CONFIG_I2C_TEGRA) += i2c-tegra.o
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obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
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obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
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obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
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obj-$(CONFIG_I2C_XLR) += i2c-xlr.o
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obj-$(CONFIG_I2C_EG20T) += i2c-eg20t.o
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# External I2C/SMBus adapter drivers
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@ -0,0 +1,278 @@
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/*
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* Copyright 2011, Netlogic Microsystems Inc.
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* Copyright 2004, Matt Porter <mporter@kernel.crashing.org>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/i2c.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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/* XLR I2C REGISTERS */
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#define XLR_I2C_CFG 0x00
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#define XLR_I2C_CLKDIV 0x01
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#define XLR_I2C_DEVADDR 0x02
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#define XLR_I2C_ADDR 0x03
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#define XLR_I2C_DATAOUT 0x04
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#define XLR_I2C_DATAIN 0x05
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#define XLR_I2C_STATUS 0x06
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#define XLR_I2C_STARTXFR 0x07
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#define XLR_I2C_BYTECNT 0x08
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#define XLR_I2C_HDSTATIM 0x09
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/* XLR I2C REGISTERS FLAGS */
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#define XLR_I2C_BUS_BUSY 0x01
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#define XLR_I2C_SDOEMPTY 0x02
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#define XLR_I2C_RXRDY 0x04
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#define XLR_I2C_ACK_ERR 0x08
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#define XLR_I2C_ARB_STARTERR 0x30
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/* Register Values */
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#define XLR_I2C_CFG_ADDR 0xF8
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#define XLR_I2C_CFG_NOADDR 0xFA
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#define XLR_I2C_STARTXFR_ND 0x02 /* No Data */
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#define XLR_I2C_STARTXFR_RD 0x01 /* Read */
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#define XLR_I2C_STARTXFR_WR 0x00 /* Write */
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#define XLR_I2C_TIMEOUT 10 /* timeout per byte in msec */
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/*
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* On XLR/XLS, we need to use __raw_ IO to read the I2C registers
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* because they are in the big-endian MMIO area on the SoC.
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*
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* The readl/writel implementation on XLR/XLS byteswaps, because
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* those are for its little-endian PCI space (see arch/mips/Kconfig).
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*/
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static inline void xlr_i2c_wreg(u32 __iomem *base, unsigned int reg, u32 val)
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{
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__raw_writel(val, base + reg);
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}
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static inline u32 xlr_i2c_rdreg(u32 __iomem *base, unsigned int reg)
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{
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return __raw_readl(base + reg);
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}
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struct xlr_i2c_private {
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struct i2c_adapter adap;
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u32 __iomem *iobase;
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};
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static int xlr_i2c_tx(struct xlr_i2c_private *priv, u16 len,
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u8 *buf, u16 addr)
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{
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struct i2c_adapter *adap = &priv->adap;
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unsigned long timeout, stoptime, checktime;
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u32 i2c_status;
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int pos, timedout;
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u8 offset, byte;
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offset = buf[0];
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xlr_i2c_wreg(priv->iobase, XLR_I2C_ADDR, offset);
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xlr_i2c_wreg(priv->iobase, XLR_I2C_DEVADDR, addr);
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xlr_i2c_wreg(priv->iobase, XLR_I2C_CFG, XLR_I2C_CFG_ADDR);
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xlr_i2c_wreg(priv->iobase, XLR_I2C_BYTECNT, len - 1);
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timeout = msecs_to_jiffies(XLR_I2C_TIMEOUT);
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stoptime = jiffies + timeout;
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timedout = 0;
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pos = 1;
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retry:
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if (len == 1) {
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xlr_i2c_wreg(priv->iobase, XLR_I2C_STARTXFR,
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XLR_I2C_STARTXFR_ND);
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} else {
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xlr_i2c_wreg(priv->iobase, XLR_I2C_DATAOUT, buf[pos]);
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xlr_i2c_wreg(priv->iobase, XLR_I2C_STARTXFR,
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XLR_I2C_STARTXFR_WR);
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}
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while (!timedout) {
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checktime = jiffies;
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i2c_status = xlr_i2c_rdreg(priv->iobase, XLR_I2C_STATUS);
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if (i2c_status & XLR_I2C_SDOEMPTY) {
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pos++;
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/* need to do a empty dataout after the last byte */
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byte = (pos < len) ? buf[pos] : 0;
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xlr_i2c_wreg(priv->iobase, XLR_I2C_DATAOUT, byte);
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/* reset timeout on successful xmit */
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stoptime = jiffies + timeout;
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}
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timedout = time_after(checktime, stoptime);
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if (i2c_status & XLR_I2C_ARB_STARTERR) {
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if (timedout)
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break;
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goto retry;
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}
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if (i2c_status & XLR_I2C_ACK_ERR)
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return -EIO;
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if ((i2c_status & XLR_I2C_BUS_BUSY) == 0 && pos >= len)
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return 0;
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}
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dev_err(&adap->dev, "I2C transmit timeout\n");
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return -ETIMEDOUT;
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}
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static int xlr_i2c_rx(struct xlr_i2c_private *priv, u16 len, u8 *buf, u16 addr)
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{
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struct i2c_adapter *adap = &priv->adap;
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u32 i2c_status;
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unsigned long timeout, stoptime, checktime;
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int nbytes, timedout;
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u8 byte;
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xlr_i2c_wreg(priv->iobase, XLR_I2C_CFG, XLR_I2C_CFG_NOADDR);
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xlr_i2c_wreg(priv->iobase, XLR_I2C_BYTECNT, len);
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xlr_i2c_wreg(priv->iobase, XLR_I2C_DEVADDR, addr);
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timeout = msecs_to_jiffies(XLR_I2C_TIMEOUT);
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stoptime = jiffies + timeout;
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timedout = 0;
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nbytes = 0;
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retry:
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xlr_i2c_wreg(priv->iobase, XLR_I2C_STARTXFR, XLR_I2C_STARTXFR_RD);
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while (!timedout) {
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checktime = jiffies;
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i2c_status = xlr_i2c_rdreg(priv->iobase, XLR_I2C_STATUS);
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if (i2c_status & XLR_I2C_RXRDY) {
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if (nbytes > len)
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return -EIO; /* should not happen */
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/* we need to do a dummy datain when nbytes == len */
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byte = xlr_i2c_rdreg(priv->iobase, XLR_I2C_DATAIN);
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if (nbytes < len)
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buf[nbytes] = byte;
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nbytes++;
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/* reset timeout on successful read */
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stoptime = jiffies + timeout;
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}
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timedout = time_after(checktime, stoptime);
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if (i2c_status & XLR_I2C_ARB_STARTERR) {
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if (timedout)
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break;
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goto retry;
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}
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if (i2c_status & XLR_I2C_ACK_ERR)
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return -EIO;
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if ((i2c_status & XLR_I2C_BUS_BUSY) == 0)
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return 0;
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}
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dev_err(&adap->dev, "I2C receive timeout\n");
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return -ETIMEDOUT;
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}
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static int xlr_i2c_xfer(struct i2c_adapter *adap,
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struct i2c_msg *msgs, int num)
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{
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struct i2c_msg *msg;
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int i;
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int ret = 0;
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struct xlr_i2c_private *priv = i2c_get_adapdata(adap);
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for (i = 0; ret == 0 && i < num; i++) {
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msg = &msgs[i];
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if (msg->flags & I2C_M_RD)
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ret = xlr_i2c_rx(priv, msg->len, &msg->buf[0],
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msg->addr);
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else
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ret = xlr_i2c_tx(priv, msg->len, &msg->buf[0],
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msg->addr);
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}
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return (ret != 0) ? ret : num;
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}
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static u32 xlr_func(struct i2c_adapter *adap)
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{
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/* Emulate SMBUS over I2C */
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return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C;
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}
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static struct i2c_algorithm xlr_i2c_algo = {
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.master_xfer = xlr_i2c_xfer,
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.functionality = xlr_func,
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};
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static int __devinit xlr_i2c_probe(struct platform_device *pdev)
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{
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struct xlr_i2c_private *priv;
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struct resource *res;
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int ret;
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->iobase = devm_request_and_ioremap(&pdev->dev, res);
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if (!priv->iobase) {
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dev_err(&pdev->dev, "devm_request_and_ioremap failed\n");
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return -EBUSY;
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}
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priv->adap.dev.parent = &pdev->dev;
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priv->adap.owner = THIS_MODULE;
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priv->adap.algo_data = priv;
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priv->adap.algo = &xlr_i2c_algo;
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priv->adap.nr = pdev->id;
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priv->adap.class = I2C_CLASS_HWMON;
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snprintf(priv->adap.name, sizeof(priv->adap.name), "xlr-i2c");
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i2c_set_adapdata(&priv->adap, priv);
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ret = i2c_add_numbered_adapter(&priv->adap);
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if (ret < 0) {
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dev_err(&priv->adap.dev, "Failed to add i2c bus.\n");
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return ret;
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}
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platform_set_drvdata(pdev, priv);
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dev_info(&priv->adap.dev, "Added I2C Bus.\n");
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return 0;
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}
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static int __devexit xlr_i2c_remove(struct platform_device *pdev)
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{
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struct xlr_i2c_private *priv;
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priv = platform_get_drvdata(pdev);
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i2c_del_adapter(&priv->adap);
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platform_set_drvdata(pdev, NULL);
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return 0;
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}
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static struct platform_driver xlr_i2c_driver = {
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.probe = xlr_i2c_probe,
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.remove = __devexit_p(xlr_i2c_remove),
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.driver = {
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.name = "xlr-i2cbus",
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.owner = THIS_MODULE,
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},
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};
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module_platform_driver(xlr_i2c_driver);
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MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@netlogicmicro.com>");
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MODULE_DESCRIPTION("XLR/XLS SoC I2C Controller driver");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:xlr-i2cbus");
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