ARM: pxa: separate the clock support into clock-{pxa2xx,pxa3xx}.c
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
This commit is contained in:
Eric Miao
Родитель
2e8581e756
Коммит
4029813c89
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@ -16,9 +16,9 @@ endif
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# Generic drivers that other drivers may depend upon
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# SoC-specific code
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obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa2xx.o pxa25x.o
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obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o pxa2xx.o pxa27x.o
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obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o
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obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa25x.o
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obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa27x.o
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obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o clock-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o
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obj-$(CONFIG_CPU_PXA300) += pxa300.o
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obj-$(CONFIG_CPU_PXA320) += pxa320.o
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obj-$(CONFIG_CPU_PXA930) += pxa930.o
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@ -0,0 +1,30 @@
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/*
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* linux/arch/arm/mach-pxa/clock-pxa2xx.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <mach/pxa2xx-regs.h>
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#include "clock.h"
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void clk_pxa2xx_cken_enable(struct clk *clk)
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{
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CKEN |= 1 << clk->cken;
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}
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void clk_pxa2xx_cken_disable(struct clk *clk)
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{
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CKEN &= ~(1 << clk->cken);
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}
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const struct clkops clk_pxa2xx_cken_ops = {
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.enable = clk_pxa2xx_cken_enable,
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.disable = clk_pxa2xx_cken_disable,
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};
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@ -0,0 +1,161 @@
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/*
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* linux/arch/arm/mach-pxa/clock-pxa3xx.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <mach/pxa3xx-regs.h>
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#include "clock.h"
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/* Crystal clock: 13MHz */
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#define BASE_CLK 13000000
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/* Ring Oscillator Clock: 60MHz */
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#define RO_CLK 60000000
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#define ACCR_D0CS (1 << 26)
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#define ACCR_PCCE (1 << 11)
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/* crystal frequency to static memory controller multiplier (SMCFS) */
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static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
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/* crystal frequency to HSIO bus frequency multiplier (HSS) */
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static unsigned char hss_mult[4] = { 8, 12, 16, 24 };
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/*
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* Get the clock frequency as reflected by CCSR and the turbo flag.
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* We assume these values have been applied via a fcs.
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* If info is not 0 we also display the current settings.
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*/
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unsigned int pxa3xx_get_clk_frequency_khz(int info)
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{
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unsigned long acsr, xclkcfg;
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unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
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/* Read XCLKCFG register turbo bit */
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__asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
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t = xclkcfg & 0x1;
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acsr = ACSR;
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xl = acsr & 0x1f;
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xn = (acsr >> 8) & 0x7;
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hss = (acsr >> 14) & 0x3;
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XL = xl * BASE_CLK;
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XN = xn * XL;
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ro = acsr & ACCR_D0CS;
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CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
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HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
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if (info) {
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pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
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RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
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(ro) ? "" : "in");
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pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
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XL / 1000000, (XL % 1000000) / 10000, xl);
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pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
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XN / 1000000, (XN % 1000000) / 10000, xn,
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(t) ? "" : "in");
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pr_info("HSIO bus clock: %d.%02dMHz\n",
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HSS / 1000000, (HSS % 1000000) / 10000);
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}
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return CLK / 1000;
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}
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/*
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* Return the current AC97 clock frequency.
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*/
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static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
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{
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unsigned long rate = 312000000;
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unsigned long ac97_div;
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ac97_div = AC97_DIV;
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/* This may loose precision for some rates but won't for the
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* standard 24.576MHz.
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*/
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rate /= (ac97_div >> 12) & 0x7fff;
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rate *= (ac97_div & 0xfff);
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return rate;
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}
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/*
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* Return the current HSIO bus clock frequency
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*/
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static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
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{
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unsigned long acsr;
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unsigned int hss, hsio_clk;
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acsr = ACSR;
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hss = (acsr >> 14) & 0x3;
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hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
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return hsio_clk;
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}
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void clk_pxa3xx_cken_enable(struct clk *clk)
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{
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unsigned long mask = 1ul << (clk->cken & 0x1f);
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if (clk->cken < 32)
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CKENA |= mask;
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else
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CKENB |= mask;
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}
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void clk_pxa3xx_cken_disable(struct clk *clk)
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{
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unsigned long mask = 1ul << (clk->cken & 0x1f);
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if (clk->cken < 32)
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CKENA &= ~mask;
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else
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CKENB &= ~mask;
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}
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const struct clkops clk_pxa3xx_cken_ops = {
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.enable = clk_pxa3xx_cken_enable,
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.disable = clk_pxa3xx_cken_disable,
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};
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const struct clkops clk_pxa3xx_hsio_ops = {
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.enable = clk_pxa3xx_cken_enable,
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.disable = clk_pxa3xx_cken_disable,
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.getrate = clk_pxa3xx_hsio_getrate,
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};
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const struct clkops clk_pxa3xx_ac97_ops = {
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.enable = clk_pxa3xx_cken_enable,
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.disable = clk_pxa3xx_cken_disable,
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.getrate = clk_pxa3xx_ac97_getrate,
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};
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static void clk_pout_enable(struct clk *clk)
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{
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OSCC |= OSCC_PEN;
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}
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static void clk_pout_disable(struct clk *clk)
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{
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OSCC &= ~OSCC_PEN;
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}
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const struct clkops clk_pxa3xx_pout_ops = {
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.enable = clk_pout_enable,
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.disable = clk_pout_disable,
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};
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@ -3,21 +3,12 @@
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/string.h>
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#include <linux/clk.h>
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#include <linux/spinlock.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <asm/clkdev.h>
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#include <mach/pxa2xx-regs.h>
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#include <mach/hardware.h>
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#include "devices.h"
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#include "generic.h"
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#include "clock.h"
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static DEFINE_SPINLOCK(clocks_lock);
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@ -63,18 +54,19 @@ unsigned long clk_get_rate(struct clk *clk)
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}
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EXPORT_SYMBOL(clk_get_rate);
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void clk_cken_enable(struct clk *clk)
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void clk_dummy_enable(struct clk *clk)
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{
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CKEN |= 1 << clk->cken;
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}
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void clk_cken_disable(struct clk *clk)
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void clk_dummy_disable(struct clk *clk)
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{
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CKEN &= ~(1 << clk->cken);
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}
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const struct clkops clk_cken_ops = {
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.enable = clk_cken_enable,
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.disable = clk_cken_disable,
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const struct clkops clk_dummy_ops = {
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.enable = clk_dummy_enable,
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.disable = clk_dummy_disable,
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};
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struct clk clk_dummy = {
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.ops = &clk_dummy_ops,
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};
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@ -14,6 +14,12 @@ struct clk {
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unsigned int enabled;
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};
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void clk_dummy_enable(struct clk *);
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void clk_dummy_disable(struct clk *);
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extern const struct clkops clk_dummy_ops;
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extern struct clk clk_dummy;
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#define INIT_CLKREG(_clk,_devname,_conname) \
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{ \
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.clk = _clk, \
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@ -34,18 +40,18 @@ struct clk clk_##_name = { \
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.delay = _delay, \
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}
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#define DEFINE_CKEN(_name, _cken, _rate, _delay) \
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#define DEFINE_PXA2_CKEN(_name, _cken, _rate, _delay) \
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struct clk clk_##_name = { \
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.ops = &clk_cken_ops, \
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.ops = &clk_pxa2xx_cken_ops, \
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.rate = _rate, \
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.cken = CKEN_##_cken, \
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.delay = _delay, \
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}
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extern const struct clkops clk_cken_ops;
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extern const struct clkops clk_pxa2xx_cken_ops;
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void clk_cken_enable(struct clk *clk);
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void clk_cken_disable(struct clk *clk);
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void clk_pxa2xx_cken_enable(struct clk *clk);
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void clk_pxa2xx_cken_disable(struct clk *clk);
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#ifdef CONFIG_PXA3xx
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#define DEFINE_PXA3_CKEN(_name, _cken, _rate, _delay) \
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@ -57,7 +63,10 @@ struct clk clk_##_name = { \
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}
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extern const struct clkops clk_pxa3xx_cken_ops;
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extern const struct clkops clk_pxa3xx_hsio_ops;
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extern const struct clkops clk_pxa3xx_ac97_ops;
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extern const struct clkops clk_pxa3xx_pout_ops;
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extern void clk_pxa3xx_cken_enable(struct clk *);
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extern void clk_pxa3xx_cken_disable(struct clk *);
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#endif
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@ -106,8 +106,8 @@ static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk)
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}
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static const struct clkops clk_pxa25x_lcd_ops = {
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.enable = clk_cken_enable,
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.disable = clk_cken_disable,
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.enable = clk_pxa2xx_cken_enable,
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.disable = clk_pxa2xx_cken_disable,
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.getrate = clk_pxa25x_lcd_getrate,
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};
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@ -162,31 +162,29 @@ static const struct clkops clk_pxa25x_gpio11_ops = {
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* 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
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* 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
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*/
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static DEFINE_CKEN(pxa25x_hwuart, HWUART, 14745600, 1);
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static struct clk_lookup pxa25x_hwuart_clkreg =
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INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL);
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/*
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* PXA 2xx clock declarations.
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*/
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static DEFINE_PXA2_CKEN(pxa25x_hwuart, HWUART, 14745600, 1);
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static DEFINE_PXA2_CKEN(pxa25x_ffuart, FFUART, 14745600, 1);
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static DEFINE_PXA2_CKEN(pxa25x_btuart, BTUART, 14745600, 1);
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static DEFINE_PXA2_CKEN(pxa25x_stuart, STUART, 14745600, 1);
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static DEFINE_PXA2_CKEN(pxa25x_usb, USB, 47923000, 5);
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static DEFINE_PXA2_CKEN(pxa25x_mmc, MMC, 19169000, 0);
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static DEFINE_PXA2_CKEN(pxa25x_i2c, I2C, 31949000, 0);
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static DEFINE_PXA2_CKEN(pxa25x_ssp, SSP, 3686400, 0);
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static DEFINE_PXA2_CKEN(pxa25x_nssp, NSSP, 3686400, 0);
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static DEFINE_PXA2_CKEN(pxa25x_assp, ASSP, 3686400, 0);
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static DEFINE_PXA2_CKEN(pxa25x_pwm0, PWM0, 3686400, 0);
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static DEFINE_PXA2_CKEN(pxa25x_pwm1, PWM1, 3686400, 0);
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static DEFINE_PXA2_CKEN(pxa25x_ac97, AC97, 24576000, 0);
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static DEFINE_PXA2_CKEN(pxa25x_i2s, I2S, 14745600, 0);
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static DEFINE_PXA2_CKEN(pxa25x_ficp, FICP, 47923000, 0);
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static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops);
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static DEFINE_CKEN(pxa25x_ffuart, FFUART, 14745600, 1);
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static DEFINE_CKEN(pxa25x_btuart, BTUART, 14745600, 1);
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static DEFINE_CKEN(pxa25x_stuart, STUART, 14745600, 1);
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static DEFINE_CKEN(pxa25x_usb, USB, 47923000, 5);
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static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0);
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static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0);
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static DEFINE_CKEN(pxa25x_mmc, MMC, 19169000, 0);
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static DEFINE_CKEN(pxa25x_i2c, I2C, 31949000, 0);
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static DEFINE_CKEN(pxa25x_ssp, SSP, 3686400, 0);
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static DEFINE_CKEN(pxa25x_nssp, NSSP, 3686400, 0);
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static DEFINE_CKEN(pxa25x_assp, ASSP, 3686400, 0);
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static DEFINE_CKEN(pxa25x_pwm0, PWM0, 3686400, 0);
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static DEFINE_CKEN(pxa25x_pwm1, PWM1, 3686400, 0);
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static DEFINE_CKEN(pxa25x_ac97, AC97, 24576000, 0);
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static DEFINE_CKEN(pxa25x_i2s, I2S, 14745600, 0);
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static DEFINE_CKEN(pxa25x_ficp, FICP, 47923000, 0);
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static struct clk_lookup pxa25x_clkregs[] = {
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INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL),
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@ -209,6 +207,9 @@ static struct clk_lookup pxa25x_clkregs[] = {
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INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
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};
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static struct clk_lookup pxa25x_hwuart_clkreg =
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INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL);
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#ifdef CONFIG_PM
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#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
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@ -161,36 +161,37 @@ static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
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}
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static const struct clkops clk_pxa27x_lcd_ops = {
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.enable = clk_cken_enable,
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.disable = clk_cken_disable,
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.enable = clk_pxa2xx_cken_enable,
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.disable = clk_pxa2xx_cken_disable,
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.getrate = clk_pxa27x_lcd_getrate,
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};
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static DEFINE_PXA2_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
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static DEFINE_PXA2_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
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static DEFINE_PXA2_CKEN(pxa27x_stuart, STUART, 14857000, 1);
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static DEFINE_PXA2_CKEN(pxa27x_i2s, I2S, 14682000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_i2c, I2C, 32842000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_usb, USB, 48000000, 5);
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static DEFINE_PXA2_CKEN(pxa27x_mmc, MMC, 19500000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_ficp, FICP, 48000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
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static DEFINE_PXA2_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
|
||||
static DEFINE_PXA2_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
|
||||
static DEFINE_PXA2_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
|
||||
static DEFINE_PXA2_CKEN(pxa27x_ac97, AC97, 24576000, 0);
|
||||
static DEFINE_PXA2_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
|
||||
static DEFINE_PXA2_CKEN(pxa27x_msl, MSL, 48000000, 0);
|
||||
static DEFINE_PXA2_CKEN(pxa27x_usim, USIM, 48000000, 0);
|
||||
static DEFINE_PXA2_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
|
||||
static DEFINE_PXA2_CKEN(pxa27x_im, IM, 0, 0);
|
||||
static DEFINE_PXA2_CKEN(pxa27x_memc, MEMC, 0, 0);
|
||||
|
||||
static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
|
||||
static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
|
||||
static DEFINE_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
|
||||
static DEFINE_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
|
||||
static DEFINE_CKEN(pxa27x_stuart, STUART, 14857000, 1);
|
||||
static DEFINE_CKEN(pxa27x_i2s, I2S, 14682000, 0);
|
||||
static DEFINE_CKEN(pxa27x_i2c, I2C, 32842000, 0);
|
||||
static DEFINE_CKEN(pxa27x_usb, USB, 48000000, 5);
|
||||
static DEFINE_CKEN(pxa27x_mmc, MMC, 19500000, 0);
|
||||
static DEFINE_CKEN(pxa27x_ficp, FICP, 48000000, 0);
|
||||
static DEFINE_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
|
||||
static DEFINE_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
|
||||
static DEFINE_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
|
||||
static DEFINE_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
|
||||
static DEFINE_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
|
||||
static DEFINE_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
|
||||
static DEFINE_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
|
||||
static DEFINE_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
|
||||
static DEFINE_CKEN(pxa27x_ac97, AC97, 24576000, 0);
|
||||
static DEFINE_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
|
||||
static DEFINE_CKEN(pxa27x_msl, MSL, 48000000, 0);
|
||||
static DEFINE_CKEN(pxa27x_usim, USIM, 48000000, 0);
|
||||
static DEFINE_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
|
||||
static DEFINE_CKEN(pxa27x_im, IM, 0, 0);
|
||||
static DEFINE_CKEN(pxa27x_memc, MEMC, 0, 0);
|
||||
|
||||
static struct clk_lookup pxa27x_clkregs[] = {
|
||||
INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
|
||||
|
|
|
|||
|
|
@ -38,184 +38,15 @@
|
|||
#include "devices.h"
|
||||
#include "clock.h"
|
||||
|
||||
/* Crystal clock: 13MHz */
|
||||
#define BASE_CLK 13000000
|
||||
|
||||
/* Ring Oscillator Clock: 60MHz */
|
||||
#define RO_CLK 60000000
|
||||
|
||||
#define ACCR_D0CS (1 << 26)
|
||||
#define ACCR_PCCE (1 << 11)
|
||||
|
||||
#define PECR_IE(n) ((1 << ((n) * 2)) << 28)
|
||||
#define PECR_IS(n) ((1 << ((n) * 2)) << 29)
|
||||
|
||||
/* crystal frequency to static memory controller multiplier (SMCFS) */
|
||||
static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
|
||||
|
||||
/* crystal frequency to HSIO bus frequency multiplier (HSS) */
|
||||
static unsigned char hss_mult[4] = { 8, 12, 16, 24 };
|
||||
|
||||
/*
|
||||
* Get the clock frequency as reflected by CCSR and the turbo flag.
|
||||
* We assume these values have been applied via a fcs.
|
||||
* If info is not 0 we also display the current settings.
|
||||
*/
|
||||
unsigned int pxa3xx_get_clk_frequency_khz(int info)
|
||||
{
|
||||
unsigned long acsr, xclkcfg;
|
||||
unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
|
||||
|
||||
/* Read XCLKCFG register turbo bit */
|
||||
__asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
|
||||
t = xclkcfg & 0x1;
|
||||
|
||||
acsr = ACSR;
|
||||
|
||||
xl = acsr & 0x1f;
|
||||
xn = (acsr >> 8) & 0x7;
|
||||
hss = (acsr >> 14) & 0x3;
|
||||
|
||||
XL = xl * BASE_CLK;
|
||||
XN = xn * XL;
|
||||
|
||||
ro = acsr & ACCR_D0CS;
|
||||
|
||||
CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
|
||||
HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
|
||||
|
||||
if (info) {
|
||||
pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
|
||||
RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
|
||||
(ro) ? "" : "in");
|
||||
pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
|
||||
XL / 1000000, (XL % 1000000) / 10000, xl);
|
||||
pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
|
||||
XN / 1000000, (XN % 1000000) / 10000, xn,
|
||||
(t) ? "" : "in");
|
||||
pr_info("HSIO bus clock: %d.%02dMHz\n",
|
||||
HSS / 1000000, (HSS % 1000000) / 10000);
|
||||
}
|
||||
|
||||
return CLK / 1000;
|
||||
}
|
||||
|
||||
void pxa3xx_clear_reset_status(unsigned int mask)
|
||||
{
|
||||
/* RESET_STATUS_* has a 1:1 mapping with ARSR */
|
||||
ARSR = mask;
|
||||
}
|
||||
|
||||
/*
|
||||
* Return the current AC97 clock frequency.
|
||||
*/
|
||||
static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
|
||||
{
|
||||
unsigned long rate = 312000000;
|
||||
unsigned long ac97_div;
|
||||
|
||||
ac97_div = AC97_DIV;
|
||||
|
||||
/* This may loose precision for some rates but won't for the
|
||||
* standard 24.576MHz.
|
||||
*/
|
||||
rate /= (ac97_div >> 12) & 0x7fff;
|
||||
rate *= (ac97_div & 0xfff);
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
/*
|
||||
* Return the current HSIO bus clock frequency
|
||||
*/
|
||||
static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
|
||||
{
|
||||
unsigned long acsr;
|
||||
unsigned int hss, hsio_clk;
|
||||
|
||||
acsr = ACSR;
|
||||
|
||||
hss = (acsr >> 14) & 0x3;
|
||||
hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
|
||||
|
||||
return hsio_clk;
|
||||
}
|
||||
|
||||
void clk_pxa3xx_cken_enable(struct clk *clk)
|
||||
{
|
||||
unsigned long mask = 1ul << (clk->cken & 0x1f);
|
||||
|
||||
if (clk->cken < 32)
|
||||
CKENA |= mask;
|
||||
else
|
||||
CKENB |= mask;
|
||||
}
|
||||
|
||||
void clk_pxa3xx_cken_disable(struct clk *clk)
|
||||
{
|
||||
unsigned long mask = 1ul << (clk->cken & 0x1f);
|
||||
|
||||
if (clk->cken < 32)
|
||||
CKENA &= ~mask;
|
||||
else
|
||||
CKENB &= ~mask;
|
||||
}
|
||||
|
||||
const struct clkops clk_pxa3xx_cken_ops = {
|
||||
.enable = clk_pxa3xx_cken_enable,
|
||||
.disable = clk_pxa3xx_cken_disable,
|
||||
};
|
||||
|
||||
static const struct clkops clk_pxa3xx_hsio_ops = {
|
||||
.enable = clk_pxa3xx_cken_enable,
|
||||
.disable = clk_pxa3xx_cken_disable,
|
||||
.getrate = clk_pxa3xx_hsio_getrate,
|
||||
};
|
||||
|
||||
static const struct clkops clk_pxa3xx_ac97_ops = {
|
||||
.enable = clk_pxa3xx_cken_enable,
|
||||
.disable = clk_pxa3xx_cken_disable,
|
||||
.getrate = clk_pxa3xx_ac97_getrate,
|
||||
};
|
||||
|
||||
static void clk_pout_enable(struct clk *clk)
|
||||
{
|
||||
OSCC |= OSCC_PEN;
|
||||
}
|
||||
|
||||
static void clk_pout_disable(struct clk *clk)
|
||||
{
|
||||
OSCC &= ~OSCC_PEN;
|
||||
}
|
||||
|
||||
static const struct clkops clk_pout_ops = {
|
||||
.enable = clk_pout_enable,
|
||||
.disable = clk_pout_disable,
|
||||
};
|
||||
|
||||
static void clk_dummy_enable(struct clk *clk)
|
||||
{
|
||||
}
|
||||
|
||||
static void clk_dummy_disable(struct clk *clk)
|
||||
{
|
||||
}
|
||||
|
||||
static const struct clkops clk_dummy_ops = {
|
||||
.enable = clk_dummy_enable,
|
||||
.disable = clk_dummy_disable,
|
||||
};
|
||||
|
||||
static struct clk clk_pxa3xx_pout = {
|
||||
.ops = &clk_pout_ops,
|
||||
.rate = 13000000,
|
||||
.delay = 70,
|
||||
};
|
||||
|
||||
static struct clk clk_dummy = {
|
||||
.ops = &clk_dummy_ops,
|
||||
};
|
||||
|
||||
static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
|
||||
static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
|
||||
static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
|
||||
|
|
@ -236,6 +67,7 @@ static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
|
|||
static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
|
||||
static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
|
||||
static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
|
||||
static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70);
|
||||
|
||||
static struct clk_lookup pxa3xx_clkregs[] = {
|
||||
INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
|
||||
|
|
|
|||
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