i40e/i40evf: Only track one ITR setting per ring instead of Tx/Rx
The rings are already split out into Tx and Rx rings so it doesn't make sense to have any single ring store both a Tx and Rx itr_setting value. Since that is the case drop the pair in favor of storing just a single ITR value. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Родитель
11a350c965
Коммит
40588ca651
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@ -315,9 +315,9 @@ static void i40e_dbg_dump_vsi_seid(struct i40e_pf *pf, int seid)
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i, rx_ring->vsi,
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rx_ring->q_vector);
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dev_info(&pf->pdev->dev,
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" rx_rings[%i]: rx_itr_setting = %d (%s)\n",
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i, rx_ring->rx_itr_setting,
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ITR_IS_DYNAMIC(rx_ring->rx_itr_setting) ? "dynamic" : "fixed");
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" rx_rings[%i]: itr_setting = %d (%s)\n",
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i, rx_ring->itr_setting,
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ITR_IS_DYNAMIC(rx_ring->itr_setting) ? "dynamic" : "fixed");
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}
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for (i = 0; i < vsi->num_queue_pairs; i++) {
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struct i40e_ring *tx_ring = READ_ONCE(vsi->tx_rings[i]);
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@ -366,9 +366,9 @@ static void i40e_dbg_dump_vsi_seid(struct i40e_pf *pf, int seid)
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" tx_rings[%i]: DCB tc = %d\n",
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i, tx_ring->dcb_tc);
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dev_info(&pf->pdev->dev,
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" tx_rings[%i]: tx_itr_setting = %d (%s)\n",
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i, tx_ring->tx_itr_setting,
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ITR_IS_DYNAMIC(tx_ring->tx_itr_setting) ? "dynamic" : "fixed");
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" tx_rings[%i]: itr_setting = %d (%s)\n",
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i, tx_ring->itr_setting,
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ITR_IS_DYNAMIC(tx_ring->itr_setting) ? "dynamic" : "fixed");
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}
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rcu_read_unlock();
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dev_info(&pf->pdev->dev,
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@ -2244,14 +2244,14 @@ static int __i40e_get_coalesce(struct net_device *netdev,
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rx_ring = vsi->rx_rings[queue];
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tx_ring = vsi->tx_rings[queue];
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if (ITR_IS_DYNAMIC(rx_ring->rx_itr_setting))
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if (ITR_IS_DYNAMIC(rx_ring->itr_setting))
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ec->use_adaptive_rx_coalesce = 1;
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if (ITR_IS_DYNAMIC(tx_ring->tx_itr_setting))
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if (ITR_IS_DYNAMIC(tx_ring->itr_setting))
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ec->use_adaptive_tx_coalesce = 1;
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ec->rx_coalesce_usecs = rx_ring->rx_itr_setting & ~I40E_ITR_DYNAMIC;
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ec->tx_coalesce_usecs = tx_ring->tx_itr_setting & ~I40E_ITR_DYNAMIC;
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ec->rx_coalesce_usecs = rx_ring->itr_setting & ~I40E_ITR_DYNAMIC;
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ec->tx_coalesce_usecs = tx_ring->itr_setting & ~I40E_ITR_DYNAMIC;
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/* we use the _usecs_high to store/set the interrupt rate limit
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* that the hardware supports, that almost but not quite
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@ -2315,26 +2315,26 @@ static void i40e_set_itr_per_queue(struct i40e_vsi *vsi,
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intrl = i40e_intrl_usec_to_reg(vsi->int_rate_limit);
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rx_ring->rx_itr_setting = ec->rx_coalesce_usecs;
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tx_ring->tx_itr_setting = ec->tx_coalesce_usecs;
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rx_ring->itr_setting = ec->rx_coalesce_usecs;
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tx_ring->itr_setting = ec->tx_coalesce_usecs;
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if (ec->use_adaptive_rx_coalesce)
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rx_ring->rx_itr_setting |= I40E_ITR_DYNAMIC;
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rx_ring->itr_setting |= I40E_ITR_DYNAMIC;
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else
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rx_ring->rx_itr_setting &= ~I40E_ITR_DYNAMIC;
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rx_ring->itr_setting &= ~I40E_ITR_DYNAMIC;
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if (ec->use_adaptive_tx_coalesce)
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tx_ring->tx_itr_setting |= I40E_ITR_DYNAMIC;
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tx_ring->itr_setting |= I40E_ITR_DYNAMIC;
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else
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tx_ring->tx_itr_setting &= ~I40E_ITR_DYNAMIC;
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tx_ring->itr_setting &= ~I40E_ITR_DYNAMIC;
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q_vector = rx_ring->q_vector;
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q_vector->rx.itr = ITR_TO_REG(rx_ring->rx_itr_setting);
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q_vector->rx.itr = ITR_TO_REG(rx_ring->itr_setting);
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vector = vsi->base_vector + q_vector->v_idx;
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wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1), q_vector->rx.itr);
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q_vector = tx_ring->q_vector;
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q_vector->tx.itr = ITR_TO_REG(tx_ring->tx_itr_setting);
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q_vector->tx.itr = ITR_TO_REG(tx_ring->itr_setting);
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vector = vsi->base_vector + q_vector->v_idx;
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wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1), q_vector->tx.itr);
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@ -2364,11 +2364,11 @@ static int __i40e_set_coalesce(struct net_device *netdev,
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vsi->work_limit = ec->tx_max_coalesced_frames_irq;
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if (queue < 0) {
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cur_rx_itr = vsi->rx_rings[0]->rx_itr_setting;
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cur_tx_itr = vsi->tx_rings[0]->tx_itr_setting;
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cur_rx_itr = vsi->rx_rings[0]->itr_setting;
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cur_tx_itr = vsi->tx_rings[0]->itr_setting;
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} else if (queue < vsi->num_queue_pairs) {
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cur_rx_itr = vsi->rx_rings[queue]->rx_itr_setting;
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cur_tx_itr = vsi->tx_rings[queue]->tx_itr_setting;
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cur_rx_itr = vsi->rx_rings[queue]->itr_setting;
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cur_tx_itr = vsi->tx_rings[queue]->itr_setting;
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} else {
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netif_info(pf, drv, netdev, "Invalid queue value, queue range is 0 - %d\n",
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vsi->num_queue_pairs - 1);
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@ -3450,11 +3450,11 @@ static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
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struct i40e_q_vector *q_vector = vsi->q_vectors[i];
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q_vector->itr_countdown = ITR_COUNTDOWN_START;
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q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[i]->rx_itr_setting);
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q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[i]->itr_setting);
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q_vector->rx.latency_range = I40E_LOW_LATENCY;
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wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
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q_vector->rx.itr);
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q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[i]->tx_itr_setting);
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q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[i]->itr_setting);
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q_vector->tx.latency_range = I40E_LOW_LATENCY;
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wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
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q_vector->tx.itr);
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@ -3559,10 +3559,10 @@ static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
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/* set the ITR configuration */
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q_vector->itr_countdown = ITR_COUNTDOWN_START;
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q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[0]->rx_itr_setting);
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q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[0]->itr_setting);
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q_vector->rx.latency_range = I40E_LOW_LATENCY;
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wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
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q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[0]->tx_itr_setting);
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q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[0]->itr_setting);
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q_vector->tx.latency_range = I40E_LOW_LATENCY;
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wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
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@ -10018,7 +10018,7 @@ static int i40e_alloc_rings(struct i40e_vsi *vsi)
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ring->dcb_tc = 0;
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if (vsi->back->hw_features & I40E_HW_WB_ON_ITR_CAPABLE)
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ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
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ring->tx_itr_setting = pf->tx_itr_default;
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ring->itr_setting = pf->tx_itr_default;
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vsi->tx_rings[i] = ring++;
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if (!i40e_enabled_xdp_vsi(vsi))
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@ -10036,7 +10036,7 @@ static int i40e_alloc_rings(struct i40e_vsi *vsi)
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if (vsi->back->hw_features & I40E_HW_WB_ON_ITR_CAPABLE)
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ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
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set_ring_xdp(ring);
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ring->tx_itr_setting = pf->tx_itr_default;
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ring->itr_setting = pf->tx_itr_default;
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vsi->xdp_rings[i] = ring++;
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setup_rx:
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@ -10049,7 +10049,7 @@ setup_rx:
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ring->count = vsi->num_desc;
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ring->size = 0;
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ring->dcb_tc = 0;
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ring->rx_itr_setting = pf->rx_itr_default;
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ring->itr_setting = pf->rx_itr_default;
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vsi->rx_rings[i] = ring;
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}
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@ -2290,12 +2290,12 @@ static u32 i40e_buildreg_itr(const int type, const u16 itr)
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#define INTREG I40E_PFINT_DYN_CTLN
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static inline int get_rx_itr(struct i40e_vsi *vsi, int idx)
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{
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return vsi->rx_rings[idx]->rx_itr_setting;
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return vsi->rx_rings[idx]->itr_setting;
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}
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static inline int get_tx_itr(struct i40e_vsi *vsi, int idx)
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{
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return vsi->tx_rings[idx]->tx_itr_setting;
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return vsi->tx_rings[idx]->itr_setting;
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}
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/**
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@ -2322,7 +2322,7 @@ static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
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/* avoid dynamic calculation if in countdown mode OR if
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* all dynamic is disabled
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*/
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rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
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txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
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rx_itr_setting = get_rx_itr(vsi, idx);
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tx_itr_setting = get_tx_itr(vsi, idx);
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@ -382,8 +382,7 @@ struct i40e_ring {
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* these values always store the USER setting, and must be converted
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* before programming to a register.
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*/
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u16 rx_itr_setting;
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u16 tx_itr_setting;
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u16 itr_setting;
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u16 count; /* Number of descriptors */
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u16 reg_idx; /* HW register index of the ring */
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@ -1475,14 +1475,14 @@ static inline int get_rx_itr(struct i40e_vsi *vsi, int idx)
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{
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struct i40evf_adapter *adapter = vsi->back;
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return adapter->rx_rings[idx].rx_itr_setting;
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return adapter->rx_rings[idx].itr_setting;
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}
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static inline int get_tx_itr(struct i40e_vsi *vsi, int idx)
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{
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struct i40evf_adapter *adapter = vsi->back;
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return adapter->tx_rings[idx].tx_itr_setting;
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return adapter->tx_rings[idx].itr_setting;
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}
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/**
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@ -1503,7 +1503,7 @@ static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
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/* avoid dynamic calculation if in countdown mode OR if
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* all dynamic is disabled
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*/
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rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
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txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
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rx_itr_setting = get_rx_itr(vsi, idx);
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tx_itr_setting = get_tx_itr(vsi, idx);
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@ -362,8 +362,7 @@ struct i40e_ring {
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* these values always store the USER setting, and must be converted
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* before programming to a register.
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*/
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u16 rx_itr_setting;
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u16 tx_itr_setting;
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u16 itr_setting;
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u16 count; /* Number of descriptors */
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u16 reg_idx; /* HW register index of the ring */
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@ -457,14 +457,14 @@ static int __i40evf_get_coalesce(struct net_device *netdev,
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rx_ring = &adapter->rx_rings[queue];
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tx_ring = &adapter->tx_rings[queue];
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if (ITR_IS_DYNAMIC(rx_ring->rx_itr_setting))
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if (ITR_IS_DYNAMIC(rx_ring->itr_setting))
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ec->use_adaptive_rx_coalesce = 1;
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if (ITR_IS_DYNAMIC(tx_ring->tx_itr_setting))
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if (ITR_IS_DYNAMIC(tx_ring->itr_setting))
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ec->use_adaptive_tx_coalesce = 1;
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ec->rx_coalesce_usecs = rx_ring->rx_itr_setting & ~I40E_ITR_DYNAMIC;
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ec->tx_coalesce_usecs = tx_ring->tx_itr_setting & ~I40E_ITR_DYNAMIC;
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ec->rx_coalesce_usecs = rx_ring->itr_setting & ~I40E_ITR_DYNAMIC;
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ec->tx_coalesce_usecs = tx_ring->itr_setting & ~I40E_ITR_DYNAMIC;
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return 0;
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}
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@ -519,24 +519,24 @@ static void i40evf_set_itr_per_queue(struct i40evf_adapter *adapter,
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struct i40e_q_vector *q_vector;
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u16 vector;
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rx_ring->rx_itr_setting = ec->rx_coalesce_usecs;
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tx_ring->tx_itr_setting = ec->tx_coalesce_usecs;
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rx_ring->itr_setting = ec->rx_coalesce_usecs;
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tx_ring->itr_setting = ec->tx_coalesce_usecs;
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rx_ring->rx_itr_setting |= I40E_ITR_DYNAMIC;
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rx_ring->itr_setting |= I40E_ITR_DYNAMIC;
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if (!ec->use_adaptive_rx_coalesce)
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rx_ring->rx_itr_setting ^= I40E_ITR_DYNAMIC;
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rx_ring->itr_setting ^= I40E_ITR_DYNAMIC;
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tx_ring->tx_itr_setting |= I40E_ITR_DYNAMIC;
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tx_ring->itr_setting |= I40E_ITR_DYNAMIC;
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if (!ec->use_adaptive_tx_coalesce)
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tx_ring->tx_itr_setting ^= I40E_ITR_DYNAMIC;
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tx_ring->itr_setting ^= I40E_ITR_DYNAMIC;
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q_vector = rx_ring->q_vector;
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q_vector->rx.itr = ITR_TO_REG(rx_ring->rx_itr_setting);
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q_vector->rx.itr = ITR_TO_REG(rx_ring->itr_setting);
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vector = vsi->base_vector + q_vector->v_idx;
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wr32(hw, I40E_VFINT_ITRN1(I40E_RX_ITR, vector - 1), q_vector->rx.itr);
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q_vector = tx_ring->q_vector;
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q_vector->tx.itr = ITR_TO_REG(tx_ring->tx_itr_setting);
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q_vector->tx.itr = ITR_TO_REG(tx_ring->itr_setting);
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vector = vsi->base_vector + q_vector->v_idx;
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wr32(hw, I40E_VFINT_ITRN1(I40E_TX_ITR, vector - 1), q_vector->tx.itr);
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@ -354,7 +354,7 @@ i40evf_map_vector_to_rxq(struct i40evf_adapter *adapter, int v_idx, int r_idx)
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q_vector->rx.ring = rx_ring;
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q_vector->rx.count++;
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q_vector->rx.latency_range = I40E_LOW_LATENCY;
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q_vector->rx.itr = ITR_TO_REG(rx_ring->rx_itr_setting);
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q_vector->rx.itr = ITR_TO_REG(rx_ring->itr_setting);
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q_vector->ring_mask |= BIT(r_idx);
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q_vector->itr_countdown = ITR_COUNTDOWN_START;
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wr32(hw, I40E_VFINT_ITRN1(I40E_RX_ITR, v_idx - 1), q_vector->rx.itr);
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@ -379,7 +379,7 @@ i40evf_map_vector_to_txq(struct i40evf_adapter *adapter, int v_idx, int t_idx)
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q_vector->tx.ring = tx_ring;
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q_vector->tx.count++;
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q_vector->tx.latency_range = I40E_LOW_LATENCY;
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q_vector->tx.itr = ITR_TO_REG(tx_ring->tx_itr_setting);
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q_vector->tx.itr = ITR_TO_REG(tx_ring->itr_setting);
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q_vector->itr_countdown = ITR_COUNTDOWN_START;
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q_vector->num_ringpairs++;
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wr32(hw, I40E_VFINT_ITRN1(I40E_TX_ITR, v_idx - 1), q_vector->tx.itr);
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@ -1169,7 +1169,7 @@ static int i40evf_alloc_queues(struct i40evf_adapter *adapter)
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tx_ring->netdev = adapter->netdev;
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tx_ring->dev = &adapter->pdev->dev;
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tx_ring->count = adapter->tx_desc_count;
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tx_ring->tx_itr_setting = I40E_ITR_TX_DEF;
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tx_ring->itr_setting = I40E_ITR_TX_DEF;
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if (adapter->flags & I40EVF_FLAG_WB_ON_ITR_CAPABLE)
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tx_ring->flags |= I40E_TXR_FLAGS_WB_ON_ITR;
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@ -1178,7 +1178,7 @@ static int i40evf_alloc_queues(struct i40evf_adapter *adapter)
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rx_ring->netdev = adapter->netdev;
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rx_ring->dev = &adapter->pdev->dev;
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rx_ring->count = adapter->rx_desc_count;
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rx_ring->rx_itr_setting = I40E_ITR_RX_DEF;
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rx_ring->itr_setting = I40E_ITR_RX_DEF;
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}
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adapter->num_active_queues = num_active_queues;
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