ALSA: hda - Allow different ops to read/write registers
The forthcoming platform hda driver needs to override the way registers are read and written. In preparation for that, introduce a reg_ops struct that can be implemented differently by the new driver. Change the existing macros to use the new structure, and move them to hda_priv.h where they will be accessible to both PCI and platform drivers. Start with register access, but later commits will add more ops that differ between PCI and platform. Signed-off-by: Dylan Reid <dgreid@chromium.org> Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Dylan Reid
Takashi Iwai
Родитель
2538a4f583
Коммит
4083081333
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@ -293,35 +293,6 @@ static char *driver_short_names[] = {
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[AZX_DRIVER_GENERIC] = "HD-Audio Generic",
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};
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/*
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* macros for easy use
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*/
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#define azx_writel(chip,reg,value) \
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writel(value, (chip)->remap_addr + ICH6_REG_##reg)
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#define azx_readl(chip,reg) \
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readl((chip)->remap_addr + ICH6_REG_##reg)
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#define azx_writew(chip,reg,value) \
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writew(value, (chip)->remap_addr + ICH6_REG_##reg)
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#define azx_readw(chip,reg) \
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readw((chip)->remap_addr + ICH6_REG_##reg)
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#define azx_writeb(chip,reg,value) \
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writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
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#define azx_readb(chip,reg) \
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readb((chip)->remap_addr + ICH6_REG_##reg)
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#define azx_sd_writel(dev,reg,value) \
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writel(value, (dev)->sd_addr + ICH6_REG_##reg)
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#define azx_sd_readl(dev,reg) \
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readl((dev)->sd_addr + ICH6_REG_##reg)
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#define azx_sd_writew(dev,reg,value) \
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writew(value, (dev)->sd_addr + ICH6_REG_##reg)
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#define azx_sd_readw(dev,reg) \
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readw((dev)->sd_addr + ICH6_REG_##reg)
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#define azx_sd_writeb(dev,reg,value) \
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writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
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#define azx_sd_readb(dev,reg) \
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readb((dev)->sd_addr + ICH6_REG_##reg)
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/* for pcm support */
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#define get_azx_dev(substream) (substream->runtime->private_data)
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@ -876,8 +847,9 @@ static void azx_int_disable(struct azx *chip)
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/* disable interrupts in stream descriptor */
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for (i = 0; i < chip->num_streams; i++) {
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struct azx_dev *azx_dev = &chip->azx_dev[i];
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azx_sd_writeb(azx_dev, SD_CTL,
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azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
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azx_sd_writeb(chip, azx_dev, SD_CTL,
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azx_sd_readb(chip, azx_dev, SD_CTL) &
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~SD_INT_MASK);
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}
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/* disable SIE for all streams */
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@ -896,7 +868,7 @@ static void azx_int_clear(struct azx *chip)
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/* clear stream status */
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for (i = 0; i < chip->num_streams; i++) {
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struct azx_dev *azx_dev = &chip->azx_dev[i];
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azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
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azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
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}
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/* clear STATESTS */
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@ -921,16 +893,18 @@ static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
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azx_writel(chip, INTCTL,
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azx_readl(chip, INTCTL) | (1 << azx_dev->index));
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/* set DMA start and interrupt mask */
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azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
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azx_sd_writeb(chip, azx_dev, SD_CTL,
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azx_sd_readb(chip, azx_dev, SD_CTL) |
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SD_CTL_DMA_START | SD_INT_MASK);
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}
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/* stop DMA */
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static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
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{
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azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
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azx_sd_writeb(chip, azx_dev, SD_CTL,
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azx_sd_readb(chip, azx_dev, SD_CTL) &
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~(SD_CTL_DMA_START | SD_INT_MASK));
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azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
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azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
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}
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/* stop a stream */
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@ -1078,8 +1052,8 @@ static irqreturn_t azx_interrupt(int irq, void *dev_id)
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for (i = 0; i < chip->num_streams; i++) {
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azx_dev = &chip->azx_dev[i];
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if (status & azx_dev->sd_int_sta_mask) {
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sd_status = azx_sd_readb(azx_dev, SD_STS);
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azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
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sd_status = azx_sd_readb(chip, azx_dev, SD_STS);
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azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
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if (!azx_dev->substream || !azx_dev->running ||
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!(sd_status & SD_INT_COMPLETE))
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continue;
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@ -1176,8 +1150,8 @@ static int azx_setup_periods(struct azx *chip,
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int pos_adj;
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/* reset BDL address */
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azx_sd_writel(azx_dev, SD_BDLPL, 0);
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azx_sd_writel(azx_dev, SD_BDLPU, 0);
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azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
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azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
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period_bytes = azx_dev->period_bytes;
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periods = azx_dev->bufsize / period_bytes;
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@ -1239,21 +1213,22 @@ static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
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azx_stream_clear(chip, azx_dev);
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azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
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azx_sd_writeb(chip, azx_dev, SD_CTL,
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azx_sd_readb(chip, azx_dev, SD_CTL) |
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SD_CTL_STREAM_RESET);
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udelay(3);
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timeout = 300;
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while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
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--timeout)
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while (!((val = azx_sd_readb(chip, azx_dev, SD_CTL)) &
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SD_CTL_STREAM_RESET) && --timeout)
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;
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val &= ~SD_CTL_STREAM_RESET;
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azx_sd_writeb(azx_dev, SD_CTL, val);
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azx_sd_writeb(chip, azx_dev, SD_CTL, val);
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udelay(3);
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timeout = 300;
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/* waiting for hardware to report that the stream is out of reset */
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while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
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--timeout)
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while (((val = azx_sd_readb(chip, azx_dev, SD_CTL)) &
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SD_CTL_STREAM_RESET) && --timeout)
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;
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/* reset first position - may not be synced with hw at this time */
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@ -1269,28 +1244,29 @@ static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
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/* make sure the run bit is zero for SD */
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azx_stream_clear(chip, azx_dev);
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/* program the stream_tag */
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val = azx_sd_readl(azx_dev, SD_CTL);
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val = azx_sd_readl(chip, azx_dev, SD_CTL);
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val = (val & ~SD_CTL_STREAM_TAG_MASK) |
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(azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
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if (!azx_snoop(chip))
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val |= SD_CTL_TRAFFIC_PRIO;
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azx_sd_writel(azx_dev, SD_CTL, val);
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azx_sd_writel(chip, azx_dev, SD_CTL, val);
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/* program the length of samples in cyclic buffer */
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azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
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azx_sd_writel(chip, azx_dev, SD_CBL, azx_dev->bufsize);
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/* program the stream format */
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/* this value needs to be the same as the one programmed */
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azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
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azx_sd_writew(chip, azx_dev, SD_FORMAT, azx_dev->format_val);
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/* program the stream LVI (last valid index) of the BDL */
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azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
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azx_sd_writew(chip, azx_dev, SD_LVI, azx_dev->frags - 1);
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/* program the BDL address */
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/* lower BDL address */
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azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
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azx_sd_writel(chip, azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
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/* upper BDL address */
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azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
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azx_sd_writel(chip, azx_dev, SD_BDLPU,
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upper_32_bits(azx_dev->bdl.addr));
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/* enable the position buffer */
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if (chip->position_fix[0] != POS_FIX_LPIB ||
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@ -1301,8 +1277,8 @@ static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
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}
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/* set the interrupt enable bits in the descriptor control register */
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azx_sd_writel(azx_dev, SD_CTL,
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azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
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azx_sd_writel(chip, azx_dev, SD_CTL,
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azx_sd_readl(chip, azx_dev, SD_CTL) | SD_INT_MASK);
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return 0;
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}
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@ -1776,9 +1752,9 @@ static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
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/* reset BDL address */
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dsp_lock(azx_dev);
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if (!dsp_is_locked(azx_dev)) {
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azx_sd_writel(azx_dev, SD_BDLPL, 0);
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azx_sd_writel(azx_dev, SD_BDLPU, 0);
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azx_sd_writel(azx_dev, SD_CTL, 0);
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azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
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azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
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azx_sd_writel(chip, azx_dev, SD_CTL, 0);
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azx_dev->bufsize = 0;
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azx_dev->period_bytes = 0;
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azx_dev->format_val = 0;
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@ -1858,7 +1834,8 @@ static int azx_pcm_prepare(struct snd_pcm_substream *substream)
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runtime->rate) * 1000);
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azx_setup_controller(chip, azx_dev);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
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azx_dev->fifo_size =
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azx_sd_readw(chip, azx_dev, SD_FIFOSIZE) + 1;
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else
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azx_dev->fifo_size = 0;
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@ -1950,7 +1927,7 @@ static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
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if (s->pcm->card != substream->pcm->card)
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continue;
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azx_dev = get_azx_dev(s);
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if (!(azx_sd_readb(azx_dev, SD_STS) &
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if (!(azx_sd_readb(chip, azx_dev, SD_STS) &
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SD_STS_FIFO_READY))
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nwait++;
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}
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@ -1966,7 +1943,7 @@ static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
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if (s->pcm->card != substream->pcm->card)
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continue;
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azx_dev = get_azx_dev(s);
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if (azx_sd_readb(azx_dev, SD_CTL) &
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if (azx_sd_readb(chip, azx_dev, SD_CTL) &
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SD_CTL_DMA_START)
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nwait++;
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}
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@ -2010,7 +1987,7 @@ static unsigned int azx_via_get_position(struct azx *chip,
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unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
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unsigned int fifo_size;
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link_pos = azx_sd_readl(azx_dev, SD_LPIB);
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link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
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if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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/* Playback, no problem using link position */
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return link_pos;
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@ -2072,7 +2049,7 @@ static unsigned int azx_get_position(struct azx *chip,
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switch (chip->position_fix[stream]) {
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case POS_FIX_LPIB:
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/* read LPIB */
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pos = azx_sd_readl(azx_dev, SD_LPIB);
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pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
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break;
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case POS_FIX_VIACOMBO:
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pos = azx_via_get_position(chip, azx_dev);
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@ -2085,7 +2062,7 @@ static unsigned int azx_get_position(struct azx *chip,
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dev_info(chip->card->dev,
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"Invalid position buffer, using LPIB read method instead.\n");
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chip->position_fix[stream] = POS_FIX_LPIB;
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pos = azx_sd_readl(azx_dev, SD_LPIB);
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pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
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} else
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chip->position_fix[stream] = POS_FIX_POSBUF;
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}
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@ -2099,7 +2076,7 @@ static unsigned int azx_get_position(struct azx *chip,
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if (substream->runtime &&
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chip->position_fix[stream] == POS_FIX_POSBUF &&
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(chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
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unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
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unsigned int lpib_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
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if (stream == SNDRV_PCM_STREAM_PLAYBACK)
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delay = pos - lpib_pos;
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else
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@ -2438,8 +2415,8 @@ static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
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azx_stream_reset(chip, azx_dev);
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/* reset BDL address */
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azx_sd_writel(azx_dev, SD_BDLPL, 0);
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azx_sd_writel(azx_dev, SD_BDLPU, 0);
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azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
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azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
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azx_dev->frags = 0;
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bdl = (u32 *)azx_dev->bdl.area;
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@ -2488,9 +2465,9 @@ static void azx_load_dsp_cleanup(struct hda_bus *bus,
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dsp_lock(azx_dev);
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/* reset BDL address */
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azx_sd_writel(azx_dev, SD_BDLPL, 0);
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azx_sd_writel(azx_dev, SD_BDLPU, 0);
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azx_sd_writel(azx_dev, SD_CTL, 0);
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azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
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azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
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azx_sd_writel(chip, azx_dev, SD_CTL, 0);
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azx_dev->bufsize = 0;
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azx_dev->period_bytes = 0;
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azx_dev->format_val = 0;
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@ -3167,6 +3144,7 @@ static void azx_probe_work(struct work_struct *work)
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*/
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static int azx_create(struct snd_card *card, struct pci_dev *pci,
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int dev, unsigned int driver_caps,
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const struct hda_controller_ops *hda_ops,
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struct azx **rchip)
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{
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static struct snd_device_ops ops = {
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|
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@ -3192,6 +3170,7 @@ static int azx_create(struct snd_card *card, struct pci_dev *pci,
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mutex_init(&chip->open_mutex);
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chip->card = card;
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chip->pci = pci;
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chip->ops = hda_ops;
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chip->irq = -1;
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chip->driver_caps = driver_caps;
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chip->driver_type = driver_caps & 0xff;
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@ -3450,6 +3429,50 @@ static void azx_firmware_cb(const struct firmware *fw, void *context)
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}
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#endif
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/*
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* HDA controller ops.
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*/
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/* PCI register access. */
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static void pci_azx_writel(u32 value, u32 *addr)
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{
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writel(value, addr);
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}
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static u32 pci_azx_readl(u32 *addr)
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{
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return readl(addr);
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}
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static void pci_azx_writew(u16 value, u16 *addr)
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{
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writew(value, addr);
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}
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static u16 pci_azx_readw(u16 *addr)
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{
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return readw(addr);
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}
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static void pci_azx_writeb(u8 value, u8 *addr)
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{
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writeb(value, addr);
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}
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static u8 pci_azx_readb(u8 *addr)
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{
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return readb(addr);
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}
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||||
|
||||
static const struct hda_controller_ops pci_hda_ops = {
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||||
.writel = pci_azx_writel,
|
||||
.readl = pci_azx_readl,
|
||||
.writew = pci_azx_writew,
|
||||
.readw = pci_azx_readw,
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||||
.writeb = pci_azx_writeb,
|
||||
.readb = pci_azx_readb,
|
||||
};
|
||||
|
||||
static int azx_probe(struct pci_dev *pci,
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||||
const struct pci_device_id *pci_id)
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||||
{
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||||
|
|
@ -3473,7 +3496,8 @@ static int azx_probe(struct pci_dev *pci,
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|||
return err;
|
||||
}
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||||
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||||
err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
|
||||
err = azx_create(card, pci, dev, pci_id->driver_data,
|
||||
&pci_hda_ops, &chip);
|
||||
if (err < 0)
|
||||
goto out_free;
|
||||
card->private_data = chip;
|
||||
|
|
|
|||
|
|
@ -285,6 +285,17 @@ struct azx_rb {
|
|||
u32 res[AZX_MAX_CODECS]; /* last read value */
|
||||
};
|
||||
|
||||
/* Functions to read/write to hda registers. */
|
||||
struct hda_controller_ops {
|
||||
/* Register Access */
|
||||
void (*writel)(u32 value, u32 *addr);
|
||||
u32 (*readl)(u32 *addr);
|
||||
void (*writew)(u16 value, u16 *addr);
|
||||
u16 (*readw)(u16 *addr);
|
||||
void (*writeb)(u8 value, u8 *addr);
|
||||
u8 (*readb)(u8 *addr);
|
||||
};
|
||||
|
||||
struct azx_pcm {
|
||||
struct azx *chip;
|
||||
struct snd_pcm *pcm;
|
||||
|
|
@ -307,6 +318,9 @@ struct azx {
|
|||
int capture_index_offset;
|
||||
int num_streams;
|
||||
|
||||
/* Register interaction. */
|
||||
const struct hda_controller_ops *ops;
|
||||
|
||||
/* pci resources */
|
||||
unsigned long addr;
|
||||
void __iomem *remap_addr;
|
||||
|
|
@ -395,4 +409,34 @@ struct azx {
|
|||
#define azx_snoop(chip) true
|
||||
#endif
|
||||
|
||||
/*
|
||||
* macros for easy use
|
||||
*/
|
||||
|
||||
#define azx_writel(chip, reg, value) \
|
||||
((chip)->ops->writel(value, (chip)->remap_addr + ICH6_REG_##reg))
|
||||
#define azx_readl(chip, reg) \
|
||||
((chip)->ops->readl((chip)->remap_addr + ICH6_REG_##reg))
|
||||
#define azx_writew(chip, reg, value) \
|
||||
((chip)->ops->writew(value, (chip)->remap_addr + ICH6_REG_##reg))
|
||||
#define azx_readw(chip, reg) \
|
||||
((chip)->ops->readw((chip)->remap_addr + ICH6_REG_##reg))
|
||||
#define azx_writeb(chip, reg, value) \
|
||||
((chip)->ops->writeb(value, (chip)->remap_addr + ICH6_REG_##reg))
|
||||
#define azx_readb(chip, reg) \
|
||||
((chip)->ops->readb((chip)->remap_addr + ICH6_REG_##reg))
|
||||
|
||||
#define azx_sd_writel(chip, dev, reg, value) \
|
||||
((chip)->ops->writel(value, (dev)->sd_addr + ICH6_REG_##reg))
|
||||
#define azx_sd_readl(chip, dev, reg) \
|
||||
((chip)->ops->readl((dev)->sd_addr + ICH6_REG_##reg))
|
||||
#define azx_sd_writew(chip, dev, reg, value) \
|
||||
((chip)->ops->writew(value, (dev)->sd_addr + ICH6_REG_##reg))
|
||||
#define azx_sd_readw(chip, dev, reg) \
|
||||
((chip)->ops->readw((dev)->sd_addr + ICH6_REG_##reg))
|
||||
#define azx_sd_writeb(chip, dev, reg, value) \
|
||||
((chip)->ops->writeb(value, (dev)->sd_addr + ICH6_REG_##reg))
|
||||
#define azx_sd_readb(chip, dev, reg) \
|
||||
((chip)->ops->readb((dev)->sd_addr + ICH6_REG_##reg))
|
||||
|
||||
#endif /* __SOUND_HDA_PRIV_H */
|
||||
|
|
|
|||
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