clk: meson: gxbb: add cts_amclk
Add the i2s master clock also referred as cts_amclk Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
This commit is contained in:
Jerome Brunet
Родитель
59e85335dd
Коммит
4087bd4b21
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@ -845,6 +845,51 @@ static struct clk_mux gxbb_mali = {
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},
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};
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static struct clk_mux gxbb_cts_amclk_sel = {
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.reg = (void *) HHI_AUD_CLK_CNTL,
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.mask = 0x3,
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.shift = 9,
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/* Default parent unknown (register reset value: 0) */
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.table = (u32[]){ 1, 2, 3 },
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "cts_amclk_sel",
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.ops = &clk_mux_ops,
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.parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
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.num_parents = 3,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct meson_clk_audio_divider gxbb_cts_amclk_div = {
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.div = {
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.reg_off = HHI_AUD_CLK_CNTL,
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.shift = 0,
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.width = 8,
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},
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "cts_amclk_div",
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.ops = &meson_clk_audio_divider_ops,
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.parent_names = (const char *[]){ "cts_amclk_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
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},
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};
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static struct clk_gate gxbb_cts_amclk = {
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.reg = (void *) HHI_AUD_CLK_CNTL,
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.bit_idx = 8,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "cts_amclk",
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.ops = &clk_gate_ops,
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.parent_names = (const char *[]){ "cts_amclk_div" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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/* Everything Else (EE) domain gates */
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static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
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static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
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@ -1045,6 +1090,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
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[CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
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[CLKID_MALI_1] = &gxbb_mali_1.hw,
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[CLKID_MALI] = &gxbb_mali.hw,
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[CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
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[CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
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[CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
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},
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.num = NR_CLKS,
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};
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@ -1158,6 +1206,9 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
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[CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
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[CLKID_MALI_1] = &gxbb_mali_1.hw,
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[CLKID_MALI] = &gxbb_mali.hw,
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[CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
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[CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
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[CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
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},
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.num = NR_CLKS,
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};
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@ -1270,6 +1321,7 @@ static struct clk_gate *const gxbb_clk_gates[] = {
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&gxbb_sar_adc_clk,
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&gxbb_mali_0,
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&gxbb_mali_1,
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&gxbb_cts_amclk,
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};
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static struct clk_mux *const gxbb_clk_muxes[] = {
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@ -1278,6 +1330,7 @@ static struct clk_mux *const gxbb_clk_muxes[] = {
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&gxbb_mali_0_sel,
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&gxbb_mali_1_sel,
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&gxbb_mali,
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&gxbb_cts_amclk_sel,
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};
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static struct clk_divider *const gxbb_clk_dividers[] = {
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@ -1287,6 +1340,10 @@ static struct clk_divider *const gxbb_clk_dividers[] = {
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&gxbb_mali_1_div,
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};
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static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = {
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&gxbb_cts_amclk_div,
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};
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struct clkc_data {
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struct clk_gate *const *clk_gates;
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unsigned int clk_gates_count;
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@ -1298,6 +1355,8 @@ struct clkc_data {
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unsigned int clk_muxes_count;
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struct clk_divider *const *clk_dividers;
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unsigned int clk_dividers_count;
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struct meson_clk_audio_divider *const *clk_audio_dividers;
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unsigned int clk_audio_dividers_count;
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struct meson_clk_cpu *cpu_clk;
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struct clk_hw_onecell_data *hw_onecell_data;
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};
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@ -1313,6 +1372,8 @@ static const struct clkc_data gxbb_clkc_data = {
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.clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes),
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.clk_dividers = gxbb_clk_dividers,
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.clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),
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.clk_audio_dividers = gxbb_audio_dividers,
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.clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),
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.cpu_clk = &gxbb_cpu_clk,
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.hw_onecell_data = &gxbb_hw_onecell_data,
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};
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@ -1328,6 +1389,8 @@ static const struct clkc_data gxl_clkc_data = {
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.clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes),
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.clk_dividers = gxbb_clk_dividers,
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.clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),
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.clk_audio_dividers = gxbb_audio_dividers,
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.clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),
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.cpu_clk = &gxbb_cpu_clk,
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.hw_onecell_data = &gxl_hw_onecell_data,
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};
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@ -1384,6 +1447,10 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
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clkc_data->clk_dividers[i]->reg = clk_base +
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(u64)clkc_data->clk_dividers[i]->reg;
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/* Populate base address for the audio dividers */
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for (i = 0; i < clkc_data->clk_audio_dividers_count; i++)
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clkc_data->clk_audio_dividers[i]->base = clk_base;
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/*
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* register all clks
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*/
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@ -277,8 +277,11 @@
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#define CLKID_MALI_1_DIV 104
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/* CLKID_MALI_1 */
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/* CLKID_MALI */
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#define CLKID_CTS_AMCLK 107
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#define CLKID_CTS_AMCLK_SEL 108
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#define CLKID_CTS_AMCLK_DIV 109
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#define NR_CLKS 107
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#define NR_CLKS 110
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/* include the CLKIDs that have been made part of the stable DT binding */
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#include <dt-bindings/clock/gxbb-clkc.h>
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