ARM: dts: sun4i: Convert to CCU
Convert sun4i-a10.dtsi to new CCU driver. Tested on Gemei G9 tablet. Signed-off-by: Priit Laes <plaes@plaes.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Priit Laes
Maxime Ripard
Родитель
f18698e1c6
Коммит
41193869f2
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@ -44,9 +44,9 @@
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#include "skeleton.dtsi"
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#include <dt-bindings/thermal/thermal.h>
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#include <dt-bindings/clock/sun4i-a10-pll2.h>
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#include <dt-bindings/dma/sun4i-a10.h>
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#include <dt-bindings/clock/sun4i-a10-ccu.h>
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#include <dt-bindings/reset/sun4i-a10-ccu.h>
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/ {
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interrupt-parent = <&intc>;
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@ -64,9 +64,9 @@
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0-hdmi";
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clocks = <&ahb_gates 36>, <&ahb_gates 43>,
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<&ahb_gates 44>, <&de_be0_clk>,
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<&tcon0_ch1_clk>, <&dram_gates 26>;
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clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
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<&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
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<&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
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status = "disabled";
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};
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@ -74,10 +74,11 @@
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
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clocks = <&ahb_gates 36>, <&ahb_gates 43>,
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<&ahb_gates 44>, <&ahb_gates 46>,
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<&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch1_clk>,
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<&dram_gates 25>, <&dram_gates 26>;
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clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
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<&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
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<&ccu CLK_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
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<&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>,
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<&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
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status = "disabled";
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};
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@ -85,9 +86,10 @@
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_fe0-de_be0-lcd0";
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clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&ahb_gates 46>,
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<&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>,
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<&dram_gates 25>, <&dram_gates 26>;
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clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
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<&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>,
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<&ccu CLK_AHB_DE_FE0>, <&ccu CLK_TCON0_CH0>,
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<&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
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status = "disabled";
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};
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@ -95,11 +97,11 @@
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
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clocks = <&ahb_gates 34>, <&ahb_gates 36>,
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<&ahb_gates 44>, <&ahb_gates 46>,
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<&de_be0_clk>, <&de_fe0_clk>,
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<&tcon0_ch1_clk>, <&dram_gates 5>,
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<&dram_gates 25>, <&dram_gates 26>;
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clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
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<&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
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<&ccu CLK_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
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<&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>,
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<&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
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status = "disabled";
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};
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};
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@ -111,7 +113,7 @@
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device_type = "cpu";
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compatible = "arm,cortex-a8";
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reg = <0x0>;
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clocks = <&cpu>;
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clocks = <&ccu CLK_CPU>;
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clock-latency = <244144>; /* 8 32k periods */
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operating-points = <
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/* kHz uV */
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@ -167,507 +169,19 @@
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#size-cells = <1>;
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ranges;
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/*
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* This is a dummy clock, to be used as placeholder on
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* other mux clocks when a specific parent clock is not
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* yet implemented. It should be dropped when the driver
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* is complete.
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*/
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dummy: dummy {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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osc24M: clk@01c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-osc-clk";
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reg = <0x01c20050 0x4>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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osc3M: osc3M_clk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clock-div = <8>;
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clock-mult = <1>;
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clocks = <&osc24M>;
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clock-output-names = "osc3M";
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};
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osc32k: clk@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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pll1: clk@01c20000 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-pll1-clk";
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reg = <0x01c20000 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll1";
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};
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pll2: clk@01c20008 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-pll2-clk";
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reg = <0x01c20008 0x8>;
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clocks = <&osc24M>;
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clock-output-names = "pll2-1x", "pll2-2x",
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"pll2-4x", "pll2-8x";
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};
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pll3: clk@01c20010 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-pll3-clk";
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reg = <0x01c20010 0x4>;
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clocks = <&osc3M>;
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clock-output-names = "pll3";
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};
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pll3x2: pll3x2_clk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <2>;
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clocks = <&pll3>;
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clock-output-names = "pll3-2x";
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};
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pll4: clk@01c20018 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-pll1-clk";
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reg = <0x01c20018 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll4";
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};
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pll5: clk@01c20020 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-pll5-clk";
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reg = <0x01c20020 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll5_ddr", "pll5_other";
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};
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pll6: clk@01c20028 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-pll6-clk";
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reg = <0x01c20028 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll6_sata", "pll6_other", "pll6";
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};
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pll7: clk@01c20030 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-pll3-clk";
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reg = <0x01c20030 0x4>;
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clocks = <&osc3M>;
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clock-output-names = "pll7";
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};
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pll7x2: pll7x2_clk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <2>;
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clocks = <&pll7>;
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clock-output-names = "pll7-2x";
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};
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/* dummy is 200M */
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cpu: cpu@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-cpu-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
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clock-output-names = "cpu";
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};
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axi: axi@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-axi-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&cpu>;
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clock-output-names = "axi";
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};
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axi_gates: clk@01c2005c {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-axi-gates-clk";
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reg = <0x01c2005c 0x4>;
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clocks = <&axi>;
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clock-indices = <0>;
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clock-output-names = "axi_dram";
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};
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ahb: ahb@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-ahb-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&axi>;
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clock-output-names = "ahb";
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};
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ahb_gates: clk@01c20060 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-ahb-gates-clk";
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reg = <0x01c20060 0x8>;
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clocks = <&ahb>;
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clock-indices = <0>, <1>,
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<2>, <3>,
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<4>, <5>, <6>,
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<7>, <8>, <9>,
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<10>, <11>, <12>,
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<13>, <14>, <16>,
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<17>, <18>, <20>,
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<21>, <22>, <23>,
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<24>, <25>, <26>,
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<32>, <33>, <34>,
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<35>, <36>, <37>,
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<40>, <41>, <43>,
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<44>, <45>,
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<46>, <47>,
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<50>, <52>;
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clock-output-names = "ahb_usb0", "ahb_ehci0",
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"ahb_ohci0", "ahb_ehci1",
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"ahb_ohci1", "ahb_ss", "ahb_dma",
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"ahb_bist", "ahb_mmc0", "ahb_mmc1",
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"ahb_mmc2", "ahb_mmc3", "ahb_ms",
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"ahb_nand", "ahb_sdram", "ahb_ace",
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"ahb_emac", "ahb_ts", "ahb_spi0",
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"ahb_spi1", "ahb_spi2", "ahb_spi3",
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"ahb_pata", "ahb_sata", "ahb_gps",
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"ahb_ve", "ahb_tvd", "ahb_tve0",
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"ahb_tve1", "ahb_lcd0", "ahb_lcd1",
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"ahb_csi0", "ahb_csi1", "ahb_hdmi",
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"ahb_de_be0", "ahb_de_be1",
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"ahb_de_fe0", "ahb_de_fe1",
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"ahb_mp", "ahb_mali400";
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};
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apb0: apb0@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-apb0-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&ahb>;
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clock-output-names = "apb0";
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};
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apb0_gates: clk@01c20068 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-apb0-gates-clk";
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reg = <0x01c20068 0x4>;
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clocks = <&apb0>;
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clock-indices = <0>, <1>,
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<2>, <3>,
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<5>, <6>,
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<7>, <10>;
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clock-output-names = "apb0_codec", "apb0_spdif",
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"apb0_ac97", "apb0_iis",
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"apb0_pio", "apb0_ir0",
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"apb0_ir1", "apb0_keypad";
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};
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apb1: clk@01c20058 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-apb1-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
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clock-output-names = "apb1";
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};
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apb1_gates: clk@01c2006c {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-apb1-gates-clk";
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reg = <0x01c2006c 0x4>;
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clocks = <&apb1>;
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clock-indices = <0>, <1>,
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<2>, <4>,
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<5>, <6>,
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<7>, <16>,
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<17>, <18>,
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<19>, <20>,
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<21>, <22>,
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<23>;
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clock-output-names = "apb1_i2c0", "apb1_i2c1",
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"apb1_i2c2", "apb1_can",
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"apb1_scr", "apb1_ps20",
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"apb1_ps21", "apb1_uart0",
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"apb1_uart1", "apb1_uart2",
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"apb1_uart3", "apb1_uart4",
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"apb1_uart5", "apb1_uart6",
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"apb1_uart7";
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};
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nand_clk: clk@01c20080 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c20080 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "nand";
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};
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ms_clk: clk@01c20084 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c20084 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ms";
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};
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mmc0_clk: clk@01c20088 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20088 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc0",
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"mmc0_output",
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"mmc0_sample";
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};
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mmc1_clk: clk@01c2008c {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c2008c 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc1",
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"mmc1_output",
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"mmc1_sample";
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};
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mmc2_clk: clk@01c20090 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20090 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc2",
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"mmc2_output",
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"mmc2_sample";
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};
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mmc3_clk: clk@01c20094 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20094 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc3",
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"mmc3_output",
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"mmc3_sample";
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||||
};
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ts_clk: clk@01c20098 {
|
||||
#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c20098 0x4>;
|
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ts";
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||||
};
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ss_clk: clk@01c2009c {
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#clock-cells = <0>;
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||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c2009c 0x4>;
|
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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||||
clock-output-names = "ss";
|
||||
};
|
||||
|
||||
spi0_clk: clk@01c200a0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
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reg = <0x01c200a0 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "spi0";
|
||||
};
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||||
|
||||
spi1_clk: clk@01c200a4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200a4 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "spi1";
|
||||
};
|
||||
|
||||
spi2_clk: clk@01c200a8 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200a8 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "spi2";
|
||||
};
|
||||
|
||||
pata_clk: clk@01c200ac {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200ac 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "pata";
|
||||
};
|
||||
|
||||
ir0_clk: clk@01c200b0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200b0 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ir0";
|
||||
};
|
||||
|
||||
ir1_clk: clk@01c200b4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200b4 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ir1";
|
||||
};
|
||||
|
||||
spdif_clk: clk@01c200c0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod1-clk";
|
||||
reg = <0x01c200c0 0x4>;
|
||||
clocks = <&pll2 SUN4I_A10_PLL2_8X>,
|
||||
<&pll2 SUN4I_A10_PLL2_4X>,
|
||||
<&pll2 SUN4I_A10_PLL2_2X>,
|
||||
<&pll2 SUN4I_A10_PLL2_1X>;
|
||||
clock-output-names = "spdif";
|
||||
};
|
||||
|
||||
usb_clk: clk@01c200cc {
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
compatible = "allwinner,sun4i-a10-usb-clk";
|
||||
reg = <0x01c200cc 0x4>;
|
||||
clocks = <&pll6 1>;
|
||||
clock-output-names = "usb_ohci0", "usb_ohci1",
|
||||
"usb_phy";
|
||||
};
|
||||
|
||||
spi3_clk: clk@01c200d4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c200d4 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "spi3";
|
||||
};
|
||||
|
||||
dram_gates: clk@01c20100 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-a10-dram-gates-clk";
|
||||
reg = <0x01c20100 0x4>;
|
||||
clocks = <&pll5 0>;
|
||||
clock-indices = <0>,
|
||||
<1>, <2>,
|
||||
<3>,
|
||||
<4>,
|
||||
<5>, <6>,
|
||||
<15>,
|
||||
<24>, <25>,
|
||||
<26>, <27>,
|
||||
<28>, <29>;
|
||||
clock-output-names = "dram_ve",
|
||||
"dram_csi0", "dram_csi1",
|
||||
"dram_ts",
|
||||
"dram_tvd",
|
||||
"dram_tve0", "dram_tve1",
|
||||
"dram_output",
|
||||
"dram_de_fe1", "dram_de_fe0",
|
||||
"dram_de_be0", "dram_de_be1",
|
||||
"dram_de_mp", "dram_ace";
|
||||
};
|
||||
|
||||
de_be0_clk: clk@01c20104 {
|
||||
#clock-cells = <0>;
|
||||
#reset-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-display-clk";
|
||||
reg = <0x01c20104 0x4>;
|
||||
clocks = <&pll3>, <&pll7>, <&pll5 1>;
|
||||
clock-output-names = "de-be0";
|
||||
};
|
||||
|
||||
de_be1_clk: clk@01c20108 {
|
||||
#clock-cells = <0>;
|
||||
#reset-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-display-clk";
|
||||
reg = <0x01c20108 0x4>;
|
||||
clocks = <&pll3>, <&pll7>, <&pll5 1>;
|
||||
clock-output-names = "de-be1";
|
||||
};
|
||||
|
||||
de_fe0_clk: clk@01c2010c {
|
||||
#clock-cells = <0>;
|
||||
#reset-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-display-clk";
|
||||
reg = <0x01c2010c 0x4>;
|
||||
clocks = <&pll3>, <&pll7>, <&pll5 1>;
|
||||
clock-output-names = "de-fe0";
|
||||
};
|
||||
|
||||
de_fe1_clk: clk@01c20110 {
|
||||
#clock-cells = <0>;
|
||||
#reset-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-display-clk";
|
||||
reg = <0x01c20110 0x4>;
|
||||
clocks = <&pll3>, <&pll7>, <&pll5 1>;
|
||||
clock-output-names = "de-fe1";
|
||||
};
|
||||
|
||||
|
||||
tcon0_ch0_clk: clk@01c20118 {
|
||||
#clock-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
|
||||
reg = <0x01c20118 0x4>;
|
||||
clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
|
||||
clock-output-names = "tcon0-ch0-sclk";
|
||||
|
||||
};
|
||||
|
||||
tcon1_ch0_clk: clk@01c2011c {
|
||||
#clock-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
|
||||
reg = <0x01c2011c 0x4>;
|
||||
clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
|
||||
clock-output-names = "tcon1-ch0-sclk";
|
||||
|
||||
};
|
||||
|
||||
tcon0_ch1_clk: clk@01c2012c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
|
||||
reg = <0x01c2012c 0x4>;
|
||||
clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
|
||||
clock-output-names = "tcon0-ch1-sclk";
|
||||
|
||||
};
|
||||
|
||||
tcon1_ch1_clk: clk@01c20130 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
|
||||
reg = <0x01c20130 0x4>;
|
||||
clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
|
||||
clock-output-names = "tcon1-ch1-sclk";
|
||||
|
||||
};
|
||||
|
||||
ve_clk: clk@01c2013c {
|
||||
#clock-cells = <0>;
|
||||
#reset-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-ve-clk";
|
||||
reg = <0x01c2013c 0x4>;
|
||||
clocks = <&pll4>;
|
||||
clock-output-names = "ve";
|
||||
};
|
||||
|
||||
codec_clk: clk@01c20140 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-codec-clk";
|
||||
reg = <0x01c20140 0x4>;
|
||||
clocks = <&pll2 SUN4I_A10_PLL2_1X>;
|
||||
clock-output-names = "codec";
|
||||
};
|
||||
};
|
||||
|
||||
soc@01c00000 {
|
||||
|
|
@ -716,7 +230,7 @@
|
|||
compatible = "allwinner,sun4i-a10-dma";
|
||||
reg = <0x01c02000 0x1000>;
|
||||
interrupts = <27>;
|
||||
clocks = <&ahb_gates 6>;
|
||||
clocks = <&ccu CLK_AHB_DMA>;
|
||||
#dma-cells = <2>;
|
||||
};
|
||||
|
||||
|
|
@ -724,7 +238,7 @@
|
|||
compatible = "allwinner,sun4i-a10-nand";
|
||||
reg = <0x01c03000 0x1000>;
|
||||
interrupts = <37>;
|
||||
clocks = <&ahb_gates 13>, <&nand_clk>;
|
||||
clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
|
||||
clock-names = "ahb", "mod";
|
||||
dmas = <&dma SUN4I_DMA_DEDICATED 3>;
|
||||
dma-names = "rxtx";
|
||||
|
|
@ -737,7 +251,7 @@
|
|||
compatible = "allwinner,sun4i-a10-spi";
|
||||
reg = <0x01c05000 0x1000>;
|
||||
interrupts = <10>;
|
||||
clocks = <&ahb_gates 20>, <&spi0_clk>;
|
||||
clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
|
||||
clock-names = "ahb", "mod";
|
||||
dmas = <&dma SUN4I_DMA_DEDICATED 27>,
|
||||
<&dma SUN4I_DMA_DEDICATED 26>;
|
||||
|
|
@ -751,7 +265,7 @@
|
|||
compatible = "allwinner,sun4i-a10-spi";
|
||||
reg = <0x01c06000 0x1000>;
|
||||
interrupts = <11>;
|
||||
clocks = <&ahb_gates 21>, <&spi1_clk>;
|
||||
clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
|
||||
clock-names = "ahb", "mod";
|
||||
dmas = <&dma SUN4I_DMA_DEDICATED 9>,
|
||||
<&dma SUN4I_DMA_DEDICATED 8>;
|
||||
|
|
@ -765,7 +279,7 @@
|
|||
compatible = "allwinner,sun4i-a10-emac";
|
||||
reg = <0x01c0b000 0x1000>;
|
||||
interrupts = <55>;
|
||||
clocks = <&ahb_gates 17>;
|
||||
clocks = <&ccu CLK_AHB_EMAC>;
|
||||
allwinner,sram = <&emac_sram 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -781,14 +295,8 @@
|
|||
mmc0: mmc@01c0f000 {
|
||||
compatible = "allwinner,sun4i-a10-mmc";
|
||||
reg = <0x01c0f000 0x1000>;
|
||||
clocks = <&ahb_gates 8>,
|
||||
<&mmc0_clk 0>,
|
||||
<&mmc0_clk 1>,
|
||||
<&mmc0_clk 2>;
|
||||
clock-names = "ahb",
|
||||
"mmc",
|
||||
"output",
|
||||
"sample";
|
||||
clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
|
||||
clock-names = "ahb", "mmc";
|
||||
interrupts = <32>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -798,14 +306,8 @@
|
|||
mmc1: mmc@01c10000 {
|
||||
compatible = "allwinner,sun4i-a10-mmc";
|
||||
reg = <0x01c10000 0x1000>;
|
||||
clocks = <&ahb_gates 9>,
|
||||
<&mmc1_clk 0>,
|
||||
<&mmc1_clk 1>,
|
||||
<&mmc1_clk 2>;
|
||||
clock-names = "ahb",
|
||||
"mmc",
|
||||
"output",
|
||||
"sample";
|
||||
clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
|
||||
clock-names = "ahb", "mmc";
|
||||
interrupts = <33>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -815,14 +317,8 @@
|
|||
mmc2: mmc@01c11000 {
|
||||
compatible = "allwinner,sun4i-a10-mmc";
|
||||
reg = <0x01c11000 0x1000>;
|
||||
clocks = <&ahb_gates 10>,
|
||||
<&mmc2_clk 0>,
|
||||
<&mmc2_clk 1>,
|
||||
<&mmc2_clk 2>;
|
||||
clock-names = "ahb",
|
||||
"mmc",
|
||||
"output",
|
||||
"sample";
|
||||
clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
|
||||
clock-names = "ahb", "mmc";
|
||||
interrupts = <34>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -832,14 +328,8 @@
|
|||
mmc3: mmc@01c12000 {
|
||||
compatible = "allwinner,sun4i-a10-mmc";
|
||||
reg = <0x01c12000 0x1000>;
|
||||
clocks = <&ahb_gates 11>,
|
||||
<&mmc3_clk 0>,
|
||||
<&mmc3_clk 1>,
|
||||
<&mmc3_clk 2>;
|
||||
clock-names = "ahb",
|
||||
"mmc",
|
||||
"output",
|
||||
"sample";
|
||||
clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>;
|
||||
clock-names = "ahb", "mmc";
|
||||
interrupts = <35>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -849,7 +339,7 @@
|
|||
usb_otg: usb@01c13000 {
|
||||
compatible = "allwinner,sun4i-a10-musb";
|
||||
reg = <0x01c13000 0x0400>;
|
||||
clocks = <&ahb_gates 0>;
|
||||
clocks = <&ccu CLK_AHB_OTG>;
|
||||
interrupts = <38>;
|
||||
interrupt-names = "mc";
|
||||
phys = <&usbphy 0>;
|
||||
|
|
@ -864,9 +354,11 @@
|
|||
compatible = "allwinner,sun4i-a10-usb-phy";
|
||||
reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
|
||||
reg-names = "phy_ctrl", "pmu1", "pmu2";
|
||||
clocks = <&usb_clk 8>;
|
||||
clocks = <&ccu CLK_USB_PHY>;
|
||||
clock-names = "usb_phy";
|
||||
resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
|
||||
resets = <&ccu RST_USB_PHY0>,
|
||||
<&ccu RST_USB_PHY1>,
|
||||
<&ccu RST_USB_PHY2>;
|
||||
reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -875,7 +367,7 @@
|
|||
compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
|
||||
reg = <0x01c14000 0x100>;
|
||||
interrupts = <39>;
|
||||
clocks = <&ahb_gates 1>;
|
||||
clocks = <&ccu CLK_AHB_EHCI0>;
|
||||
phys = <&usbphy 1>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
|
|
@ -885,7 +377,7 @@
|
|||
compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
|
||||
reg = <0x01c14400 0x100>;
|
||||
interrupts = <64>;
|
||||
clocks = <&usb_clk 6>, <&ahb_gates 2>;
|
||||
clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
|
||||
phys = <&usbphy 1>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
|
|
@ -895,7 +387,7 @@
|
|||
compatible = "allwinner,sun4i-a10-crypto";
|
||||
reg = <0x01c15000 0x1000>;
|
||||
interrupts = <86>;
|
||||
clocks = <&ahb_gates 5>, <&ss_clk>;
|
||||
clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
|
||||
clock-names = "ahb", "mod";
|
||||
};
|
||||
|
||||
|
|
@ -903,7 +395,7 @@
|
|||
compatible = "allwinner,sun4i-a10-spi";
|
||||
reg = <0x01c17000 0x1000>;
|
||||
interrupts = <12>;
|
||||
clocks = <&ahb_gates 22>, <&spi2_clk>;
|
||||
clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
|
||||
clock-names = "ahb", "mod";
|
||||
dmas = <&dma SUN4I_DMA_DEDICATED 29>,
|
||||
<&dma SUN4I_DMA_DEDICATED 28>;
|
||||
|
|
@ -917,7 +409,7 @@
|
|||
compatible = "allwinner,sun4i-a10-ahci";
|
||||
reg = <0x01c18000 0x1000>;
|
||||
interrupts = <56>;
|
||||
clocks = <&pll6 0>, <&ahb_gates 25>;
|
||||
clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -925,7 +417,7 @@
|
|||
compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
|
||||
reg = <0x01c1c000 0x100>;
|
||||
interrupts = <40>;
|
||||
clocks = <&ahb_gates 3>;
|
||||
clocks = <&ccu CLK_AHB_EHCI1>;
|
||||
phys = <&usbphy 2>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
|
|
@ -935,7 +427,7 @@
|
|||
compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
|
||||
reg = <0x01c1c400 0x100>;
|
||||
interrupts = <65>;
|
||||
clocks = <&usb_clk 7>, <&ahb_gates 4>;
|
||||
clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
|
||||
phys = <&usbphy 2>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
|
|
@ -945,7 +437,7 @@
|
|||
compatible = "allwinner,sun4i-a10-spi";
|
||||
reg = <0x01c1f000 0x1000>;
|
||||
interrupts = <50>;
|
||||
clocks = <&ahb_gates 23>, <&spi3_clk>;
|
||||
clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
|
||||
clock-names = "ahb", "mod";
|
||||
dmas = <&dma SUN4I_DMA_DEDICATED 31>,
|
||||
<&dma SUN4I_DMA_DEDICATED 30>;
|
||||
|
|
@ -955,6 +447,15 @@
|
|||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
ccu: clock@01c20000 {
|
||||
compatible = "allwinner,sun4i-a10-ccu";
|
||||
reg = <0x01c20000 0x400>;
|
||||
clocks = <&osc24M>, <&osc32k>;
|
||||
clock-names = "hosc", "losc";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@01c20400 {
|
||||
compatible = "allwinner,sun4i-a10-ic";
|
||||
reg = <0x01c20400 0x400>;
|
||||
|
|
@ -966,7 +467,7 @@
|
|||
compatible = "allwinner,sun4i-a10-pinctrl";
|
||||
reg = <0x01c20800 0x400>;
|
||||
interrupts = <28>;
|
||||
clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
|
||||
clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
|
||||
clock-names = "apb", "hosc", "losc";
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
|
|
@ -1143,7 +644,7 @@
|
|||
compatible = "allwinner,sun4i-a10-spdif";
|
||||
reg = <0x01c21000 0x400>;
|
||||
interrupts = <13>;
|
||||
clocks = <&apb0_gates 1>, <&spdif_clk>;
|
||||
clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
|
||||
clock-names = "apb", "spdif";
|
||||
dmas = <&dma SUN4I_DMA_NORMAL 2>,
|
||||
<&dma SUN4I_DMA_NORMAL 2>;
|
||||
|
|
@ -1153,7 +654,7 @@
|
|||
|
||||
ir0: ir@01c21800 {
|
||||
compatible = "allwinner,sun4i-a10-ir";
|
||||
clocks = <&apb0_gates 6>, <&ir0_clk>;
|
||||
clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
|
||||
clock-names = "apb", "ir";
|
||||
interrupts = <5>;
|
||||
reg = <0x01c21800 0x40>;
|
||||
|
|
@ -1162,7 +663,7 @@
|
|||
|
||||
ir1: ir@01c21c00 {
|
||||
compatible = "allwinner,sun4i-a10-ir";
|
||||
clocks = <&apb0_gates 7>, <&ir1_clk>;
|
||||
clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
|
||||
clock-names = "apb", "ir";
|
||||
interrupts = <6>;
|
||||
reg = <0x01c21c00 0x40>;
|
||||
|
|
@ -1181,7 +682,7 @@
|
|||
compatible = "allwinner,sun4i-a10-codec";
|
||||
reg = <0x01c22c00 0x40>;
|
||||
interrupts = <30>;
|
||||
clocks = <&apb0_gates 0>, <&codec_clk>;
|
||||
clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
|
||||
clock-names = "apb", "codec";
|
||||
dmas = <&dma SUN4I_DMA_NORMAL 19>,
|
||||
<&dma SUN4I_DMA_NORMAL 19>;
|
||||
|
|
@ -1207,7 +708,7 @@
|
|||
interrupts = <1>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 16>;
|
||||
clocks = <&ccu CLK_APB1_UART0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1217,7 +718,7 @@
|
|||
interrupts = <2>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 17>;
|
||||
clocks = <&ccu CLK_APB1_UART1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1227,7 +728,7 @@
|
|||
interrupts = <3>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 18>;
|
||||
clocks = <&ccu CLK_APB1_UART2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1237,7 +738,7 @@
|
|||
interrupts = <4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 19>;
|
||||
clocks = <&ccu CLK_APB1_UART3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1247,7 +748,7 @@
|
|||
interrupts = <17>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 20>;
|
||||
clocks = <&ccu CLK_APB1_UART4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1257,7 +758,7 @@
|
|||
interrupts = <18>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 21>;
|
||||
clocks = <&ccu CLK_APB1_UART5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1267,7 +768,7 @@
|
|||
interrupts = <19>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 22>;
|
||||
clocks = <&ccu CLK_APB1_UART6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1277,7 +778,7 @@
|
|||
interrupts = <20>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 23>;
|
||||
clocks = <&ccu CLK_APB1_UART7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1285,7 +786,7 @@
|
|||
compatible = "allwinner,sun4i-a10-ps2";
|
||||
reg = <0x01c2a000 0x400>;
|
||||
interrupts = <62>;
|
||||
clocks = <&apb1_gates 6>;
|
||||
clocks = <&ccu CLK_APB1_PS20>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1293,7 +794,7 @@
|
|||
compatible = "allwinner,sun4i-a10-ps2";
|
||||
reg = <0x01c2a400 0x400>;
|
||||
interrupts = <63>;
|
||||
clocks = <&apb1_gates 7>;
|
||||
clocks = <&ccu CLK_APB1_PS21>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1301,7 +802,7 @@
|
|||
compatible = "allwinner,sun4i-a10-i2c";
|
||||
reg = <0x01c2ac00 0x400>;
|
||||
interrupts = <7>;
|
||||
clocks = <&apb1_gates 0>;
|
||||
clocks = <&ccu CLK_APB1_I2C0>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -1311,7 +812,7 @@
|
|||
compatible = "allwinner,sun4i-a10-i2c";
|
||||
reg = <0x01c2b000 0x400>;
|
||||
interrupts = <8>;
|
||||
clocks = <&apb1_gates 1>;
|
||||
clocks = <&ccu CLK_APB1_I2C1>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -1321,7 +822,7 @@
|
|||
compatible = "allwinner,sun4i-a10-i2c";
|
||||
reg = <0x01c2b400 0x400>;
|
||||
interrupts = <9>;
|
||||
clocks = <&apb1_gates 2>;
|
||||
clocks = <&ccu CLK_APB1_I2C2>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -1331,7 +832,7 @@
|
|||
compatible = "allwinner,sun4i-a10-can";
|
||||
reg = <0x01c2bc00 0x400>;
|
||||
interrupts = <26>;
|
||||
clocks = <&apb1_gates 4>;
|
||||
clocks = <&ccu CLK_APB1_CAN>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
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