Merge tag 'amd-drm-fixes-6.0-2022-09-30-1' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-6.0-2022-09-30-1: amdgpu: - VCN 4.x fixes - RLC fixes for GC 11.x Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220930210454.542719-1-alexander.deucher@amd.com
This commit is contained in:
Daniel Vetter
Коммит
414208e489
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@ -304,6 +304,10 @@ struct amdgpu_gfx {
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uint32_t rlc_srlg_feature_version;
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uint32_t rlc_srls_fw_version;
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uint32_t rlc_srls_feature_version;
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uint32_t rlcp_ucode_version;
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uint32_t rlcp_ucode_feature_version;
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uint32_t rlcv_ucode_version;
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uint32_t rlcv_ucode_feature_version;
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uint32_t mec_feature_version;
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uint32_t mec2_feature_version;
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bool mec_fw_write_wait;
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@ -272,3 +272,267 @@ void amdgpu_gfx_rlc_fini(struct amdgpu_device *adev)
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&adev->gfx.rlc.cp_table_gpu_addr,
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(void **)&adev->gfx.rlc.cp_table_ptr);
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}
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static int amdgpu_gfx_rlc_init_microcode_v2_0(struct amdgpu_device *adev)
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{
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const struct common_firmware_header *common_hdr;
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const struct rlc_firmware_header_v2_0 *rlc_hdr;
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struct amdgpu_firmware_info *info;
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unsigned int *tmp;
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unsigned int i;
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rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
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adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
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adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
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adev->gfx.rlc.save_and_restore_offset =
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le32_to_cpu(rlc_hdr->save_and_restore_offset);
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adev->gfx.rlc.clear_state_descriptor_offset =
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le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
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adev->gfx.rlc.avail_scratch_ram_locations =
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le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
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adev->gfx.rlc.reg_restore_list_size =
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le32_to_cpu(rlc_hdr->reg_restore_list_size);
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adev->gfx.rlc.reg_list_format_start =
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le32_to_cpu(rlc_hdr->reg_list_format_start);
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adev->gfx.rlc.reg_list_format_separate_start =
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le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
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adev->gfx.rlc.starting_offsets_start =
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le32_to_cpu(rlc_hdr->starting_offsets_start);
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adev->gfx.rlc.reg_list_format_size_bytes =
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le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
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adev->gfx.rlc.reg_list_size_bytes =
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le32_to_cpu(rlc_hdr->reg_list_size_bytes);
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adev->gfx.rlc.register_list_format =
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kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
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adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
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if (!adev->gfx.rlc.register_list_format) {
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dev_err(adev->dev, "failed to allocate memory for rlc register_list_format\n");
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return -ENOMEM;
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}
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tmp = (unsigned int *)((uintptr_t)rlc_hdr +
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le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
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for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
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adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
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adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
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tmp = (unsigned int *)((uintptr_t)rlc_hdr +
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le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
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for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
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adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
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info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
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info->fw = adev->gfx.rlc_fw;
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if (info->fw) {
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common_hdr = (const struct common_firmware_header *)info->fw->data;
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adev->firmware.fw_size +=
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ALIGN(le32_to_cpu(common_hdr->ucode_size_bytes), PAGE_SIZE);
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}
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}
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return 0;
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}
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static void amdgpu_gfx_rlc_init_microcode_v2_1(struct amdgpu_device *adev)
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{
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const struct rlc_firmware_header_v2_1 *rlc_hdr;
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struct amdgpu_firmware_info *info;
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rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
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adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
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adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
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adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
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adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
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adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
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adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
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adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
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adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
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adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
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adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
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adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
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adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
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adev->gfx.rlc.reg_list_format_direct_reg_list_length =
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le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
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if (adev->gfx.rlc.save_restore_list_gpm_size_bytes) {
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
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info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
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info->fw = adev->gfx.rlc_fw;
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adev->firmware.fw_size +=
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ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
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}
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if (adev->gfx.rlc.save_restore_list_srm_size_bytes) {
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
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info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
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info->fw = adev->gfx.rlc_fw;
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adev->firmware.fw_size +=
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ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
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}
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}
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}
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static void amdgpu_gfx_rlc_init_microcode_v2_2(struct amdgpu_device *adev)
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{
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const struct rlc_firmware_header_v2_2 *rlc_hdr;
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struct amdgpu_firmware_info *info;
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rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
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adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
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adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
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adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
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adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
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if (adev->gfx.rlc.rlc_iram_ucode_size_bytes) {
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
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info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
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info->fw = adev->gfx.rlc_fw;
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adev->firmware.fw_size +=
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ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
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}
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if (adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
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info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
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info->fw = adev->gfx.rlc_fw;
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adev->firmware.fw_size +=
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ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
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}
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}
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}
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static void amdgpu_gfx_rlc_init_microcode_v2_3(struct amdgpu_device *adev)
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{
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const struct rlc_firmware_header_v2_3 *rlc_hdr;
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struct amdgpu_firmware_info *info;
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rlc_hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data;
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adev->gfx.rlcp_ucode_version = le32_to_cpu(rlc_hdr->rlcp_ucode_version);
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adev->gfx.rlcp_ucode_feature_version = le32_to_cpu(rlc_hdr->rlcp_ucode_feature_version);
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adev->gfx.rlc.rlcp_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlcp_ucode_size_bytes);
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adev->gfx.rlc.rlcp_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcp_ucode_offset_bytes);
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adev->gfx.rlcv_ucode_version = le32_to_cpu(rlc_hdr->rlcv_ucode_version);
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adev->gfx.rlcv_ucode_feature_version = le32_to_cpu(rlc_hdr->rlcv_ucode_feature_version);
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adev->gfx.rlc.rlcv_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlcv_ucode_size_bytes);
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adev->gfx.rlc.rlcv_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcv_ucode_offset_bytes);
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
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if (adev->gfx.rlc.rlcp_ucode_size_bytes) {
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_P];
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info->ucode_id = AMDGPU_UCODE_ID_RLC_P;
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info->fw = adev->gfx.rlc_fw;
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adev->firmware.fw_size +=
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ALIGN(adev->gfx.rlc.rlcp_ucode_size_bytes, PAGE_SIZE);
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}
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if (adev->gfx.rlc.rlcv_ucode_size_bytes) {
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_V];
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info->ucode_id = AMDGPU_UCODE_ID_RLC_V;
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info->fw = adev->gfx.rlc_fw;
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adev->firmware.fw_size +=
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ALIGN(adev->gfx.rlc.rlcv_ucode_size_bytes, PAGE_SIZE);
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}
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}
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}
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static void amdgpu_gfx_rlc_init_microcode_v2_4(struct amdgpu_device *adev)
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{
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const struct rlc_firmware_header_v2_4 *rlc_hdr;
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struct amdgpu_firmware_info *info;
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rlc_hdr = (const struct rlc_firmware_header_v2_4 *)adev->gfx.rlc_fw->data;
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adev->gfx.rlc.global_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->global_tap_delays_ucode_size_bytes);
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adev->gfx.rlc.global_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->global_tap_delays_ucode_offset_bytes);
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adev->gfx.rlc.se0_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_size_bytes);
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adev->gfx.rlc.se0_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_offset_bytes);
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adev->gfx.rlc.se1_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_size_bytes);
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adev->gfx.rlc.se1_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_offset_bytes);
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adev->gfx.rlc.se2_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_size_bytes);
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adev->gfx.rlc.se2_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_offset_bytes);
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adev->gfx.rlc.se3_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_size_bytes);
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adev->gfx.rlc.se3_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_offset_bytes);
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
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if (adev->gfx.rlc.global_tap_delays_ucode_size_bytes) {
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS];
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info->ucode_id = AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS;
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info->fw = adev->gfx.rlc_fw;
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adev->firmware.fw_size +=
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ALIGN(adev->gfx.rlc.global_tap_delays_ucode_size_bytes, PAGE_SIZE);
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}
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if (adev->gfx.rlc.se0_tap_delays_ucode_size_bytes) {
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE0_TAP_DELAYS];
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info->ucode_id = AMDGPU_UCODE_ID_SE0_TAP_DELAYS;
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info->fw = adev->gfx.rlc_fw;
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adev->firmware.fw_size +=
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ALIGN(adev->gfx.rlc.se0_tap_delays_ucode_size_bytes, PAGE_SIZE);
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}
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if (adev->gfx.rlc.se1_tap_delays_ucode_size_bytes) {
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE1_TAP_DELAYS];
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info->ucode_id = AMDGPU_UCODE_ID_SE1_TAP_DELAYS;
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info->fw = adev->gfx.rlc_fw;
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adev->firmware.fw_size +=
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ALIGN(adev->gfx.rlc.se1_tap_delays_ucode_size_bytes, PAGE_SIZE);
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}
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if (adev->gfx.rlc.se2_tap_delays_ucode_size_bytes) {
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE2_TAP_DELAYS];
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info->ucode_id = AMDGPU_UCODE_ID_SE2_TAP_DELAYS;
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info->fw = adev->gfx.rlc_fw;
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adev->firmware.fw_size +=
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ALIGN(adev->gfx.rlc.se2_tap_delays_ucode_size_bytes, PAGE_SIZE);
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}
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if (adev->gfx.rlc.se3_tap_delays_ucode_size_bytes) {
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE3_TAP_DELAYS];
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info->ucode_id = AMDGPU_UCODE_ID_SE3_TAP_DELAYS;
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info->fw = adev->gfx.rlc_fw;
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adev->firmware.fw_size +=
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ALIGN(adev->gfx.rlc.se3_tap_delays_ucode_size_bytes, PAGE_SIZE);
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}
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}
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}
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int amdgpu_gfx_rlc_init_microcode(struct amdgpu_device *adev,
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uint16_t version_major,
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uint16_t version_minor)
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{
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int err;
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if (version_major < 2) {
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/* only support rlc_hdr v2.x and onwards */
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dev_err(adev->dev, "unsupported rlc fw hdr\n");
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return -EINVAL;
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}
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/* is_rlc_v2_1 is still used in APU code path */
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if (version_major == 2 && version_minor == 1)
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adev->gfx.rlc.is_rlc_v2_1 = true;
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if (version_minor >= 0) {
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err = amdgpu_gfx_rlc_init_microcode_v2_0(adev);
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if (err) {
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dev_err(adev->dev, "fail to init rlc v2_0 microcode\n");
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return err;
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}
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}
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if (version_minor >= 1)
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amdgpu_gfx_rlc_init_microcode_v2_1(adev);
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if (version_minor >= 2)
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amdgpu_gfx_rlc_init_microcode_v2_2(adev);
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if (version_minor == 3)
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amdgpu_gfx_rlc_init_microcode_v2_3(adev);
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if (version_minor == 4)
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amdgpu_gfx_rlc_init_microcode_v2_4(adev);
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return 0;
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}
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@ -267,5 +267,7 @@ int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev);
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int amdgpu_gfx_rlc_init_cpt(struct amdgpu_device *adev);
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void amdgpu_gfx_rlc_setup_cp_table(struct amdgpu_device *adev);
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void amdgpu_gfx_rlc_fini(struct amdgpu_device *adev);
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int amdgpu_gfx_rlc_init_microcode(struct amdgpu_device *adev,
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uint16_t version_major,
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uint16_t version_minor);
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#endif
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@ -260,8 +260,12 @@ struct rlc_firmware_header_v2_2 {
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/* version_major=2, version_minor=3 */
|
||||
struct rlc_firmware_header_v2_3 {
|
||||
struct rlc_firmware_header_v2_2 v2_2;
|
||||
uint32_t rlcp_ucode_version;
|
||||
uint32_t rlcp_ucode_feature_version;
|
||||
uint32_t rlcp_ucode_size_bytes;
|
||||
uint32_t rlcp_ucode_offset_bytes;
|
||||
uint32_t rlcv_ucode_version;
|
||||
uint32_t rlcv_ucode_feature_version;
|
||||
uint32_t rlcv_ucode_size_bytes;
|
||||
uint32_t rlcv_ucode_offset_bytes;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -191,7 +191,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
|
|||
fw_name = FIRMWARE_VCN4_0_2;
|
||||
if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
|
||||
(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
|
||||
adev->vcn.indirect_sram = false;
|
||||
adev->vcn.indirect_sram = true;
|
||||
break;
|
||||
case IP_VERSION(4, 0, 4):
|
||||
fw_name = FIRMWARE_VCN4_0_4;
|
||||
|
|
|
|||
|
|
@ -474,49 +474,6 @@ static void gfx_v11_0_free_microcode(struct amdgpu_device *adev)
|
|||
kfree(adev->gfx.rlc.register_list_format);
|
||||
}
|
||||
|
||||
static void gfx_v11_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
|
||||
{
|
||||
const struct rlc_firmware_header_v2_1 *rlc_hdr;
|
||||
|
||||
rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
|
||||
adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
|
||||
adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
|
||||
adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
|
||||
adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
|
||||
adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
|
||||
adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
|
||||
adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
|
||||
adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
|
||||
adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
|
||||
adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
|
||||
adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
|
||||
adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
|
||||
adev->gfx.rlc.reg_list_format_direct_reg_list_length =
|
||||
le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
|
||||
}
|
||||
|
||||
static void gfx_v11_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
|
||||
{
|
||||
const struct rlc_firmware_header_v2_2 *rlc_hdr;
|
||||
|
||||
rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
|
||||
adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
|
||||
adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
|
||||
adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
|
||||
adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
|
||||
}
|
||||
|
||||
static void gfx_v11_0_init_rlcp_rlcv_microcode(struct amdgpu_device *adev)
|
||||
{
|
||||
const struct rlc_firmware_header_v2_3 *rlc_hdr;
|
||||
|
||||
rlc_hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data;
|
||||
adev->gfx.rlc.rlcp_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlcp_ucode_size_bytes);
|
||||
adev->gfx.rlc.rlcp_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcp_ucode_offset_bytes);
|
||||
adev->gfx.rlc.rlcv_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlcv_ucode_size_bytes);
|
||||
adev->gfx.rlc.rlcv_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcv_ucode_offset_bytes);
|
||||
}
|
||||
|
||||
static int gfx_v11_0_init_microcode(struct amdgpu_device *adev)
|
||||
{
|
||||
char fw_name[40];
|
||||
|
|
@ -527,8 +484,6 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev)
|
|||
const struct gfx_firmware_header_v1_0 *cp_hdr;
|
||||
const struct gfx_firmware_header_v2_0 *cp_hdr_v2_0;
|
||||
const struct rlc_firmware_header_v2_0 *rlc_hdr;
|
||||
unsigned int *tmp = NULL;
|
||||
unsigned int i = 0;
|
||||
uint16_t version_major;
|
||||
uint16_t version_minor;
|
||||
|
||||
|
|
@ -583,58 +538,14 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev)
|
|||
if (err)
|
||||
goto out;
|
||||
err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
|
||||
if (err)
|
||||
goto out;
|
||||
rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
|
||||
version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
|
||||
version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
|
||||
|
||||
adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
|
||||
adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
|
||||
adev->gfx.rlc.save_and_restore_offset =
|
||||
le32_to_cpu(rlc_hdr->save_and_restore_offset);
|
||||
adev->gfx.rlc.clear_state_descriptor_offset =
|
||||
le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
|
||||
adev->gfx.rlc.avail_scratch_ram_locations =
|
||||
le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
|
||||
adev->gfx.rlc.reg_restore_list_size =
|
||||
le32_to_cpu(rlc_hdr->reg_restore_list_size);
|
||||
adev->gfx.rlc.reg_list_format_start =
|
||||
le32_to_cpu(rlc_hdr->reg_list_format_start);
|
||||
adev->gfx.rlc.reg_list_format_separate_start =
|
||||
le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
|
||||
adev->gfx.rlc.starting_offsets_start =
|
||||
le32_to_cpu(rlc_hdr->starting_offsets_start);
|
||||
adev->gfx.rlc.reg_list_format_size_bytes =
|
||||
le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
|
||||
adev->gfx.rlc.reg_list_size_bytes =
|
||||
le32_to_cpu(rlc_hdr->reg_list_size_bytes);
|
||||
adev->gfx.rlc.register_list_format =
|
||||
kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
|
||||
adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
|
||||
if (!adev->gfx.rlc.register_list_format) {
|
||||
err = -ENOMEM;
|
||||
err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
|
||||
if (err)
|
||||
goto out;
|
||||
}
|
||||
|
||||
tmp = (unsigned int *)((uintptr_t)rlc_hdr +
|
||||
le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
|
||||
for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
|
||||
adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
|
||||
|
||||
adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
|
||||
|
||||
tmp = (unsigned int *)((uintptr_t)rlc_hdr +
|
||||
le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
|
||||
for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
|
||||
adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
|
||||
|
||||
if (version_major == 2) {
|
||||
if (version_minor >= 1)
|
||||
gfx_v11_0_init_rlc_ext_microcode(adev);
|
||||
if (version_minor >= 2)
|
||||
gfx_v11_0_init_rlc_iram_dram_microcode(adev);
|
||||
if (version_minor == 3)
|
||||
gfx_v11_0_init_rlcp_rlcv_microcode(adev);
|
||||
}
|
||||
}
|
||||
|
||||
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix);
|
||||
|
|
@ -769,60 +680,6 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev)
|
|||
adev->firmware.fw_size +=
|
||||
ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
|
||||
}
|
||||
|
||||
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
|
||||
info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
|
||||
info->fw = adev->gfx.rlc_fw;
|
||||
if (info->fw) {
|
||||
header = (const struct common_firmware_header *)info->fw->data;
|
||||
adev->firmware.fw_size +=
|
||||
ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
|
||||
}
|
||||
if (adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
|
||||
adev->gfx.rlc.save_restore_list_srm_size_bytes) {
|
||||
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
|
||||
info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
|
||||
info->fw = adev->gfx.rlc_fw;
|
||||
adev->firmware.fw_size +=
|
||||
ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
|
||||
|
||||
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
|
||||
info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
|
||||
info->fw = adev->gfx.rlc_fw;
|
||||
adev->firmware.fw_size +=
|
||||
ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
|
||||
}
|
||||
|
||||
if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
|
||||
adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
|
||||
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
|
||||
info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
|
||||
info->fw = adev->gfx.rlc_fw;
|
||||
adev->firmware.fw_size +=
|
||||
ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
|
||||
|
||||
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
|
||||
info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
|
||||
info->fw = adev->gfx.rlc_fw;
|
||||
adev->firmware.fw_size +=
|
||||
ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
|
||||
}
|
||||
|
||||
if (adev->gfx.rlc.rlcp_ucode_size_bytes) {
|
||||
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_P];
|
||||
info->ucode_id = AMDGPU_UCODE_ID_RLC_P;
|
||||
info->fw = adev->gfx.rlc_fw;
|
||||
adev->firmware.fw_size +=
|
||||
ALIGN(adev->gfx.rlc.rlcp_ucode_size_bytes, PAGE_SIZE);
|
||||
}
|
||||
|
||||
if (adev->gfx.rlc.rlcv_ucode_size_bytes) {
|
||||
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_V];
|
||||
info->ucode_id = AMDGPU_UCODE_ID_RLC_V;
|
||||
info->fw = adev->gfx.rlc_fw;
|
||||
adev->firmware.fw_size +=
|
||||
ALIGN(adev->gfx.rlc.rlcv_ucode_size_bytes, PAGE_SIZE);
|
||||
}
|
||||
}
|
||||
|
||||
out:
|
||||
|
|
|
|||
|
|
@ -625,6 +625,7 @@ static int soc21_common_early_init(void *handle)
|
|||
AMD_CG_SUPPORT_JPEG_MGCG;
|
||||
adev->pg_flags =
|
||||
AMD_PG_SUPPORT_GFX_PG |
|
||||
AMD_PG_SUPPORT_VCN_DPG |
|
||||
AMD_PG_SUPPORT_JPEG;
|
||||
adev->external_rev_id = adev->rev_id + 0x1;
|
||||
break;
|
||||
|
|
|
|||
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