viafb: rework color setting
This is a rewritten version of viafb_setcolreg. The hardware register writes were split up and moved to hw.c where they belong as this is really low level stuff. It was made dual fb aware. Furthermore viafb_setcmap was removed as the problem with 8bpp originated from a bug in writing multiple color registers at once. The removal of viafb_setcmap might introduce a small performance regression but its certainly better to receive the correct result a bit slower than a garbled picture fast. It should give us a working 8bpp mode and is more extensible than the old hardcoded code. No other regressions are expected but as the hardware might be a bit picky it might cause some regressions in 8bpp mode on some hardware although I doubt that. Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de> Cc: Joseph Chan <JosephChan@via.com.tw> Cc: Scott Fang <ScottFang@viatech.com.cn> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Florian Tobias Schandinat
Linus Torvalds
Родитель
dbb7884be7
Коммит
415559fbf2
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@ -691,7 +691,7 @@ void viafb_set_primary_color_depth(u8 depth)
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DEBUG_MSG(KERN_DEBUG "viafb_set_primary_color_depth(%d)\n", depth);
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switch (depth) {
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case 6:
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case 8:
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value = 0x00;
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break;
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case 16:
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@ -715,7 +715,7 @@ void viafb_set_secondary_color_depth(u8 depth)
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DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_color_depth(%d)\n", depth);
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switch (depth) {
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case 6:
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case 8:
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value = 0x00;
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break;
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case 16:
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@ -733,6 +733,27 @@ void viafb_set_secondary_color_depth(u8 depth)
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viafb_write_reg_mask(0x67, VIACR, value, 0xC0);
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}
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static void set_color_register(u8 index, u8 red, u8 green, u8 blue)
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{
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outb(0xFF, 0x3C6); /* bit mask of palette */
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outb(index, 0x3C8);
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outb(red, 0x3C9);
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outb(green, 0x3C9);
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outb(blue, 0x3C9);
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}
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void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue)
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{
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viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01);
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set_color_register(index, red, green, blue);
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}
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void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue)
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{
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viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01);
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set_color_register(index, red, green, blue);
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}
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void viafb_set_output_path(int device, int set_iga, int output_interface)
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{
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switch (device) {
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@ -2210,8 +2231,7 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
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outb(VPIT.SR[i - 1], VIASR + 1);
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}
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viafb_write_reg_mask(0x15, VIASR, viafbinfo->fix.visual
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== FB_VISUAL_PSEUDOCOLOR ? 0x22 : 0xA2, 0xA2);
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viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);
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viafb_set_iga_path();
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/* Write CRTC */
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@ -914,6 +914,8 @@ void viafb_set_primary_address(u32 addr);
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void viafb_set_secondary_address(u32 addr);
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void viafb_set_primary_pitch(u32 pitch);
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void viafb_set_secondary_pitch(u32 pitch);
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void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue);
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void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue);
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void viafb_get_fb_info(unsigned int *fb_base, unsigned int *fb_len);
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#endif /* __HW_H__ */
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@ -76,9 +76,9 @@ static void viafb_fill_var_color_info(struct fb_var_screeninfo *var, u8 depth)
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var->red.offset = 0;
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var->green.offset = 0;
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var->blue.offset = 0;
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var->red.length = 6;
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var->green.length = 6;
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var->blue.length = 6;
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var->red.length = 8;
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var->green.length = 8;
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var->blue.length = 8;
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break;
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case 16:
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var->bits_per_pixel = 16;
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@ -255,220 +255,34 @@ static int viafb_set_par(struct fb_info *info)
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static int viafb_setcolreg(unsigned regno, unsigned red, unsigned green,
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unsigned blue, unsigned transp, struct fb_info *info)
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{
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u8 sr1a, sr1b, cr67, cr6a, rev = 0, shift = 10;
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unsigned cmap_entries = (info->var.bits_per_pixel == 8) ? 256 : 16;
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DEBUG_MSG(KERN_INFO "viafb_setcolreg!\n");
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if (regno >= cmap_entries)
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return 1;
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if (UNICHROME_CLE266 == viaparinfo->chip_info->gfx_chip_name) {
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/*
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* Read PCI bus 0,dev 0,function 0,index 0xF6 to get chip rev.
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*/
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outl(0x80000000 | (0xf6 & ~3), (unsigned long)0xCF8);
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rev = (inl((unsigned long)0xCFC) >> ((0xf6 & 3) * 8)) & 0xff;
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}
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switch (info->var.bits_per_pixel) {
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case 8:
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outb(0x1A, 0x3C4);
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sr1a = inb(0x3C5);
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outb(0x1B, 0x3C4);
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sr1b = inb(0x3C5);
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outb(0x67, 0x3D4);
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cr67 = inb(0x3D5);
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outb(0x6A, 0x3D4);
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cr6a = inb(0x3D5);
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struct viafb_par *viapar = info->par;
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u32 r, g, b;
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/* Map the 3C6/7/8/9 to the IGA2 */
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outb(0x1A, 0x3C4);
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outb(sr1a | 0x01, 0x3C5);
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/* Second Display Engine colck always on */
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outb(0x1B, 0x3C4);
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outb(sr1b | 0x80, 0x3C5);
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/* Second Display Color Depth 8 */
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outb(0x67, 0x3D4);
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outb(cr67 & 0x3F, 0x3D5);
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outb(0x6A, 0x3D4);
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/* Second Display Channel Reset CR6A[6]) */
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outb(cr6a & 0xBF, 0x3D5);
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/* Second Display Channel Enable CR6A[7] */
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outb(cr6a | 0x80, 0x3D5);
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/* Second Display Channel stop reset) */
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outb(cr6a | 0x40, 0x3D5);
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if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) {
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if (regno > 255)
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return -EINVAL;
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/* Bit mask of palette */
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outb(0xFF, 0x3c6);
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/* Write one register of IGA2 */
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outb(regno, 0x3C8);
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if (UNICHROME_CLE266 == viaparinfo->chip_info->gfx_chip_name &&
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rev >= 15) {
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shift = 8;
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viafb_write_reg_mask(CR6A, VIACR, BIT5, BIT5);
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viafb_write_reg_mask(SR15, VIASR, BIT7, BIT7);
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} else {
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shift = 10;
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viafb_write_reg_mask(CR6A, VIACR, 0, BIT5);
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viafb_write_reg_mask(SR15, VIASR, 0, BIT7);
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}
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outb(red >> shift, 0x3C9);
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outb(green >> shift, 0x3C9);
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outb(blue >> shift, 0x3C9);
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if (!viafb_dual_fb || viapar->iga_path == IGA1)
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viafb_set_primary_color_register(regno, red >> 8,
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green >> 8, blue >> 8);
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/* Map the 3C6/7/8/9 to the IGA1 */
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outb(0x1A, 0x3C4);
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outb(sr1a & 0xFE, 0x3C5);
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/* Bit mask of palette */
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outb(0xFF, 0x3c6);
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/* Write one register of IGA1 */
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outb(regno, 0x3C8);
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outb(red >> shift, 0x3C9);
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outb(green >> shift, 0x3C9);
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outb(blue >> shift, 0x3C9);
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if (!viafb_dual_fb || viapar->iga_path == IGA2)
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viafb_set_secondary_color_register(regno, red >> 8,
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green >> 8, blue >> 8);
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} else {
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if (regno > 15)
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return -EINVAL;
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outb(0x1A, 0x3C4);
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outb(sr1a, 0x3C5);
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outb(0x1B, 0x3C4);
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outb(sr1b, 0x3C5);
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outb(0x67, 0x3D4);
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outb(cr67, 0x3D5);
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outb(0x6A, 0x3D4);
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outb(cr6a, 0x3D5);
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break;
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case 16:
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((u32 *) info->pseudo_palette)[regno] = (red & 0xF800) |
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((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
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break;
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case 32:
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((u32 *) info->pseudo_palette)[regno] =
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((transp & 0xFF00) << 16) |
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((red & 0xFF00) << 8) |
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((green & 0xFF00)) | ((blue & 0xFF00) >> 8);
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break;
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r = (red >> (16 - info->var.red.length))
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<< info->var.red.offset;
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b = (blue >> (16 - info->var.blue.length))
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<< info->var.blue.offset;
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g = (green >> (16 - info->var.green.length))
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<< info->var.green.offset;
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((u32 *) info->pseudo_palette)[regno] = r | g | b;
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}
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return 0;
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}
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/*CALLED BY: fb_set_cmap */
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/* fb_set_var, pass 256 colors */
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/*CALLED BY: fb_set_cmap */
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/* fbcon_set_palette, pass 16 colors */
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static int viafb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
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{
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u32 len = cmap->len;
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u32 i;
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u16 *pred = cmap->red;
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u16 *pgreen = cmap->green;
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u16 *pblue = cmap->blue;
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u16 *ptransp = cmap->transp;
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u8 sr1a, sr1b, cr67, cr6a, rev = 0, shift = 10;
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if (len > 256)
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return 1;
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if (UNICHROME_CLE266 == viaparinfo->chip_info->gfx_chip_name) {
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/*
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* Read PCI bus 0, dev 0, function 0, index 0xF6 to get chip
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* rev.
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*/
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outl(0x80000000 | (0xf6 & ~3), (unsigned long)0xCF8);
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rev = (inl((unsigned long)0xCFC) >> ((0xf6 & 3) * 8)) & 0xff;
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}
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switch (info->var.bits_per_pixel) {
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case 8:
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outb(0x1A, 0x3C4);
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sr1a = inb(0x3C5);
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outb(0x1B, 0x3C4);
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sr1b = inb(0x3C5);
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outb(0x67, 0x3D4);
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cr67 = inb(0x3D5);
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outb(0x6A, 0x3D4);
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cr6a = inb(0x3D5);
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/* Map the 3C6/7/8/9 to the IGA2 */
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outb(0x1A, 0x3C4);
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outb(sr1a | 0x01, 0x3C5);
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outb(0x1B, 0x3C4);
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/* Second Display Engine colck always on */
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outb(sr1b | 0x80, 0x3C5);
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outb(0x67, 0x3D4);
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/* Second Display Color Depth 8 */
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outb(cr67 & 0x3F, 0x3D5);
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outb(0x6A, 0x3D4);
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/* Second Display Channel Reset CR6A[6]) */
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outb(cr6a & 0xBF, 0x3D5);
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/* Second Display Channel Enable CR6A[7] */
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outb(cr6a | 0x80, 0x3D5);
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/* Second Display Channel stop reset) */
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outb(cr6a | 0xC0, 0x3D5);
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/* Bit mask of palette */
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outb(0xFF, 0x3c6);
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outb(0x00, 0x3C8);
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if (UNICHROME_CLE266 == viaparinfo->chip_info->gfx_chip_name &&
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rev >= 15) {
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shift = 8;
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viafb_write_reg_mask(CR6A, VIACR, BIT5, BIT5);
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viafb_write_reg_mask(SR15, VIASR, BIT7, BIT7);
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} else {
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shift = 10;
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viafb_write_reg_mask(CR6A, VIACR, 0, BIT5);
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viafb_write_reg_mask(SR15, VIASR, 0, BIT7);
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}
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for (i = 0; i < len; i++) {
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outb((*(pred + i)) >> shift, 0x3C9);
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outb((*(pgreen + i)) >> shift, 0x3C9);
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outb((*(pblue + i)) >> shift, 0x3C9);
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}
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outb(0x1A, 0x3C4);
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/* Map the 3C6/7/8/9 to the IGA1 */
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outb(sr1a & 0xFE, 0x3C5);
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/* Bit mask of palette */
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outb(0xFF, 0x3c6);
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outb(0x00, 0x3C8);
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for (i = 0; i < len; i++) {
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outb((*(pred + i)) >> shift, 0x3C9);
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outb((*(pgreen + i)) >> shift, 0x3C9);
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outb((*(pblue + i)) >> shift, 0x3C9);
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}
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outb(0x1A, 0x3C4);
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outb(sr1a, 0x3C5);
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outb(0x1B, 0x3C4);
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outb(sr1b, 0x3C5);
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outb(0x67, 0x3D4);
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outb(cr67, 0x3D5);
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outb(0x6A, 0x3D4);
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outb(cr6a, 0x3D5);
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break;
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case 16:
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if (len > 17)
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return 0; /* Because static u32 pseudo_pal[17]; */
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for (i = 0; i < len; i++)
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((u32 *) info->pseudo_palette)[i] =
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(*(pred + i) & 0xF800) |
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((*(pgreen + i) & 0xFC00) >> 5) |
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((*(pblue + i) & 0xF800) >> 11);
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break;
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case 32:
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if (len > 17)
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return 0;
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if (ptransp) {
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for (i = 0; i < len; i++)
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((u32 *) info->pseudo_palette)[i] =
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((*(ptransp + i) & 0xFF00) << 16) |
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((*(pred + i) & 0xFF00) << 8) |
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((*(pgreen + i) & 0xFF00)) |
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((*(pblue + i) & 0xFF00) >> 8);
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} else {
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for (i = 0; i < len; i++)
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((u32 *) info->pseudo_palette)[i] =
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0x00000000 |
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((*(pred + i) & 0xFF00) << 8) |
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((*(pgreen + i) & 0xFF00)) |
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((*(pblue + i) & 0xFF00) >> 8);
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}
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break;
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}
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return 0;
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}
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static int viafb_pan_display(struct fb_var_screeninfo *var,
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@ -2286,7 +2100,6 @@ static struct fb_ops viafb_ops = {
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.fb_cursor = viafb_cursor,
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.fb_ioctl = viafb_ioctl,
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.fb_sync = viafb_sync,
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.fb_setcmap = viafb_setcmap,
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};
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module_init(viafb_init);
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