mmc: sdhci-msm: Add platform_execute_tuning implementation
This patch adds implementation for platform specific tuning in order to support HS200 bus speed mode on Qualcomm SDHCI controller. Signed-off-by: Asutosh Das <asutoshd@codeaurora.org> Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org> Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
This commit is contained in:
Georgi Djakov
Chris Ball
Родитель
0eb0d9f4de
Коммит
415b5a75da
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@ -18,6 +18,8 @@
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#include <linux/of_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/delay.h>
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#include <linux/mmc/mmc.h>
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#include <linux/slab.h>
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#include "sdhci-pltfm.h"
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@ -26,6 +28,42 @@
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#define CORE_POWER 0x0
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#define CORE_SW_RST BIT(7)
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#define MAX_PHASES 16
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#define CORE_DLL_LOCK BIT(7)
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#define CORE_DLL_EN BIT(16)
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#define CORE_CDR_EN BIT(17)
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#define CORE_CK_OUT_EN BIT(18)
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#define CORE_CDR_EXT_EN BIT(19)
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#define CORE_DLL_PDN BIT(29)
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#define CORE_DLL_RST BIT(30)
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#define CORE_DLL_CONFIG 0x100
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#define CORE_DLL_STATUS 0x108
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#define CORE_VENDOR_SPEC 0x10c
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#define CORE_CLK_PWRSAVE BIT(1)
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#define CDR_SELEXT_SHIFT 20
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#define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
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#define CMUX_SHIFT_PHASE_SHIFT 24
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#define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT)
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static const u32 tuning_block_64[] = {
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0x00ff0fff, 0xccc3ccff, 0xffcc3cc3, 0xeffefffe,
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0xddffdfff, 0xfbfffbff, 0xff7fffbf, 0xefbdf777,
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0xf0fff0ff, 0x3cccfc0f, 0xcfcc33cc, 0xeeffefff,
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0xfdfffdff, 0xffbfffdf, 0xfff7ffbb, 0xde7b7ff7
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};
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static const u32 tuning_block_128[] = {
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0xff00ffff, 0x0000ffff, 0xccccffff, 0xcccc33cc,
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0xcc3333cc, 0xffffcccc, 0xffffeeff, 0xffeeeeff,
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0xffddffff, 0xddddffff, 0xbbffffff, 0xbbffffff,
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0xffffffbb, 0xffffff77, 0x77ff7777, 0xffeeddbb,
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0x00ffffff, 0x00ffffff, 0xccffff00, 0xcc33cccc,
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0x3333cccc, 0xffcccccc, 0xffeeffff, 0xeeeeffff,
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0xddffffff, 0xddffffff, 0xffffffdd, 0xffffffbb,
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0xffffbbbb, 0xffff77ff, 0xff7777ff, 0xeeddbb77
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};
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struct sdhci_msm_host {
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struct platform_device *pdev;
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@ -38,15 +76,387 @@ struct sdhci_msm_host {
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};
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/* Platform specific tuning */
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static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
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{
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u32 wait_cnt = 50;
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u8 ck_out_en;
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struct mmc_host *mmc = host->mmc;
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/* Poll for CK_OUT_EN bit. max. poll time = 50us */
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ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
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CORE_CK_OUT_EN);
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while (ck_out_en != poll) {
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if (--wait_cnt == 0) {
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dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
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mmc_hostname(mmc), poll);
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return -ETIMEDOUT;
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}
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udelay(1);
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ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
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CORE_CK_OUT_EN);
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}
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return 0;
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}
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static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
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{
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int rc;
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static const u8 grey_coded_phase_table[] = {
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0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
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0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
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};
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unsigned long flags;
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u32 config;
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struct mmc_host *mmc = host->mmc;
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spin_lock_irqsave(&host->lock, flags);
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config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
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config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
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config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
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writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
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/* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
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rc = msm_dll_poll_ck_out_en(host, 0);
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if (rc)
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goto err_out;
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/*
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* Write the selected DLL clock output phase (0 ... 15)
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* to CDR_SELEXT bit field of DLL_CONFIG register.
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*/
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config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
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config &= ~CDR_SELEXT_MASK;
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config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
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writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
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/* Set CK_OUT_EN bit of DLL_CONFIG register to 1. */
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writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
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| CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG);
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/* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
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rc = msm_dll_poll_ck_out_en(host, 1);
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if (rc)
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goto err_out;
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config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
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config |= CORE_CDR_EN;
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config &= ~CORE_CDR_EXT_EN;
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writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
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goto out;
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err_out:
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dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
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mmc_hostname(mmc), phase);
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out:
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spin_unlock_irqrestore(&host->lock, flags);
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return rc;
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}
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/*
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* Find out the greatest range of consecuitive selected
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* DLL clock output phases that can be used as sampling
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* setting for SD3.0 UHS-I card read operation (in SDR104
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* timing mode) or for eMMC4.5 card read operation (in HS200
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* timing mode).
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* Select the 3/4 of the range and configure the DLL with the
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* selected DLL clock output phase.
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*/
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static int msm_find_most_appropriate_phase(struct sdhci_host *host,
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u8 *phase_table, u8 total_phases)
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{
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int ret;
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u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
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u8 phases_per_row[MAX_PHASES] = { 0 };
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int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
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int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
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bool phase_0_found = false, phase_15_found = false;
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struct mmc_host *mmc = host->mmc;
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if (!total_phases || (total_phases > MAX_PHASES)) {
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dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
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mmc_hostname(mmc), total_phases);
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return -EINVAL;
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}
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for (cnt = 0; cnt < total_phases; cnt++) {
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ranges[row_index][col_index] = phase_table[cnt];
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phases_per_row[row_index] += 1;
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col_index++;
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if ((cnt + 1) == total_phases) {
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continue;
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/* check if next phase in phase_table is consecutive or not */
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} else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
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row_index++;
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col_index = 0;
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}
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}
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if (row_index >= MAX_PHASES)
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return -EINVAL;
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/* Check if phase-0 is present in first valid window? */
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if (!ranges[0][0]) {
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phase_0_found = true;
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phase_0_raw_index = 0;
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/* Check if cycle exist between 2 valid windows */
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for (cnt = 1; cnt <= row_index; cnt++) {
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if (phases_per_row[cnt]) {
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for (i = 0; i < phases_per_row[cnt]; i++) {
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if (ranges[cnt][i] == 15) {
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phase_15_found = true;
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phase_15_raw_index = cnt;
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break;
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}
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}
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}
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}
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}
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/* If 2 valid windows form cycle then merge them as single window */
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if (phase_0_found && phase_15_found) {
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/* number of phases in raw where phase 0 is present */
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u8 phases_0 = phases_per_row[phase_0_raw_index];
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/* number of phases in raw where phase 15 is present */
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u8 phases_15 = phases_per_row[phase_15_raw_index];
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if (phases_0 + phases_15 >= MAX_PHASES)
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/*
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* If there are more than 1 phase windows then total
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* number of phases in both the windows should not be
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* more than or equal to MAX_PHASES.
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*/
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return -EINVAL;
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/* Merge 2 cyclic windows */
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i = phases_15;
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for (cnt = 0; cnt < phases_0; cnt++) {
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ranges[phase_15_raw_index][i] =
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ranges[phase_0_raw_index][cnt];
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if (++i >= MAX_PHASES)
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break;
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}
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phases_per_row[phase_0_raw_index] = 0;
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phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
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}
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for (cnt = 0; cnt <= row_index; cnt++) {
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if (phases_per_row[cnt] > curr_max) {
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curr_max = phases_per_row[cnt];
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selected_row_index = cnt;
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}
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}
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i = (curr_max * 3) / 4;
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if (i)
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i--;
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ret = ranges[selected_row_index][i];
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if (ret >= MAX_PHASES) {
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ret = -EINVAL;
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dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
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mmc_hostname(mmc), ret);
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}
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return ret;
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}
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static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
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{
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u32 mclk_freq = 0, config;
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/* Program the MCLK value to MCLK_FREQ bit field */
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if (host->clock <= 112000000)
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mclk_freq = 0;
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else if (host->clock <= 125000000)
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mclk_freq = 1;
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else if (host->clock <= 137000000)
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mclk_freq = 2;
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else if (host->clock <= 150000000)
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mclk_freq = 3;
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else if (host->clock <= 162000000)
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mclk_freq = 4;
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else if (host->clock <= 175000000)
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mclk_freq = 5;
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else if (host->clock <= 187000000)
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mclk_freq = 6;
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else if (host->clock <= 200000000)
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mclk_freq = 7;
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config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
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config &= ~CMUX_SHIFT_PHASE_MASK;
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config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
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writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
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}
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/* Initialize the DLL (Programmable Delay Line) */
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static int msm_init_cm_dll(struct sdhci_host *host)
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{
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struct mmc_host *mmc = host->mmc;
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int wait_cnt = 50;
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unsigned long flags;
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spin_lock_irqsave(&host->lock, flags);
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/*
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* Make sure that clock is always enabled when DLL
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* tuning is in progress. Keeping PWRSAVE ON may
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* turn off the clock.
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*/
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writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC)
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& ~CORE_CLK_PWRSAVE), host->ioaddr + CORE_VENDOR_SPEC);
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/* Write 1 to DLL_RST bit of DLL_CONFIG register */
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writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
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| CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG);
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/* Write 1 to DLL_PDN bit of DLL_CONFIG register */
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writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
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| CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG);
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msm_cm_dll_set_freq(host);
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/* Write 0 to DLL_RST bit of DLL_CONFIG register */
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writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
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& ~CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG);
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/* Write 0 to DLL_PDN bit of DLL_CONFIG register */
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writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
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& ~CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG);
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/* Set DLL_EN bit to 1. */
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writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
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| CORE_DLL_EN), host->ioaddr + CORE_DLL_CONFIG);
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/* Set CK_OUT_EN bit to 1. */
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writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
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| CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG);
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/* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
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while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) &
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CORE_DLL_LOCK)) {
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/* max. wait for 50us sec for LOCK bit to be set */
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if (--wait_cnt == 0) {
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dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
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mmc_hostname(mmc));
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spin_unlock_irqrestore(&host->lock, flags);
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return -ETIMEDOUT;
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}
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udelay(1);
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}
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spin_unlock_irqrestore(&host->lock, flags);
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return 0;
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}
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static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
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{
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int tuning_seq_cnt = 3;
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u8 phase, *data_buf, tuned_phases[16], tuned_phase_cnt = 0;
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const u32 *tuning_block_pattern = tuning_block_64;
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int size = sizeof(tuning_block_64); /* Pattern size in bytes */
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int rc;
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struct mmc_host *mmc = host->mmc;
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struct mmc_ios ios = host->mmc->ios;
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/*
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* Tuning is required for SDR104, HS200 and HS400 cards and if the clock
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* frequency greater than 100MHz in those modes. The standard tuning
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* procedure should not be executed, but a custom implementation will be
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* added here instead.
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* Tuning is required for SDR104, HS200 and HS400 cards and
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* if clock frequency is greater than 100MHz in these modes.
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*/
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return 0;
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if (host->clock <= 100 * 1000 * 1000 ||
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!((ios.timing == MMC_TIMING_MMC_HS200) ||
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(ios.timing == MMC_TIMING_UHS_SDR104)))
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return 0;
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if ((opcode == MMC_SEND_TUNING_BLOCK_HS200) &&
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(mmc->ios.bus_width == MMC_BUS_WIDTH_8)) {
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tuning_block_pattern = tuning_block_128;
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size = sizeof(tuning_block_128);
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}
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data_buf = kmalloc(size, GFP_KERNEL);
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if (!data_buf)
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return -ENOMEM;
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retry:
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/* First of all reset the tuning block */
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rc = msm_init_cm_dll(host);
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if (rc)
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goto out;
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phase = 0;
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do {
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struct mmc_command cmd = { 0 };
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struct mmc_data data = { 0 };
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struct mmc_request mrq = {
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.cmd = &cmd,
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.data = &data
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};
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struct scatterlist sg;
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/* Set the phase in delay line hw block */
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rc = msm_config_cm_dll_phase(host, phase);
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if (rc)
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goto out;
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cmd.opcode = opcode;
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cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
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data.blksz = size;
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data.blocks = 1;
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data.flags = MMC_DATA_READ;
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data.timeout_ns = NSEC_PER_SEC; /* 1 second */
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data.sg = &sg;
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data.sg_len = 1;
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sg_init_one(&sg, data_buf, size);
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memset(data_buf, 0, size);
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mmc_wait_for_req(mmc, &mrq);
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if (!cmd.error && !data.error &&
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!memcmp(data_buf, tuning_block_pattern, size)) {
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/* Tuning is successful at this tuning point */
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tuned_phases[tuned_phase_cnt++] = phase;
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dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
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mmc_hostname(mmc), phase);
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}
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} while (++phase < ARRAY_SIZE(tuned_phases));
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if (tuned_phase_cnt) {
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rc = msm_find_most_appropriate_phase(host, tuned_phases,
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tuned_phase_cnt);
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if (rc < 0)
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goto out;
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else
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phase = rc;
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||||
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||||
/*
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* Finally set the selected phase in delay
|
||||
* line hw block.
|
||||
*/
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rc = msm_config_cm_dll_phase(host, phase);
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if (rc)
|
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goto out;
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dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
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||||
mmc_hostname(mmc), phase);
|
||||
} else {
|
||||
if (--tuning_seq_cnt)
|
||||
goto retry;
|
||||
/* Tuning failed */
|
||||
dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
|
||||
mmc_hostname(mmc));
|
||||
rc = -EIO;
|
||||
}
|
||||
|
||||
out:
|
||||
kfree(data_buf);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static const struct of_device_id sdhci_msm_dt_match[] = {
|
||||
|
|
|
|||
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Ссылка в новой задаче