drm/i915: Include TLB miss latency in g4x watermark computations
Reports of FIFO underruns are still persisting on gm45. References: https://bugs.freedesktop.org/show_bug.cgi?id=27589 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson
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633f2ea266
Коммит
417ae1476d
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@ -3604,89 +3604,177 @@ static void pineview_update_wm(struct drm_device *dev, int planea_clock,
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}
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}
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static void g4x_update_wm(struct drm_device *dev, int planea_clock,
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int planeb_clock, int sr_hdisplay, int sr_htotal,
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int pixel_size)
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static bool g4x_compute_wm0(struct drm_device *dev,
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int plane,
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const struct intel_watermark_params *display,
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int display_latency_ns,
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const struct intel_watermark_params *cursor,
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int cursor_latency_ns,
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int *plane_wm,
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int *cursor_wm)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int total_size, cacheline_size;
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int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
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struct intel_watermark_params planea_params, planeb_params;
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unsigned long line_time_us;
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int sr_clock, sr_entries = 0, entries_required;
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struct drm_crtc *crtc;
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int htotal, hdisplay, clock, pixel_size;
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int line_time_us, line_count;
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int entries, tlb_miss;
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/* Create copies of the base settings for each pipe */
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planea_params = planeb_params = g4x_wm_info;
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crtc = intel_get_crtc_for_plane(dev, plane);
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if (crtc->fb == NULL || !crtc->enabled)
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return false;
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/* Grab a couple of global values before we overwrite them */
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total_size = planea_params.fifo_size;
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cacheline_size = planea_params.cacheline_size;
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htotal = crtc->mode.htotal;
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hdisplay = crtc->mode.hdisplay;
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clock = crtc->mode.clock;
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pixel_size = crtc->fb->bits_per_pixel / 8;
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/*
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* Note: we need to make sure we don't overflow for various clock &
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* latency values.
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* clocks go from a few thousand to several hundred thousand.
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* latency is usually a few thousand
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*/
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entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
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1000;
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entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
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planea_wm = entries_required + planea_params.guard_size;
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/* Use the small buffer method to calculate plane watermark */
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entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
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tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
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if (tlb_miss > 0)
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entries += tlb_miss;
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entries = DIV_ROUND_UP(entries, display->cacheline_size);
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*plane_wm = entries + display->guard_size;
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if (*plane_wm > (int)display->max_wm)
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*plane_wm = display->max_wm;
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entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
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1000;
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entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
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planeb_wm = entries_required + planeb_params.guard_size;
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/* Use the large buffer method to calculate cursor watermark */
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line_time_us = ((htotal * 1000) / clock);
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line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
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entries = line_count * 64 * pixel_size;
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tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
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if (tlb_miss > 0)
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entries += tlb_miss;
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entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
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*cursor_wm = entries + cursor->guard_size;
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if (*cursor_wm > (int)cursor->max_wm)
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*cursor_wm = (int)cursor->max_wm;
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cursora_wm = cursorb_wm = 16;
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cursor_sr = 32;
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return true;
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}
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DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
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/*
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* Check the wm result.
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*
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* If any calculated watermark values is larger than the maximum value that
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* can be programmed into the associated watermark register, that watermark
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* must be disabled.
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*/
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static bool g4x_check_srwm(struct drm_device *dev,
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int display_wm, int cursor_wm,
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const struct intel_watermark_params *display,
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const struct intel_watermark_params *cursor)
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{
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DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
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display_wm, cursor_wm);
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/* Calc sr entries for one plane configs */
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if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
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/* self-refresh has much higher latency */
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static const int sr_latency_ns = 12000;
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sr_clock = planea_clock ? planea_clock : planeb_clock;
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line_time_us = ((sr_htotal * 1000) / sr_clock);
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/* Use ns/us then divide to preserve precision */
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sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
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pixel_size * sr_hdisplay;
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sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
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entries_required = (((sr_latency_ns / line_time_us) +
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1000) / 1000) * pixel_size * 64;
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entries_required = DIV_ROUND_UP(entries_required,
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g4x_cursor_wm_info.cacheline_size);
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cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
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if (cursor_sr > g4x_cursor_wm_info.max_wm)
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cursor_sr = g4x_cursor_wm_info.max_wm;
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DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
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"cursor %d\n", sr_entries, cursor_sr);
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I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
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} else {
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/* Turn off self refresh if both pipes are enabled */
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I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
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& ~FW_BLC_SELF_EN);
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if (display_wm > display->max_wm) {
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DRM_DEBUG_KMS("display watermark is too large(%d), disabling\n",
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display_wm, display->max_wm);
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return false;
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}
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DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
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planea_wm, planeb_wm, sr_entries);
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if (cursor_wm > cursor->max_wm) {
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DRM_DEBUG_KMS("cursor watermark is too large(%d), disabling\n",
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cursor_wm, cursor->max_wm);
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return false;
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}
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planea_wm &= 0x3f;
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planeb_wm &= 0x3f;
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if (!(display_wm || cursor_wm)) {
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DRM_DEBUG_KMS("SR latency is 0, disabling\n");
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return false;
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}
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I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
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return true;
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}
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static bool g4x_compute_srwm(struct drm_device *dev,
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int hdisplay, int htotal,
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int pixel_size, int clock, int latency_ns,
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const struct intel_watermark_params *display,
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const struct intel_watermark_params *cursor,
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int *display_wm, int *cursor_wm)
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{
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unsigned long line_time_us;
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int line_count, line_size;
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int small, large;
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int entries;
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if (!latency_ns) {
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*display_wm = *cursor_wm = 0;
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return false;
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}
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line_time_us = (htotal * 1000) / clock;
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line_count = (latency_ns / line_time_us + 1000) / 1000;
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line_size = hdisplay * pixel_size;
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/* Use the minimum of the small and large buffer method for primary */
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small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
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large = line_count * line_size;
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entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
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*display_wm = entries + display->guard_size;
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/* calculate the self-refresh watermark for display cursor */
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entries = line_count * pixel_size * 64;
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entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
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*cursor_wm = entries + cursor->guard_size;
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return g4x_check_srwm(dev,
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*display_wm, *cursor_wm,
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display, cursor);
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}
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static void g4x_update_wm(struct drm_device *dev,
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int planea_clock, int planeb_clock,
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int hdisplay, int htotal, int pixel_size)
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{
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static const int sr_latency_ns = 12000;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
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int enabled = 0, plane_sr, cursor_sr, clock;
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if (g4x_compute_wm0(dev, 0,
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&g4x_wm_info, latency_ns,
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&g4x_cursor_wm_info, latency_ns,
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&planea_wm, &cursora_wm))
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enabled++;
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if (g4x_compute_wm0(dev, 1,
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&g4x_wm_info, latency_ns,
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&g4x_cursor_wm_info, latency_ns,
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&planeb_wm, &cursorb_wm))
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enabled++;
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plane_sr = cursor_sr = 0;
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clock = planea_clock ? planea_clock : planeb_clock;
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if (enabled == 1 &&
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g4x_compute_srwm(dev, hdisplay, htotal, pixel_size,
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clock, sr_latency_ns,
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&g4x_wm_info,
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&g4x_cursor_wm_info,
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&plane_sr, &cursor_sr))
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I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
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else
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I915_WRITE(FW_BLC_SELF,
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I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
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DRM_DEBUG("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
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planea_wm, cursora_wm,
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planeb_wm, cursorb_wm,
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plane_sr, cursor_sr);
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I915_WRITE(DSPFW1,
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(plane_sr << DSPFW_SR_SHIFT) |
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(cursorb_wm << DSPFW_CURSORB_SHIFT) |
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(planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
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I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
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(planeb_wm << DSPFW_PLANEB_SHIFT) |
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planea_wm);
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I915_WRITE(DSPFW2,
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(I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
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(cursora_wm << DSPFW_CURSORA_SHIFT));
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/* HPLL off in SR has some issues on G4x... disable it */
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I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
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I915_WRITE(DSPFW3,
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(I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
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(cursor_sr << DSPFW_CURSOR_SR_SHIFT));
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}
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@ -3743,8 +3831,8 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock,
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srwm);
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/* 965 has limitations... */
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I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
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(8 << 0));
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I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
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(8 << 16) | (8 << 8) | (8 << 0));
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I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
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/* update cursor SR watermark */
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I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
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@ -217,6 +217,13 @@ intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
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return dev_priv->pipe_to_crtc_mapping[pipe];
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}
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static inline struct drm_crtc *
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intel_get_crtc_for_plane(struct drm_device *dev, int plane)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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return dev_priv->plane_to_crtc_mapping[plane];
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}
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struct intel_unpin_work {
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struct work_struct work;
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struct drm_device *dev;
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