Merge commit 3669ef9fa7
("x86, tls: Interpret an all-zero struct user_desc as 'no segment'") into x86/asm
Pick up the latestest asm fixes before advancing it any further. Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Коммит
41ca5d4e9b
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@ -14,3 +14,18 @@ Description:
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|||
The /sys/class/mei/meiN directory is created for
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each probed mei device
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What: /sys/class/mei/meiN/fw_status
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Date: Nov 2014
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KernelVersion: 3.19
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Contact: Tomas Winkler <tomas.winkler@intel.com>
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Description: Display fw status registers content
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The ME FW writes its status information into fw status
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registers for BIOS and OS to monitor fw health.
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The register contains running state, power management
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state, error codes, and others. The way the registers
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are decoded depends on PCH or SoC generation.
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Also number of registers varies between 1 and 6
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depending on generation.
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@ -3183,7 +3183,7 @@ L: dmaengine@vger.kernel.org
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Q: https://patchwork.kernel.org/project/linux-dmaengine/list/
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S: Maintained
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F: drivers/dma/
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F: include/linux/dma*
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F: include/linux/dmaengine.h
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F: Documentation/dmaengine/
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T: git git://git.infradead.org/users/vkoul/slave-dma.git
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@ -7747,8 +7747,7 @@ F: Documentation/scsi/LICENSE.qla2xxx
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F: drivers/scsi/qla2xxx/
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QLOGIC QLA4XXX iSCSI DRIVER
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M: Vikas Chaudhary <vikas.chaudhary@qlogic.com>
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M: iscsi-driver@qlogic.com
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M: QLogic-Storage-Upstream@qlogic.com
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L: linux-scsi@vger.kernel.org
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S: Supported
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F: Documentation/scsi/LICENSE.qla4xxx
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|
2
Makefile
2
Makefile
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@ -1,7 +1,7 @@
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VERSION = 3
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PATCHLEVEL = 19
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SUBLEVEL = 0
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EXTRAVERSION = -rc4
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EXTRAVERSION = -rc5
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NAME = Diseased Newt
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# *DOCUMENTATION*
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|
|
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@ -953,6 +953,8 @@
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interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fb>;
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clocks = <&lcd_clk>, <&lcd_clk>;
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clock-names = "lcdc_clk", "hclk";
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status = "disabled";
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};
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|
|
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@ -65,6 +65,8 @@
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};
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&sdhci2 {
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broken-cd;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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|
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@ -83,7 +83,8 @@
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compatible = "mrvl,pxav3-mmc";
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reg = <0xab1000 0x200>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&chip CLKID_SDIO1XIN>;
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clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>;
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clock-names = "io", "core";
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status = "disabled";
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};
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@ -348,36 +349,6 @@
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpio4: gpio@5000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x5000 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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porte: gpio-port@4 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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};
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};
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gpio5: gpio@c000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0xc000 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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portf: gpio-port@5 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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};
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};
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};
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chip: chip-control@ea0000 {
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@ -466,6 +437,21 @@
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ranges = <0 0xfc0000 0x10000>;
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interrupt-parent = <&sic>;
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sm_gpio1: gpio@5000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x5000 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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portf: gpio-port@5 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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};
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};
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i2c2: i2c@7000 {
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compatible = "snps,designware-i2c";
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#address-cells = <1>;
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@ -516,6 +502,21 @@
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status = "disabled";
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};
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sm_gpio0: gpio@c000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0xc000 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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porte: gpio-port@4 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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};
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};
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sysctrl: pin-controller@d000 {
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compatible = "marvell,berlin2q-system-ctrl";
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reg = <0xd000 0x100>;
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@ -499,23 +499,23 @@
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};
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partition@5 {
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label = "QSPI.u-boot-spl-os";
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reg = <0x00140000 0x00010000>;
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reg = <0x00140000 0x00080000>;
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};
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partition@6 {
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label = "QSPI.u-boot-env";
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reg = <0x00150000 0x00010000>;
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reg = <0x001c0000 0x00010000>;
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};
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partition@7 {
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label = "QSPI.u-boot-env.backup1";
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reg = <0x00160000 0x0010000>;
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reg = <0x001d0000 0x0010000>;
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};
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partition@8 {
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label = "QSPI.kernel";
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reg = <0x00170000 0x0800000>;
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reg = <0x001e0000 0x0800000>;
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};
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partition@9 {
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label = "QSPI.file-system";
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reg = <0x00970000 0x01690000>;
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reg = <0x009e0000 0x01620000>;
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};
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};
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};
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@ -736,7 +736,7 @@
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dp_phy: video-phy@10040720 {
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compatible = "samsung,exynos5250-dp-video-phy";
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reg = <0x10040720 4>;
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samsung,pmu-syscon = <&pmu_system_controller>;
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#phy-cells = <0>;
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};
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@ -372,3 +372,7 @@
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&usbdrd_dwc3_1 {
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dr_mode = "host";
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};
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&cci {
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status = "disabled";
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};
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@ -120,7 +120,7 @@
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};
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};
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cci@10d20000 {
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cci: cci@10d20000 {
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compatible = "arm,cci-400";
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#address-cells = <1>;
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#size-cells = <1>;
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@ -503,8 +503,8 @@
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};
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dp_phy: video-phy@10040728 {
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compatible = "samsung,exynos5250-dp-video-phy";
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reg = <0x10040728 4>;
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compatible = "samsung,exynos5420-dp-video-phy";
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samsung,pmu-syscon = <&pmu_system_controller>;
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#phy-cells = <0>;
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};
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@ -162,7 +162,7 @@
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#size-cells = <0>;
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compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
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reg = <0x43fa4000 0x4000>;
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clocks = <&clks 62>, <&clks 62>;
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clocks = <&clks 78>, <&clks 78>;
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clock-names = "ipg", "per";
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interrupts = <14>;
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status = "disabled";
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|
|
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@ -127,24 +127,12 @@
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#address-cells = <1>;
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#size-cells = <0>;
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reg_usbh1_vbus: regulator@0 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbh1reg>;
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reg = <0>;
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regulator-name = "usbh1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usbotg_vbus: regulator@1 {
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reg_hub_reset: regulator@0 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotgreg>;
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reg = <1>;
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regulator-name = "usbotg_vbus";
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reg = <0>;
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regulator-name = "hub_reset";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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|
@ -176,6 +164,7 @@
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reg = <0>;
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clocks = <&clks IMX5_CLK_DUMMY>;
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clock-names = "main_clk";
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reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
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};
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};
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};
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|
@ -419,7 +408,7 @@
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&usbh1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbh1>;
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vbus-supply = <®_usbh1_vbus>;
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vbus-supply = <®_hub_reset>;
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fsl,usbphy = <&usbh1phy>;
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phy_type = "ulpi";
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status = "okay";
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|
@ -429,7 +418,6 @@
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dr_mode = "otg";
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disable-over-current;
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phy_type = "utmi_wide";
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vbus-supply = <®_usbotg_vbus>;
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status = "okay";
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};
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|
|
|
@ -335,8 +335,8 @@
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vpu: vpu@02040000 {
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compatible = "cnm,coda960";
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reg = <0x02040000 0x3c000>;
|
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interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
|
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<0 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "bit", "jpeg";
|
||||
clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
|
||||
<&clks IMX6QDL_CLK_MMDC_CH0_AXI>,
|
||||
|
|
|
@ -142,6 +142,7 @@
|
|||
scfg: scfg@1570000 {
|
||||
compatible = "fsl,ls1021a-scfg", "syscon";
|
||||
reg = <0x0 0x1570000 0x0 0x10000>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
clockgen: clocking@1ee1000 {
|
||||
|
|
|
@ -700,11 +700,9 @@
|
|||
};
|
||||
};
|
||||
|
||||
/* Ethernet is on some early development boards and qemu */
|
||||
ethernet@gpmc {
|
||||
compatible = "smsc,lan91c94";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */
|
||||
reg = <1 0x300 0xf>; /* 16 byte IO range at offset 0x300 */
|
||||
|
|
|
@ -155,6 +155,15 @@
|
|||
};
|
||||
|
||||
&pinctrl {
|
||||
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
|
||||
bias-pull-up;
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
backlight {
|
||||
bl_en: bl-en {
|
||||
rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
|
@ -173,6 +182,27 @@
|
|||
};
|
||||
};
|
||||
|
||||
sdmmc {
|
||||
/*
|
||||
* Default drive strength isn't enough to achieve even
|
||||
* high-speed mode on EVB board so bump up to 8ma.
|
||||
*/
|
||||
sdmmc_bus4: sdmmc-bus4 {
|
||||
rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
|
||||
<6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
|
||||
<6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
|
||||
<6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
|
||||
};
|
||||
|
||||
sdmmc_clk: sdmmc-clk {
|
||||
rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
|
||||
};
|
||||
|
||||
sdmmc_cmd: sdmmc-cmd {
|
||||
rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
host_vbus_drv: host-vbus-drv {
|
||||
rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
|
|
|
@ -176,7 +176,7 @@
|
|||
"Headphone Jack", "HPOUTR",
|
||||
"IN2L", "Line In Jack",
|
||||
"IN2R", "Line In Jack",
|
||||
"MICBIAS", "IN1L",
|
||||
"Mic", "MICBIAS",
|
||||
"IN1L", "Mic";
|
||||
|
||||
atmel,ssc-controller = <&ssc0>;
|
||||
|
|
|
@ -1008,7 +1008,7 @@
|
|||
|
||||
pit: timer@fc068630 {
|
||||
compatible = "atmel,at91sam9260-pit";
|
||||
reg = <0xfc068630 0xf>;
|
||||
reg = <0xfc068630 0x10>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
clocks = <&h32ck>;
|
||||
};
|
||||
|
|
|
@ -25,11 +25,11 @@
|
|||
stmpe2401_1 {
|
||||
stmpe2401_1_nhk_mode: stmpe2401_1_nhk {
|
||||
nhk_cfg1 {
|
||||
ste,pins = "GPIO76_B20"; // IRQ line
|
||||
pins = "GPIO76_B20"; // IRQ line
|
||||
ste,input = <0>;
|
||||
};
|
||||
nhk_cfg2 {
|
||||
ste,pins = "GPIO77_B8"; // reset line
|
||||
pins = "GPIO77_B8"; // reset line
|
||||
ste,output = <1>;
|
||||
};
|
||||
};
|
||||
|
@ -37,11 +37,11 @@
|
|||
stmpe2401_2 {
|
||||
stmpe2401_2_nhk_mode: stmpe2401_2_nhk {
|
||||
nhk_cfg1 {
|
||||
ste,pins = "GPIO78_A8"; // IRQ line
|
||||
pins = "GPIO78_A8"; // IRQ line
|
||||
ste,input = <0>;
|
||||
};
|
||||
nhk_cfg2 {
|
||||
ste,pins = "GPIO79_C9"; // reset line
|
||||
pins = "GPIO79_C9"; // reset line
|
||||
ste,output = <1>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -84,7 +84,8 @@ CONFIG_DEBUG_GPIO=y
|
|||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_BATTERY_SBS=y
|
||||
CONFIG_CHARGER_TPS65090=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_HWMON=y
|
||||
CONFIG_SENSORS_LM90=y
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_EXYNOS_THERMAL=y
|
||||
CONFIG_EXYNOS_THERMAL_CORE=y
|
||||
|
@ -109,11 +110,26 @@ CONFIG_REGULATOR_S2MPA01=y
|
|||
CONFIG_REGULATOR_S2MPS11=y
|
||||
CONFIG_REGULATOR_S5M8767=y
|
||||
CONFIG_REGULATOR_TPS65090=y
|
||||
CONFIG_DRM=y
|
||||
CONFIG_DRM_BRIDGE=y
|
||||
CONFIG_DRM_PTN3460=y
|
||||
CONFIG_DRM_PS8622=y
|
||||
CONFIG_DRM_EXYNOS=y
|
||||
CONFIG_DRM_EXYNOS_FIMD=y
|
||||
CONFIG_DRM_EXYNOS_DP=y
|
||||
CONFIG_DRM_PANEL=y
|
||||
CONFIG_DRM_PANEL_SIMPLE=y
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_MODE_HELPERS=y
|
||||
CONFIG_FB_SIMPLE=y
|
||||
CONFIG_EXYNOS_VIDEO=y
|
||||
CONFIG_EXYNOS_MIPI_DSI=y
|
||||
CONFIG_BACKLIGHT_LCD_SUPPORT=y
|
||||
CONFIG_LCD_CLASS_DEVICE=y
|
||||
CONFIG_LCD_PLATFORM=y
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
CONFIG_BACKLIGHT_GENERIC=y
|
||||
CONFIG_BACKLIGHT_PWM=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_FONTS=y
|
||||
CONFIG_FONT_7x14=y
|
||||
|
|
|
@ -68,7 +68,7 @@ CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
|
|||
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
|
||||
CONFIG_CPU_FREQ_GOV_USERSPACE=y
|
||||
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
|
||||
CONFIG_GENERIC_CPUFREQ_CPU0=y
|
||||
CONFIG_CPUFREQ_DT=y
|
||||
# CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_BINFMT_MISC=y
|
||||
|
|
|
@ -17,6 +17,7 @@
|
|||
#include <linux/of_platform.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/phy.h>
|
||||
|
||||
#include <asm/setup.h>
|
||||
#include <asm/irq.h>
|
||||
|
@ -26,8 +27,25 @@
|
|||
|
||||
#include "generic.h"
|
||||
|
||||
static int ksz8081_phy_fixup(struct phy_device *phy)
|
||||
{
|
||||
int value;
|
||||
|
||||
value = phy_read(phy, 0x16);
|
||||
value &= ~0x20;
|
||||
phy_write(phy, 0x16, value);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init sama5_dt_device_init(void)
|
||||
{
|
||||
if (of_machine_is_compatible("atmel,sama5d4ek") &&
|
||||
IS_ENABLED(CONFIG_PHYLIB)) {
|
||||
phy_register_fixup_for_id("fc028000.etherne:00",
|
||||
ksz8081_phy_fixup);
|
||||
}
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
|
|
|
@ -144,7 +144,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
|||
post_div_table[1].div = 1;
|
||||
post_div_table[2].div = 1;
|
||||
video_div_table[1].div = 1;
|
||||
video_div_table[2].div = 1;
|
||||
video_div_table[3].div = 1;
|
||||
}
|
||||
|
||||
clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
|
||||
|
|
|
@ -558,6 +558,9 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
|
|||
clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
|
||||
clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
|
||||
|
||||
clk_set_parent(clks[IMX6SX_CLK_QSPI1_SEL], clks[IMX6SX_CLK_PLL2_BUS]);
|
||||
clk_set_parent(clks[IMX6SX_CLK_QSPI2_SEL], clks[IMX6SX_CLK_PLL2_BUS]);
|
||||
|
||||
/* Set initial power mode */
|
||||
imx6q_set_lpm(WAIT_CLOCKED);
|
||||
}
|
||||
|
|
|
@ -77,6 +77,24 @@ MACHINE_END
|
|||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP3
|
||||
/* Some boards need board name for legacy userspace in /proc/cpuinfo */
|
||||
static const char *const n900_boards_compat[] __initconst = {
|
||||
"nokia,omap3-n900",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(OMAP3_N900_DT, "Nokia RX-51 board")
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap3_map_io,
|
||||
.init_early = omap3430_init_early,
|
||||
.init_machine = omap_generic_init,
|
||||
.init_late = omap3_init_late,
|
||||
.init_time = omap3_sync32k_timer_init,
|
||||
.dt_compat = n900_boards_compat,
|
||||
.restart = omap3xxx_restart,
|
||||
MACHINE_END
|
||||
|
||||
/* Generic omap3 boards, most boards can use these */
|
||||
static const char *const omap3_boards_compat[] __initconst = {
|
||||
"ti,omap3430",
|
||||
"ti,omap3",
|
||||
|
|
|
@ -249,6 +249,7 @@ extern void omap4_cpu_die(unsigned int cpu);
|
|||
extern struct smp_operations omap4_smp_ops;
|
||||
|
||||
extern void omap5_secondary_startup(void);
|
||||
extern void omap5_secondary_hyp_startup(void);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SMP) && defined(CONFIG_PM)
|
||||
|
|
|
@ -286,6 +286,10 @@
|
|||
#define OMAP5XXX_CONTROL_STATUS 0x134
|
||||
#define OMAP5_DEVICETYPE_MASK (0x7 << 6)
|
||||
|
||||
/* DRA7XX CONTROL CORE BOOTSTRAP */
|
||||
#define DRA7_CTRL_CORE_BOOTSTRAP 0x6c4
|
||||
#define DRA7_SPEEDSELECT_MASK (0x3 << 8)
|
||||
|
||||
/*
|
||||
* REVISIT: This list of registers is not comprehensive - there are more
|
||||
* that should be added.
|
||||
|
|
|
@ -22,6 +22,7 @@
|
|||
|
||||
/* Physical address needed since MMU not enabled yet on secondary core */
|
||||
#define AUX_CORE_BOOT0_PA 0x48281800
|
||||
#define API_HYP_ENTRY 0x102
|
||||
|
||||
/*
|
||||
* OMAP5 specific entry point for secondary CPU to jump from ROM
|
||||
|
@ -40,6 +41,26 @@ wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
|
|||
bne wait
|
||||
b secondary_startup
|
||||
ENDPROC(omap5_secondary_startup)
|
||||
/*
|
||||
* Same as omap5_secondary_startup except we call into the ROM to
|
||||
* enable HYP mode first. This is called instead of
|
||||
* omap5_secondary_startup if the primary CPU was put into HYP mode by
|
||||
* the boot loader.
|
||||
*/
|
||||
ENTRY(omap5_secondary_hyp_startup)
|
||||
wait_2: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
|
||||
ldr r0, [r2]
|
||||
mov r0, r0, lsr #5
|
||||
mrc p15, 0, r4, c0, c0, 5
|
||||
and r4, r4, #0x0f
|
||||
cmp r0, r4
|
||||
bne wait_2
|
||||
ldr r12, =API_HYP_ENTRY
|
||||
adr r0, hyp_boot
|
||||
smc #0
|
||||
hyp_boot:
|
||||
b secondary_startup
|
||||
ENDPROC(omap5_secondary_hyp_startup)
|
||||
/*
|
||||
* OMAP4 specific entry point for secondary CPU to jump from ROM
|
||||
* code. This routine also provides a holding flag into which
|
||||
|
|
|
@ -22,6 +22,7 @@
|
|||
#include <linux/irqchip/arm-gic.h>
|
||||
|
||||
#include <asm/smp_scu.h>
|
||||
#include <asm/virt.h>
|
||||
|
||||
#include "omap-secure.h"
|
||||
#include "omap-wakeupgen.h"
|
||||
|
@ -227,8 +228,16 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
|
|||
if (omap_secure_apis_support())
|
||||
omap_auxcoreboot_addr(virt_to_phys(startup_addr));
|
||||
else
|
||||
writel_relaxed(virt_to_phys(omap5_secondary_startup),
|
||||
base + OMAP_AUX_CORE_BOOT_1);
|
||||
/*
|
||||
* If the boot CPU is in HYP mode then start secondary
|
||||
* CPU in HYP mode as well.
|
||||
*/
|
||||
if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
|
||||
writel_relaxed(virt_to_phys(omap5_secondary_hyp_startup),
|
||||
base + OMAP_AUX_CORE_BOOT_1);
|
||||
else
|
||||
writel_relaxed(virt_to_phys(omap5_secondary_startup),
|
||||
base + OMAP_AUX_CORE_BOOT_1);
|
||||
|
||||
}
|
||||
|
||||
|
|
|
@ -54,6 +54,7 @@
|
|||
|
||||
#include "soc.h"
|
||||
#include "common.h"
|
||||
#include "control.h"
|
||||
#include "powerdomain.h"
|
||||
#include "omap-secure.h"
|
||||
|
||||
|
@ -496,7 +497,8 @@ static void __init realtime_counter_init(void)
|
|||
void __iomem *base;
|
||||
static struct clk *sys_clk;
|
||||
unsigned long rate;
|
||||
unsigned int reg, num, den;
|
||||
unsigned int reg;
|
||||
unsigned long long num, den;
|
||||
|
||||
base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
|
||||
if (!base) {
|
||||
|
@ -511,13 +513,42 @@ static void __init realtime_counter_init(void)
|
|||
}
|
||||
|
||||
rate = clk_get_rate(sys_clk);
|
||||
|
||||
if (soc_is_dra7xx()) {
|
||||
/*
|
||||
* Errata i856 says the 32.768KHz crystal does not start at
|
||||
* power on, so the CPU falls back to an emulated 32KHz clock
|
||||
* based on sysclk / 610 instead. This causes the master counter
|
||||
* frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
|
||||
* (OR sysclk * 75 / 244)
|
||||
*
|
||||
* This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
|
||||
* Of course any board built without a populated 32.768KHz
|
||||
* crystal would also need this fix even if the CPU is fixed
|
||||
* later.
|
||||
*
|
||||
* Either case can be detected by using the two speedselect bits
|
||||
* If they are not 0, then the 32.768KHz clock driving the
|
||||
* coarse counter that corrects the fine counter every time it
|
||||
* ticks is actually rate/610 rather than 32.768KHz and we
|
||||
* should compensate to avoid the 570ppm (at 20MHz, much worse
|
||||
* at other rates) too fast system time.
|
||||
*/
|
||||
reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
|
||||
if (reg & DRA7_SPEEDSELECT_MASK) {
|
||||
num = 75;
|
||||
den = 244;
|
||||
goto sysclk1_based;
|
||||
}
|
||||
}
|
||||
|
||||
/* Numerator/denumerator values refer TRM Realtime Counter section */
|
||||
switch (rate) {
|
||||
case 1200000:
|
||||
case 12000000:
|
||||
num = 64;
|
||||
den = 125;
|
||||
break;
|
||||
case 1300000:
|
||||
case 13000000:
|
||||
num = 768;
|
||||
den = 1625;
|
||||
break;
|
||||
|
@ -529,11 +560,11 @@ static void __init realtime_counter_init(void)
|
|||
num = 192;
|
||||
den = 625;
|
||||
break;
|
||||
case 2600000:
|
||||
case 26000000:
|
||||
num = 384;
|
||||
den = 1625;
|
||||
break;
|
||||
case 2700000:
|
||||
case 27000000:
|
||||
num = 256;
|
||||
den = 1125;
|
||||
break;
|
||||
|
@ -545,6 +576,7 @@ static void __init realtime_counter_init(void)
|
|||
break;
|
||||
}
|
||||
|
||||
sysclk1_based:
|
||||
/* Program numerator and denumerator registers */
|
||||
reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
|
||||
NUMERATOR_DENUMERATOR_MASK;
|
||||
|
@ -556,7 +588,7 @@ static void __init realtime_counter_init(void)
|
|||
reg |= den;
|
||||
writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
|
||||
|
||||
arch_timer_freq = (rate / den) * num;
|
||||
arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
|
||||
set_cntfreq();
|
||||
|
||||
iounmap(base);
|
||||
|
|
|
@ -19,11 +19,37 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include "core.h"
|
||||
|
||||
#define RK3288_GRF_SOC_CON0 0x244
|
||||
|
||||
static void __init rockchip_timer_init(void)
|
||||
{
|
||||
if (of_machine_is_compatible("rockchip,rk3288")) {
|
||||
struct regmap *grf;
|
||||
|
||||
/*
|
||||
* Disable auto jtag/sdmmc switching that causes issues
|
||||
* with the mmc controllers making them unreliable
|
||||
*/
|
||||
grf = syscon_regmap_lookup_by_compatible("rockchip,rk3288-grf");
|
||||
if (!IS_ERR(grf))
|
||||
regmap_write(grf, RK3288_GRF_SOC_CON0, 0x10000000);
|
||||
else
|
||||
pr_err("rockchip: could not get grf syscon\n");
|
||||
}
|
||||
|
||||
of_clk_init(NULL);
|
||||
clocksource_of_init();
|
||||
}
|
||||
|
||||
static void __init rockchip_dt_init(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
|
@ -42,6 +68,7 @@ static const char * const rockchip_board_dt_compat[] = {
|
|||
DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)")
|
||||
.l2c_aux_val = 0,
|
||||
.l2c_aux_mask = ~0,
|
||||
.init_time = rockchip_timer_init,
|
||||
.dt_compat = rockchip_board_dt_compat,
|
||||
.init_machine = rockchip_dt_init,
|
||||
MACHINE_END
|
||||
|
|
|
@ -800,7 +800,14 @@ void __init r8a7740_init_irq_of(void)
|
|||
void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
|
||||
void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
|
||||
|
||||
#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
|
||||
void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000);
|
||||
void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000);
|
||||
|
||||
gic_init(0, 29, gic_dist_base, gic_cpu_base);
|
||||
#else
|
||||
irqchip_init();
|
||||
#endif
|
||||
|
||||
/* route signals to GIC */
|
||||
iowrite32(0x0, pfc_inta_ctrl);
|
||||
|
|
|
@ -595,6 +595,7 @@ static struct platform_device ipmmu_device = {
|
|||
|
||||
static struct renesas_intc_irqpin_config irqpin0_platform_data = {
|
||||
.irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
|
||||
.control_parent = true,
|
||||
};
|
||||
|
||||
static struct resource irqpin0_resources[] = {
|
||||
|
@ -656,6 +657,7 @@ static struct platform_device irqpin1_device = {
|
|||
|
||||
static struct renesas_intc_irqpin_config irqpin2_platform_data = {
|
||||
.irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
|
||||
.control_parent = true,
|
||||
};
|
||||
|
||||
static struct resource irqpin2_resources[] = {
|
||||
|
@ -686,6 +688,7 @@ static struct platform_device irqpin2_device = {
|
|||
|
||||
static struct renesas_intc_irqpin_config irqpin3_platform_data = {
|
||||
.irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
|
||||
.control_parent = true,
|
||||
};
|
||||
|
||||
static struct resource irqpin3_resources[] = {
|
||||
|
|
|
@ -44,7 +44,7 @@
|
|||
#define __ARM_NR_compat_cacheflush (__ARM_NR_COMPAT_BASE+2)
|
||||
#define __ARM_NR_compat_set_tls (__ARM_NR_COMPAT_BASE+5)
|
||||
|
||||
#define __NR_compat_syscalls 387
|
||||
#define __NR_compat_syscalls 388
|
||||
#endif
|
||||
|
||||
#define __ARCH_WANT_SYS_CLONE
|
||||
|
|
|
@ -795,3 +795,5 @@ __SYSCALL(__NR_getrandom, sys_getrandom)
|
|||
__SYSCALL(__NR_memfd_create, sys_memfd_create)
|
||||
#define __NR_bpf 386
|
||||
__SYSCALL(__NR_bpf, sys_bpf)
|
||||
#define __NR_execveat 387
|
||||
__SYSCALL(__NR_execveat, compat_sys_execveat)
|
||||
|
|
|
@ -335,14 +335,8 @@ static int keep_initrd;
|
|||
|
||||
void free_initrd_mem(unsigned long start, unsigned long end)
|
||||
{
|
||||
if (!keep_initrd) {
|
||||
if (start == initrd_start)
|
||||
start = round_down(start, PAGE_SIZE);
|
||||
if (end == initrd_end)
|
||||
end = round_up(end, PAGE_SIZE);
|
||||
|
||||
if (!keep_initrd)
|
||||
free_reserved_area((void *)start, (void *)end, 0, "initrd");
|
||||
}
|
||||
}
|
||||
|
||||
static int __init keepinitrd_setup(char *__unused)
|
||||
|
|
|
@ -4,7 +4,7 @@
|
|||
#include <uapi/asm/unistd.h>
|
||||
|
||||
|
||||
#define NR_syscalls 355
|
||||
#define NR_syscalls 356
|
||||
|
||||
#define __ARCH_WANT_OLD_READDIR
|
||||
#define __ARCH_WANT_OLD_STAT
|
||||
|
|
|
@ -360,5 +360,6 @@
|
|||
#define __NR_getrandom 352
|
||||
#define __NR_memfd_create 353
|
||||
#define __NR_bpf 354
|
||||
#define __NR_execveat 355
|
||||
|
||||
#endif /* _UAPI_ASM_M68K_UNISTD_H_ */
|
||||
|
|
|
@ -375,4 +375,5 @@ ENTRY(sys_call_table)
|
|||
.long sys_getrandom
|
||||
.long sys_memfd_create
|
||||
.long sys_bpf
|
||||
.long sys_execveat /* 355 */
|
||||
|
||||
|
|
|
@ -23,9 +23,9 @@
|
|||
#define THREAD_SIZE (1 << THREAD_SHIFT)
|
||||
|
||||
#ifdef CONFIG_PPC64
|
||||
#define CURRENT_THREAD_INFO(dest, sp) clrrdi dest, sp, THREAD_SHIFT
|
||||
#define CURRENT_THREAD_INFO(dest, sp) stringify_in_c(clrrdi dest, sp, THREAD_SHIFT)
|
||||
#else
|
||||
#define CURRENT_THREAD_INFO(dest, sp) rlwinm dest, sp, 0, 0, 31-THREAD_SHIFT
|
||||
#define CURRENT_THREAD_INFO(dest, sp) stringify_in_c(rlwinm dest, sp, 0, 0, 31-THREAD_SHIFT)
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
@ -71,12 +71,13 @@ struct thread_info {
|
|||
#define THREAD_SIZE_ORDER (THREAD_SHIFT - PAGE_SHIFT)
|
||||
|
||||
/* how to get the thread information struct from C */
|
||||
register unsigned long __current_r1 asm("r1");
|
||||
static inline struct thread_info *current_thread_info(void)
|
||||
{
|
||||
/* gcc4, at least, is smart enough to turn this into a single
|
||||
* rlwinm for ppc32 and clrrdi for ppc64 */
|
||||
return (struct thread_info *)(__current_r1 & ~(THREAD_SIZE-1));
|
||||
unsigned long val;
|
||||
|
||||
asm (CURRENT_THREAD_INFO(%0,1) : "=r" (val));
|
||||
|
||||
return (struct thread_info *)val;
|
||||
}
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
|
|
@ -40,7 +40,6 @@ BEGIN_FTR_SECTION; \
|
|||
b 1f; \
|
||||
END_FTR_SECTION(0, 1); \
|
||||
ld r12,opal_tracepoint_refcount@toc(r2); \
|
||||
std r12,32(r1); \
|
||||
cmpdi r12,0; \
|
||||
bne- LABEL; \
|
||||
1:
|
||||
|
|
|
@ -373,6 +373,8 @@ asmlinkage __visible void *decompress_kernel(void *rmode, memptr heap,
|
|||
unsigned long output_len,
|
||||
unsigned long run_size)
|
||||
{
|
||||
unsigned char *output_orig = output;
|
||||
|
||||
real_mode = rmode;
|
||||
|
||||
sanitize_boot_params(real_mode);
|
||||
|
@ -421,7 +423,12 @@ asmlinkage __visible void *decompress_kernel(void *rmode, memptr heap,
|
|||
debug_putstr("\nDecompressing Linux... ");
|
||||
decompress(input_data, input_len, NULL, NULL, output, NULL, error);
|
||||
parse_elf(output);
|
||||
handle_relocations(output, output_len);
|
||||
/*
|
||||
* 32-bit always performs relocations. 64-bit relocations are only
|
||||
* needed if kASLR has chosen a different load address.
|
||||
*/
|
||||
if (!IS_ENABLED(CONFIG_X86_64) || output != output_orig)
|
||||
handle_relocations(output, output_len);
|
||||
debug_putstr("done.\nBooting the kernel.\n");
|
||||
return output;
|
||||
}
|
||||
|
|
|
@ -50,6 +50,7 @@ void acpi_pic_sci_set_trigger(unsigned int, u16);
|
|||
|
||||
extern int (*__acpi_register_gsi)(struct device *dev, u32 gsi,
|
||||
int trigger, int polarity);
|
||||
extern void (*__acpi_unregister_gsi)(u32 gsi);
|
||||
|
||||
static inline void disable_acpi(void)
|
||||
{
|
||||
|
|
|
@ -251,7 +251,8 @@ static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
|
|||
gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
|
||||
}
|
||||
|
||||
#define _LDT_empty(info) \
|
||||
/* This intentionally ignores lm, since 32-bit apps don't have that field. */
|
||||
#define LDT_empty(info) \
|
||||
((info)->base_addr == 0 && \
|
||||
(info)->limit == 0 && \
|
||||
(info)->contents == 0 && \
|
||||
|
@ -261,11 +262,18 @@ static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
|
|||
(info)->seg_not_present == 1 && \
|
||||
(info)->useable == 0)
|
||||
|
||||
#ifdef CONFIG_X86_64
|
||||
#define LDT_empty(info) (_LDT_empty(info) && ((info)->lm == 0))
|
||||
#else
|
||||
#define LDT_empty(info) (_LDT_empty(info))
|
||||
#endif
|
||||
/* Lots of programs expect an all-zero user_desc to mean "no segment at all". */
|
||||
static inline bool LDT_zero(const struct user_desc *info)
|
||||
{
|
||||
return (info->base_addr == 0 &&
|
||||
info->limit == 0 &&
|
||||
info->contents == 0 &&
|
||||
info->read_exec_only == 0 &&
|
||||
info->seg_32bit == 0 &&
|
||||
info->limit_in_pages == 0 &&
|
||||
info->seg_not_present == 0 &&
|
||||
info->useable == 0);
|
||||
}
|
||||
|
||||
static inline void clear_LDT(void)
|
||||
{
|
||||
|
|
|
@ -130,7 +130,25 @@ static inline void arch_bprm_mm_init(struct mm_struct *mm,
|
|||
static inline void arch_unmap(struct mm_struct *mm, struct vm_area_struct *vma,
|
||||
unsigned long start, unsigned long end)
|
||||
{
|
||||
mpx_notify_unmap(mm, vma, start, end);
|
||||
/*
|
||||
* mpx_notify_unmap() goes and reads a rarely-hot
|
||||
* cacheline in the mm_struct. That can be expensive
|
||||
* enough to be seen in profiles.
|
||||
*
|
||||
* The mpx_notify_unmap() call and its contents have been
|
||||
* observed to affect munmap() performance on hardware
|
||||
* where MPX is not present.
|
||||
*
|
||||
* The unlikely() optimizes for the fast case: no MPX
|
||||
* in the CPU, or no MPX use in the process. Even if
|
||||
* we get this wrong (in the unlikely event that MPX
|
||||
* is widely enabled on some system) the overhead of
|
||||
* MPX itself (reading bounds tables) is expected to
|
||||
* overwhelm the overhead of getting this unlikely()
|
||||
* consistently wrong.
|
||||
*/
|
||||
if (unlikely(cpu_feature_enabled(X86_FEATURE_MPX)))
|
||||
mpx_notify_unmap(mm, vma, start, end);
|
||||
}
|
||||
|
||||
#endif /* _ASM_X86_MMU_CONTEXT_H */
|
||||
|
|
|
@ -611,20 +611,20 @@ void __init acpi_pic_sci_set_trigger(unsigned int irq, u16 trigger)
|
|||
|
||||
int acpi_gsi_to_irq(u32 gsi, unsigned int *irqp)
|
||||
{
|
||||
int irq;
|
||||
int rc, irq, trigger, polarity;
|
||||
|
||||
if (acpi_irq_model == ACPI_IRQ_MODEL_PIC) {
|
||||
*irqp = gsi;
|
||||
} else {
|
||||
mutex_lock(&acpi_ioapic_lock);
|
||||
irq = mp_map_gsi_to_irq(gsi,
|
||||
IOAPIC_MAP_ALLOC | IOAPIC_MAP_CHECK);
|
||||
mutex_unlock(&acpi_ioapic_lock);
|
||||
if (irq < 0)
|
||||
return -1;
|
||||
*irqp = irq;
|
||||
rc = acpi_get_override_irq(gsi, &trigger, &polarity);
|
||||
if (rc == 0) {
|
||||
trigger = trigger ? ACPI_LEVEL_SENSITIVE : ACPI_EDGE_SENSITIVE;
|
||||
polarity = polarity ? ACPI_ACTIVE_LOW : ACPI_ACTIVE_HIGH;
|
||||
irq = acpi_register_gsi(NULL, gsi, trigger, polarity);
|
||||
if (irq >= 0) {
|
||||
*irqp = irq;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
|
||||
return -1;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(acpi_gsi_to_irq);
|
||||
|
||||
|
|
|
@ -107,6 +107,7 @@ static struct clocksource hyperv_cs = {
|
|||
.rating = 400, /* use this when running on Hyperv*/
|
||||
.read = read_hv_clock,
|
||||
.mask = CLOCKSOURCE_MASK(64),
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
};
|
||||
|
||||
static void __init ms_hyperv_init_platform(void)
|
||||
|
|
|
@ -568,8 +568,8 @@ struct event_constraint intel_atom_pebs_event_constraints[] = {
|
|||
};
|
||||
|
||||
struct event_constraint intel_slm_pebs_event_constraints[] = {
|
||||
/* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
|
||||
INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
|
||||
/* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
|
||||
INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1),
|
||||
/* Allow all events as PEBS with no flags */
|
||||
INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
|
||||
EVENT_CONSTRAINT_END
|
||||
|
|
|
@ -103,6 +103,13 @@ static struct kobj_attribute format_attr_##_var = \
|
|||
|
||||
#define RAPL_CNTR_WIDTH 32 /* 32-bit rapl counters */
|
||||
|
||||
#define RAPL_EVENT_ATTR_STR(_name, v, str) \
|
||||
static struct perf_pmu_events_attr event_attr_##v = { \
|
||||
.attr = __ATTR(_name, 0444, rapl_sysfs_show, NULL), \
|
||||
.id = 0, \
|
||||
.event_str = str, \
|
||||
};
|
||||
|
||||
struct rapl_pmu {
|
||||
spinlock_t lock;
|
||||
int hw_unit; /* 1/2^hw_unit Joule */
|
||||
|
@ -379,23 +386,36 @@ static struct attribute_group rapl_pmu_attr_group = {
|
|||
.attrs = rapl_pmu_attrs,
|
||||
};
|
||||
|
||||
EVENT_ATTR_STR(energy-cores, rapl_cores, "event=0x01");
|
||||
EVENT_ATTR_STR(energy-pkg , rapl_pkg, "event=0x02");
|
||||
EVENT_ATTR_STR(energy-ram , rapl_ram, "event=0x03");
|
||||
EVENT_ATTR_STR(energy-gpu , rapl_gpu, "event=0x04");
|
||||
static ssize_t rapl_sysfs_show(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
char *page)
|
||||
{
|
||||
struct perf_pmu_events_attr *pmu_attr = \
|
||||
container_of(attr, struct perf_pmu_events_attr, attr);
|
||||
|
||||
EVENT_ATTR_STR(energy-cores.unit, rapl_cores_unit, "Joules");
|
||||
EVENT_ATTR_STR(energy-pkg.unit , rapl_pkg_unit, "Joules");
|
||||
EVENT_ATTR_STR(energy-ram.unit , rapl_ram_unit, "Joules");
|
||||
EVENT_ATTR_STR(energy-gpu.unit , rapl_gpu_unit, "Joules");
|
||||
if (pmu_attr->event_str)
|
||||
return sprintf(page, "%s", pmu_attr->event_str);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
RAPL_EVENT_ATTR_STR(energy-cores, rapl_cores, "event=0x01");
|
||||
RAPL_EVENT_ATTR_STR(energy-pkg , rapl_pkg, "event=0x02");
|
||||
RAPL_EVENT_ATTR_STR(energy-ram , rapl_ram, "event=0x03");
|
||||
RAPL_EVENT_ATTR_STR(energy-gpu , rapl_gpu, "event=0x04");
|
||||
|
||||
RAPL_EVENT_ATTR_STR(energy-cores.unit, rapl_cores_unit, "Joules");
|
||||
RAPL_EVENT_ATTR_STR(energy-pkg.unit , rapl_pkg_unit, "Joules");
|
||||
RAPL_EVENT_ATTR_STR(energy-ram.unit , rapl_ram_unit, "Joules");
|
||||
RAPL_EVENT_ATTR_STR(energy-gpu.unit , rapl_gpu_unit, "Joules");
|
||||
|
||||
/*
|
||||
* we compute in 0.23 nJ increments regardless of MSR
|
||||
*/
|
||||
EVENT_ATTR_STR(energy-cores.scale, rapl_cores_scale, "2.3283064365386962890625e-10");
|
||||
EVENT_ATTR_STR(energy-pkg.scale, rapl_pkg_scale, "2.3283064365386962890625e-10");
|
||||
EVENT_ATTR_STR(energy-ram.scale, rapl_ram_scale, "2.3283064365386962890625e-10");
|
||||
EVENT_ATTR_STR(energy-gpu.scale, rapl_gpu_scale, "2.3283064365386962890625e-10");
|
||||
RAPL_EVENT_ATTR_STR(energy-cores.scale, rapl_cores_scale, "2.3283064365386962890625e-10");
|
||||
RAPL_EVENT_ATTR_STR(energy-pkg.scale, rapl_pkg_scale, "2.3283064365386962890625e-10");
|
||||
RAPL_EVENT_ATTR_STR(energy-ram.scale, rapl_ram_scale, "2.3283064365386962890625e-10");
|
||||
RAPL_EVENT_ATTR_STR(energy-gpu.scale, rapl_gpu_scale, "2.3283064365386962890625e-10");
|
||||
|
||||
static struct attribute *rapl_events_srv_attr[] = {
|
||||
EVENT_PTR(rapl_cores),
|
||||
|
|
|
@ -127,7 +127,7 @@ int arch_show_interrupts(struct seq_file *p, int prec)
|
|||
seq_puts(p, " Machine check polls\n");
|
||||
#endif
|
||||
#if IS_ENABLED(CONFIG_HYPERV) || defined(CONFIG_XEN)
|
||||
seq_printf(p, "%*s: ", prec, "THR");
|
||||
seq_printf(p, "%*s: ", prec, "HYP");
|
||||
for_each_online_cpu(j)
|
||||
seq_printf(p, "%10u ", irq_stats(j)->irq_hv_callback_count);
|
||||
seq_puts(p, " Hypervisor callback interrupts\n");
|
||||
|
|
|
@ -1020,6 +1020,15 @@ int setjmp_pre_handler(struct kprobe *p, struct pt_regs *regs)
|
|||
regs->flags &= ~X86_EFLAGS_IF;
|
||||
trace_hardirqs_off();
|
||||
regs->ip = (unsigned long)(jp->entry);
|
||||
|
||||
/*
|
||||
* jprobes use jprobe_return() which skips the normal return
|
||||
* path of the function, and this messes up the accounting of the
|
||||
* function graph tracer to get messed up.
|
||||
*
|
||||
* Pause function graph tracing while performing the jprobe function.
|
||||
*/
|
||||
pause_graph_tracing();
|
||||
return 1;
|
||||
}
|
||||
NOKPROBE_SYMBOL(setjmp_pre_handler);
|
||||
|
@ -1048,24 +1057,25 @@ int longjmp_break_handler(struct kprobe *p, struct pt_regs *regs)
|
|||
struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
|
||||
u8 *addr = (u8 *) (regs->ip - 1);
|
||||
struct jprobe *jp = container_of(p, struct jprobe, kp);
|
||||
void *saved_sp = kcb->jprobe_saved_sp;
|
||||
|
||||
if ((addr > (u8 *) jprobe_return) &&
|
||||
(addr < (u8 *) jprobe_return_end)) {
|
||||
if (stack_addr(regs) != kcb->jprobe_saved_sp) {
|
||||
if (stack_addr(regs) != saved_sp) {
|
||||
struct pt_regs *saved_regs = &kcb->jprobe_saved_regs;
|
||||
printk(KERN_ERR
|
||||
"current sp %p does not match saved sp %p\n",
|
||||
stack_addr(regs), kcb->jprobe_saved_sp);
|
||||
stack_addr(regs), saved_sp);
|
||||
printk(KERN_ERR "Saved registers for jprobe %p\n", jp);
|
||||
show_regs(saved_regs);
|
||||
printk(KERN_ERR "Current registers\n");
|
||||
show_regs(regs);
|
||||
BUG();
|
||||
}
|
||||
/* It's OK to start function graph tracing again */
|
||||
unpause_graph_tracing();
|
||||
*regs = kcb->jprobe_saved_regs;
|
||||
memcpy((kprobe_opcode_t *)(kcb->jprobe_saved_sp),
|
||||
kcb->jprobes_stack,
|
||||
MIN_STACK_SIZE(kcb->jprobe_saved_sp));
|
||||
memcpy(saved_sp, kcb->jprobes_stack, MIN_STACK_SIZE(saved_sp));
|
||||
preempt_enable_no_resched();
|
||||
return 1;
|
||||
}
|
||||
|
|
|
@ -29,7 +29,28 @@ static int get_free_idx(void)
|
|||
|
||||
static bool tls_desc_okay(const struct user_desc *info)
|
||||
{
|
||||
if (LDT_empty(info))
|
||||
/*
|
||||
* For historical reasons (i.e. no one ever documented how any
|
||||
* of the segmentation APIs work), user programs can and do
|
||||
* assume that a struct user_desc that's all zeros except for
|
||||
* entry_number means "no segment at all". This never actually
|
||||
* worked. In fact, up to Linux 3.19, a struct user_desc like
|
||||
* this would create a 16-bit read-write segment with base and
|
||||
* limit both equal to zero.
|
||||
*
|
||||
* That was close enough to "no segment at all" until we
|
||||
* hardened this function to disallow 16-bit TLS segments. Fix
|
||||
* it up by interpreting these zeroed segments the way that they
|
||||
* were almost certainly intended to be interpreted.
|
||||
*
|
||||
* The correct way to ask for "no segment at all" is to specify
|
||||
* a user_desc that satisfies LDT_empty. To keep everything
|
||||
* working, we accept both.
|
||||
*
|
||||
* Note that there's a similar kludge in modify_ldt -- look at
|
||||
* the distinction between modes 1 and 0x11.
|
||||
*/
|
||||
if (LDT_empty(info) || LDT_zero(info))
|
||||
return true;
|
||||
|
||||
/*
|
||||
|
@ -71,7 +92,7 @@ static void set_tls_desc(struct task_struct *p, int idx,
|
|||
cpu = get_cpu();
|
||||
|
||||
while (n-- > 0) {
|
||||
if (LDT_empty(info))
|
||||
if (LDT_empty(info) || LDT_zero(info))
|
||||
desc->a = desc->b = 0;
|
||||
else
|
||||
fill_ldt(desc, info);
|
||||
|
|
|
@ -348,6 +348,12 @@ static __user void *task_get_bounds_dir(struct task_struct *tsk)
|
|||
if (!cpu_feature_enabled(X86_FEATURE_MPX))
|
||||
return MPX_INVALID_BOUNDS_DIR;
|
||||
|
||||
/*
|
||||
* 32-bit binaries on 64-bit kernels are currently
|
||||
* unsupported.
|
||||
*/
|
||||
if (IS_ENABLED(CONFIG_X86_64) && test_thread_flag(TIF_IA32))
|
||||
return MPX_INVALID_BOUNDS_DIR;
|
||||
/*
|
||||
* The bounds directory pointer is stored in a register
|
||||
* only accessible if we first do an xsave.
|
||||
|
|
|
@ -234,8 +234,13 @@ void pat_init(void)
|
|||
PAT(4, WB) | PAT(5, WC) | PAT(6, UC_MINUS) | PAT(7, UC);
|
||||
|
||||
/* Boot CPU check */
|
||||
if (!boot_pat_state)
|
||||
if (!boot_pat_state) {
|
||||
rdmsrl(MSR_IA32_CR_PAT, boot_pat_state);
|
||||
if (!boot_pat_state) {
|
||||
pat_disable("PAT read returns always zero, disabled.");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
wrmsrl(MSR_IA32_CR_PAT, pat);
|
||||
|
||||
|
|
|
@ -458,6 +458,7 @@ int __init pci_xen_hvm_init(void)
|
|||
* just how GSIs get registered.
|
||||
*/
|
||||
__acpi_register_gsi = acpi_register_gsi_xen_hvm;
|
||||
__acpi_unregister_gsi = NULL;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_MSI
|
||||
|
@ -471,52 +472,6 @@ int __init pci_xen_hvm_init(void)
|
|||
}
|
||||
|
||||
#ifdef CONFIG_XEN_DOM0
|
||||
static __init void xen_setup_acpi_sci(void)
|
||||
{
|
||||
int rc;
|
||||
int trigger, polarity;
|
||||
int gsi = acpi_sci_override_gsi;
|
||||
int irq = -1;
|
||||
int gsi_override = -1;
|
||||
|
||||
if (!gsi)
|
||||
return;
|
||||
|
||||
rc = acpi_get_override_irq(gsi, &trigger, &polarity);
|
||||
if (rc) {
|
||||
printk(KERN_WARNING "xen: acpi_get_override_irq failed for acpi"
|
||||
" sci, rc=%d\n", rc);
|
||||
return;
|
||||
}
|
||||
trigger = trigger ? ACPI_LEVEL_SENSITIVE : ACPI_EDGE_SENSITIVE;
|
||||
polarity = polarity ? ACPI_ACTIVE_LOW : ACPI_ACTIVE_HIGH;
|
||||
|
||||
printk(KERN_INFO "xen: sci override: global_irq=%d trigger=%d "
|
||||
"polarity=%d\n", gsi, trigger, polarity);
|
||||
|
||||
/* Before we bind the GSI to a Linux IRQ, check whether
|
||||
* we need to override it with bus_irq (IRQ) value. Usually for
|
||||
* IRQs below IRQ_LEGACY_IRQ this holds IRQ == GSI, as so:
|
||||
* ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level)
|
||||
* but there are oddballs where the IRQ != GSI:
|
||||
* ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 20 low level)
|
||||
* which ends up being: gsi_to_irq[9] == 20
|
||||
* (which is what acpi_gsi_to_irq ends up calling when starting the
|
||||
* the ACPI interpreter and keels over since IRQ 9 has not been
|
||||
* setup as we had setup IRQ 20 for it).
|
||||
*/
|
||||
if (acpi_gsi_to_irq(gsi, &irq) == 0) {
|
||||
/* Use the provided value if it's valid. */
|
||||
if (irq >= 0)
|
||||
gsi_override = irq;
|
||||
}
|
||||
|
||||
gsi = xen_register_gsi(gsi, gsi_override, trigger, polarity);
|
||||
printk(KERN_INFO "xen: acpi sci %d\n", gsi);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
int __init pci_xen_initial_domain(void)
|
||||
{
|
||||
int irq;
|
||||
|
@ -527,8 +482,8 @@ int __init pci_xen_initial_domain(void)
|
|||
x86_msi.restore_msi_irqs = xen_initdom_restore_msi_irqs;
|
||||
pci_msi_ignore_mask = 1;
|
||||
#endif
|
||||
xen_setup_acpi_sci();
|
||||
__acpi_register_gsi = acpi_register_gsi_xen;
|
||||
__acpi_unregister_gsi = NULL;
|
||||
/* Pre-allocate legacy irqs */
|
||||
for (irq = 0; irq < nr_legacy_irqs(); irq++) {
|
||||
int trigger, polarity;
|
||||
|
|
|
@ -512,7 +512,6 @@ void acpi_pci_irq_disable(struct pci_dev *dev)
|
|||
dev_dbg(&dev->dev, "PCI INT %c disabled\n", pin_name(pin));
|
||||
if (gsi >= 0) {
|
||||
acpi_unregister_gsi(gsi);
|
||||
dev->irq = 0;
|
||||
dev->irq_managed = 0;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -1312,6 +1312,9 @@ static int cci_probe(void)
|
|||
if (!np)
|
||||
return -ENODEV;
|
||||
|
||||
if (!of_device_is_available(np))
|
||||
return -ENODEV;
|
||||
|
||||
cci_config = of_match_node(arm_cci_matches, np)->data;
|
||||
if (!cci_config)
|
||||
return -ENODEV;
|
||||
|
|
|
@ -70,6 +70,7 @@ struct clk_sam9x5_slow {
|
|||
|
||||
#define to_clk_sam9x5_slow(hw) container_of(hw, struct clk_sam9x5_slow, hw)
|
||||
|
||||
static struct clk *slow_clk;
|
||||
|
||||
static int clk_slow_osc_prepare(struct clk_hw *hw)
|
||||
{
|
||||
|
@ -357,6 +358,8 @@ at91_clk_register_sam9x5_slow(void __iomem *sckcr,
|
|||
clk = clk_register(NULL, &slowck->hw);
|
||||
if (IS_ERR(clk))
|
||||
kfree(slowck);
|
||||
else
|
||||
slow_clk = clk;
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
@ -433,6 +436,8 @@ at91_clk_register_sam9260_slow(struct at91_pmc *pmc,
|
|||
clk = clk_register(NULL, &slowck->hw);
|
||||
if (IS_ERR(clk))
|
||||
kfree(slowck);
|
||||
else
|
||||
slow_clk = clk;
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
@ -465,3 +470,25 @@ void __init of_at91sam9260_clk_slow_setup(struct device_node *np,
|
|||
|
||||
of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
||||
}
|
||||
|
||||
/*
|
||||
* FIXME: All slow clk users are not properly claiming it (get + prepare +
|
||||
* enable) before using it.
|
||||
* If all users properly claiming this clock decide that they don't need it
|
||||
* anymore (or are removed), it is disabled while faulty users are still
|
||||
* requiring it, and the system hangs.
|
||||
* Prevent this clock from being disabled until all users are properly
|
||||
* requesting it.
|
||||
* Once this is done we should remove this function and the slow_clk variable.
|
||||
*/
|
||||
static int __init of_at91_clk_slow_retain(void)
|
||||
{
|
||||
if (!slow_clk)
|
||||
return 0;
|
||||
|
||||
__clk_get(slow_clk);
|
||||
clk_prepare_enable(slow_clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(of_at91_clk_slow_retain);
|
||||
|
|
|
@ -285,7 +285,6 @@ static const struct berlin2_gate_data bg2q_gates[] __initconst = {
|
|||
{ "pbridge", "perif", 15, CLK_IGNORE_UNUSED },
|
||||
{ "sdio", "perif", 16, CLK_IGNORE_UNUSED },
|
||||
{ "nfc", "perif", 18 },
|
||||
{ "smemc", "perif", 19 },
|
||||
{ "pcie", "perif", 22 },
|
||||
};
|
||||
|
||||
|
|
|
@ -291,7 +291,7 @@ static const struct of_device_id ppc_clk_ids[] __initconst = {
|
|||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver ppc_corenet_clk_driver __initdata = {
|
||||
static struct platform_driver ppc_corenet_clk_driver = {
|
||||
.driver = {
|
||||
.name = "ppc_corenet_clock",
|
||||
.of_match_table = ppc_clk_ids,
|
||||
|
|
|
@ -1366,7 +1366,7 @@ static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
|
|||
new_rate = clk->ops->determine_rate(clk->hw, rate,
|
||||
&best_parent_rate,
|
||||
&parent_hw);
|
||||
parent = parent_hw->clk;
|
||||
parent = parent_hw ? parent_hw->clk : NULL;
|
||||
} else if (clk->ops->round_rate) {
|
||||
new_rate = clk->ops->round_rate(clk->hw, rate,
|
||||
&best_parent_rate);
|
||||
|
|
|
@ -124,10 +124,11 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
|
|||
{
|
||||
const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
|
||||
unsigned long alt_prate, alt_div;
|
||||
unsigned long flags;
|
||||
|
||||
alt_prate = clk_get_rate(cpuclk->alt_parent);
|
||||
|
||||
spin_lock(cpuclk->lock);
|
||||
spin_lock_irqsave(cpuclk->lock, flags);
|
||||
|
||||
/*
|
||||
* If the old parent clock speed is less than the clock speed
|
||||
|
@ -164,7 +165,7 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
|
|||
cpuclk->reg_base + reg_data->core_reg);
|
||||
}
|
||||
|
||||
spin_unlock(cpuclk->lock);
|
||||
spin_unlock_irqrestore(cpuclk->lock, flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -173,6 +174,7 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,
|
|||
{
|
||||
const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
|
||||
const struct rockchip_cpuclk_rate_table *rate;
|
||||
unsigned long flags;
|
||||
|
||||
rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);
|
||||
if (!rate) {
|
||||
|
@ -181,7 +183,7 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
spin_lock(cpuclk->lock);
|
||||
spin_lock_irqsave(cpuclk->lock, flags);
|
||||
|
||||
if (ndata->old_rate < ndata->new_rate)
|
||||
rockchip_cpuclk_set_dividers(cpuclk, rate);
|
||||
|
@ -201,7 +203,7 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,
|
|||
if (ndata->old_rate > ndata->new_rate)
|
||||
rockchip_cpuclk_set_dividers(cpuclk, rate);
|
||||
|
||||
spin_unlock(cpuclk->lock);
|
||||
spin_unlock_irqrestore(cpuclk->lock, flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -210,6 +210,17 @@ PNAME(mux_sclk_hsadc_p) = { "hsadc_src", "hsadc_frac", "ext_hsadc" };
|
|||
PNAME(mux_mac_p) = { "gpll", "dpll" };
|
||||
PNAME(mux_sclk_macref_p) = { "mac_src", "ext_rmii" };
|
||||
|
||||
static struct rockchip_pll_clock rk3066_pll_clks[] __initdata = {
|
||||
[apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
|
||||
RK2928_MODE_CON, 0, 5, 0, rk3188_pll_rates),
|
||||
[dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
|
||||
RK2928_MODE_CON, 4, 4, 0, NULL),
|
||||
[cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
|
||||
RK2928_MODE_CON, 8, 6, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
|
||||
[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
|
||||
RK2928_MODE_CON, 12, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
|
||||
};
|
||||
|
||||
static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = {
|
||||
[apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
|
||||
RK2928_MODE_CON, 0, 6, 0, rk3188_pll_rates),
|
||||
|
@ -427,11 +438,11 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
|
|||
/* hclk_peri gates */
|
||||
GATE(0, "hclk_peri_axi_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
|
||||
GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 6, GFLAGS),
|
||||
GATE(0, "hclk_emem_peri", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 7, GFLAGS),
|
||||
GATE(0, "hclk_emem_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 7, GFLAGS),
|
||||
GATE(HCLK_EMAC, "hclk_emac", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
|
||||
GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
|
||||
GATE(0, "hclk_usb_peri", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 5, GFLAGS),
|
||||
GATE(HCLK_OTG0, "hclk_usbotg0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 13, GFLAGS),
|
||||
GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 5, GFLAGS),
|
||||
GATE(HCLK_OTG0, "hclk_usbotg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS),
|
||||
GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 5, GFLAGS),
|
||||
GATE(HCLK_PIDF, "hclk_pidfilter", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 6, GFLAGS),
|
||||
GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS),
|
||||
|
@ -592,7 +603,8 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
|
|||
GATE(0, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS),
|
||||
GATE(0, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
|
||||
|
||||
GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS),
|
||||
GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(5), 14, GFLAGS),
|
||||
|
||||
GATE(0, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS),
|
||||
|
||||
|
@ -680,7 +692,8 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
|
|||
GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
|
||||
GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS),
|
||||
|
||||
GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
|
||||
GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(7), 3, GFLAGS),
|
||||
GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
|
||||
|
||||
GATE(PCLK_TIMER3, "pclk_timer3", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS),
|
||||
|
@ -735,8 +748,8 @@ static void __init rk3188_common_clk_init(struct device_node *np)
|
|||
static void __init rk3066a_clk_init(struct device_node *np)
|
||||
{
|
||||
rk3188_common_clk_init(np);
|
||||
rockchip_clk_register_plls(rk3188_pll_clks,
|
||||
ARRAY_SIZE(rk3188_pll_clks),
|
||||
rockchip_clk_register_plls(rk3066_pll_clks,
|
||||
ARRAY_SIZE(rk3066_pll_clks),
|
||||
RK3066_GRF_SOC_STATUS);
|
||||
rockchip_clk_register_branches(rk3066a_clk_branches,
|
||||
ARRAY_SIZE(rk3066a_clk_branches));
|
||||
|
|
|
@ -145,20 +145,20 @@ struct rockchip_pll_rate_table rk3288_pll_rates[] = {
|
|||
}
|
||||
|
||||
static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = {
|
||||
RK3288_CPUCLK_RATE(1800000000, 2, 4, 2, 4, 4),
|
||||
RK3288_CPUCLK_RATE(1704000000, 2, 4, 2, 4, 4),
|
||||
RK3288_CPUCLK_RATE(1608000000, 2, 4, 2, 4, 4),
|
||||
RK3288_CPUCLK_RATE(1512000000, 2, 4, 2, 4, 4),
|
||||
RK3288_CPUCLK_RATE(1416000000, 2, 4, 2, 4, 4),
|
||||
RK3288_CPUCLK_RATE(1200000000, 2, 4, 2, 4, 4),
|
||||
RK3288_CPUCLK_RATE(1008000000, 2, 4, 2, 4, 4),
|
||||
RK3288_CPUCLK_RATE( 816000000, 2, 4, 2, 4, 4),
|
||||
RK3288_CPUCLK_RATE( 696000000, 2, 4, 2, 4, 4),
|
||||
RK3288_CPUCLK_RATE( 600000000, 2, 4, 2, 4, 4),
|
||||
RK3288_CPUCLK_RATE( 408000000, 2, 4, 2, 4, 4),
|
||||
RK3288_CPUCLK_RATE( 312000000, 2, 4, 2, 4, 4),
|
||||
RK3288_CPUCLK_RATE( 216000000, 2, 4, 2, 4, 4),
|
||||
RK3288_CPUCLK_RATE( 126000000, 2, 4, 2, 4, 4),
|
||||
RK3288_CPUCLK_RATE(1800000000, 1, 3, 1, 3, 3),
|
||||
RK3288_CPUCLK_RATE(1704000000, 1, 3, 1, 3, 3),
|
||||
RK3288_CPUCLK_RATE(1608000000, 1, 3, 1, 3, 3),
|
||||
RK3288_CPUCLK_RATE(1512000000, 1, 3, 1, 3, 3),
|
||||
RK3288_CPUCLK_RATE(1416000000, 1, 3, 1, 3, 3),
|
||||
RK3288_CPUCLK_RATE(1200000000, 1, 3, 1, 3, 3),
|
||||
RK3288_CPUCLK_RATE(1008000000, 1, 3, 1, 3, 3),
|
||||
RK3288_CPUCLK_RATE( 816000000, 1, 3, 1, 3, 3),
|
||||
RK3288_CPUCLK_RATE( 696000000, 1, 3, 1, 3, 3),
|
||||
RK3288_CPUCLK_RATE( 600000000, 1, 3, 1, 3, 3),
|
||||
RK3288_CPUCLK_RATE( 408000000, 1, 3, 1, 3, 3),
|
||||
RK3288_CPUCLK_RATE( 312000000, 1, 3, 1, 3, 3),
|
||||
RK3288_CPUCLK_RATE( 216000000, 1, 3, 1, 3, 3),
|
||||
RK3288_CPUCLK_RATE( 126000000, 1, 3, 1, 3, 3),
|
||||
};
|
||||
|
||||
static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = {
|
||||
|
|
|
@ -1505,7 +1505,6 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
|
|||
dw->regs = chip->regs;
|
||||
chip->dw = dw;
|
||||
|
||||
pm_runtime_enable(chip->dev);
|
||||
pm_runtime_get_sync(chip->dev);
|
||||
|
||||
dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
|
||||
|
@ -1703,7 +1702,6 @@ int dw_dma_remove(struct dw_dma_chip *chip)
|
|||
}
|
||||
|
||||
pm_runtime_put_sync_suspend(chip->dev);
|
||||
pm_runtime_disable(chip->dev);
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(dw_dma_remove);
|
||||
|
|
|
@ -15,6 +15,7 @@
|
|||
#include <linux/module.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
|
@ -185,6 +186,8 @@ static int dw_probe(struct platform_device *pdev)
|
|||
if (err)
|
||||
return err;
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
|
||||
err = dw_dma_probe(chip, pdata);
|
||||
if (err)
|
||||
goto err_dw_dma_probe;
|
||||
|
@ -205,6 +208,7 @@ static int dw_probe(struct platform_device *pdev)
|
|||
return 0;
|
||||
|
||||
err_dw_dma_probe:
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
clk_disable_unprepare(chip->clk);
|
||||
return err;
|
||||
}
|
||||
|
@ -217,6 +221,7 @@ static int dw_remove(struct platform_device *pdev)
|
|||
of_dma_controller_free(pdev->dev.of_node);
|
||||
|
||||
dw_dma_remove(chip);
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
clk_disable_unprepare(chip->clk);
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -143,9 +143,15 @@ static int ad799x_write_config(struct ad799x_state *st, u16 val)
|
|||
case ad7998:
|
||||
return i2c_smbus_write_word_swapped(st->client, AD7998_CONF_REG,
|
||||
val);
|
||||
default:
|
||||
case ad7992:
|
||||
case ad7993:
|
||||
case ad7994:
|
||||
return i2c_smbus_write_byte_data(st->client, AD7998_CONF_REG,
|
||||
val);
|
||||
default:
|
||||
/* Will be written when doing a conversion */
|
||||
st->config = val;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -155,8 +161,13 @@ static int ad799x_read_config(struct ad799x_state *st)
|
|||
case ad7997:
|
||||
case ad7998:
|
||||
return i2c_smbus_read_word_swapped(st->client, AD7998_CONF_REG);
|
||||
default:
|
||||
case ad7992:
|
||||
case ad7993:
|
||||
case ad7994:
|
||||
return i2c_smbus_read_byte_data(st->client, AD7998_CONF_REG);
|
||||
default:
|
||||
/* No readback support */
|
||||
return st->config;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -449,6 +449,9 @@ static int iio_channel_read(struct iio_channel *chan, int *val, int *val2,
|
|||
if (val2 == NULL)
|
||||
val2 = &unused;
|
||||
|
||||
if(!iio_channel_has_info(chan->channel, info))
|
||||
return -EINVAL;
|
||||
|
||||
if (chan->indio_dev->info->read_raw_multi) {
|
||||
ret = chan->indio_dev->info->read_raw_multi(chan->indio_dev,
|
||||
chan->channel, INDIO_MAX_RAW_ELEMENTS,
|
||||
|
|
|
@ -7,6 +7,7 @@
|
|||
#define PCI_DEVICE_ID_MEN_CHAMELEON 0x4d45
|
||||
#define CHAMELEON_FILENAME_LEN 12
|
||||
#define CHAMELEONV2_MAGIC 0xabce
|
||||
#define CHAM_HEADER_SIZE 0x200
|
||||
|
||||
enum chameleon_descriptor_type {
|
||||
CHAMELEON_DTYPE_GENERAL = 0x0,
|
||||
|
|
|
@ -17,6 +17,7 @@
|
|||
|
||||
struct priv {
|
||||
struct mcb_bus *bus;
|
||||
phys_addr_t mapbase;
|
||||
void __iomem *base;
|
||||
};
|
||||
|
||||
|
@ -31,8 +32,8 @@ static int mcb_pci_get_irq(struct mcb_device *mdev)
|
|||
|
||||
static int mcb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
||||
{
|
||||
struct resource *res;
|
||||
struct priv *priv;
|
||||
phys_addr_t mapbase;
|
||||
int ret;
|
||||
int num_cells;
|
||||
unsigned long flags;
|
||||
|
@ -47,19 +48,21 @@ static int mcb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
return -ENODEV;
|
||||
}
|
||||
|
||||
mapbase = pci_resource_start(pdev, 0);
|
||||
if (!mapbase) {
|
||||
priv->mapbase = pci_resource_start(pdev, 0);
|
||||
if (!priv->mapbase) {
|
||||
dev_err(&pdev->dev, "No PCI resource\n");
|
||||
goto err_start;
|
||||
}
|
||||
|
||||
ret = pci_request_region(pdev, 0, KBUILD_MODNAME);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to request PCI BARs\n");
|
||||
res = request_mem_region(priv->mapbase, CHAM_HEADER_SIZE,
|
||||
KBUILD_MODNAME);
|
||||
if (IS_ERR(res)) {
|
||||
dev_err(&pdev->dev, "Failed to request PCI memory\n");
|
||||
ret = PTR_ERR(res);
|
||||
goto err_start;
|
||||
}
|
||||
|
||||
priv->base = pci_iomap(pdev, 0, 0);
|
||||
priv->base = ioremap(priv->mapbase, CHAM_HEADER_SIZE);
|
||||
if (!priv->base) {
|
||||
dev_err(&pdev->dev, "Cannot ioremap\n");
|
||||
ret = -ENOMEM;
|
||||
|
@ -84,7 +87,7 @@ static int mcb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
|
||||
priv->bus->get_irq = mcb_pci_get_irq;
|
||||
|
||||
ret = chameleon_parse_cells(priv->bus, mapbase, priv->base);
|
||||
ret = chameleon_parse_cells(priv->bus, priv->mapbase, priv->base);
|
||||
if (ret < 0)
|
||||
goto err_drvdata;
|
||||
num_cells = ret;
|
||||
|
@ -93,8 +96,10 @@ static int mcb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
|
||||
mcb_bus_add_devices(priv->bus);
|
||||
|
||||
return 0;
|
||||
|
||||
err_drvdata:
|
||||
pci_iounmap(pdev, priv->base);
|
||||
iounmap(priv->base);
|
||||
err_ioremap:
|
||||
pci_release_region(pdev, 0);
|
||||
err_start:
|
||||
|
@ -107,6 +112,10 @@ static void mcb_pci_remove(struct pci_dev *pdev)
|
|||
struct priv *priv = pci_get_drvdata(pdev);
|
||||
|
||||
mcb_release_bus(priv->bus);
|
||||
|
||||
iounmap(priv->base);
|
||||
release_region(priv->mapbase, CHAM_HEADER_SIZE);
|
||||
pci_disable_device(pdev);
|
||||
}
|
||||
|
||||
static const struct pci_device_id mcb_pci_tbl[] = {
|
||||
|
|
|
@ -100,6 +100,46 @@ int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int cxl_mmap_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
|
||||
{
|
||||
struct cxl_context *ctx = vma->vm_file->private_data;
|
||||
unsigned long address = (unsigned long)vmf->virtual_address;
|
||||
u64 area, offset;
|
||||
|
||||
offset = vmf->pgoff << PAGE_SHIFT;
|
||||
|
||||
pr_devel("%s: pe: %i address: 0x%lx offset: 0x%llx\n",
|
||||
__func__, ctx->pe, address, offset);
|
||||
|
||||
if (ctx->afu->current_mode == CXL_MODE_DEDICATED) {
|
||||
area = ctx->afu->psn_phys;
|
||||
if (offset > ctx->afu->adapter->ps_size)
|
||||
return VM_FAULT_SIGBUS;
|
||||
} else {
|
||||
area = ctx->psn_phys;
|
||||
if (offset > ctx->psn_size)
|
||||
return VM_FAULT_SIGBUS;
|
||||
}
|
||||
|
||||
mutex_lock(&ctx->status_mutex);
|
||||
|
||||
if (ctx->status != STARTED) {
|
||||
mutex_unlock(&ctx->status_mutex);
|
||||
pr_devel("%s: Context not started, failing problem state access\n", __func__);
|
||||
return VM_FAULT_SIGBUS;
|
||||
}
|
||||
|
||||
vm_insert_pfn(vma, address, (area + offset) >> PAGE_SHIFT);
|
||||
|
||||
mutex_unlock(&ctx->status_mutex);
|
||||
|
||||
return VM_FAULT_NOPAGE;
|
||||
}
|
||||
|
||||
static const struct vm_operations_struct cxl_mmap_vmops = {
|
||||
.fault = cxl_mmap_fault,
|
||||
};
|
||||
|
||||
/*
|
||||
* Map a per-context mmio space into the given vma.
|
||||
*/
|
||||
|
@ -108,26 +148,25 @@ int cxl_context_iomap(struct cxl_context *ctx, struct vm_area_struct *vma)
|
|||
u64 len = vma->vm_end - vma->vm_start;
|
||||
len = min(len, ctx->psn_size);
|
||||
|
||||
if (ctx->afu->current_mode == CXL_MODE_DEDICATED) {
|
||||
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
|
||||
return vm_iomap_memory(vma, ctx->afu->psn_phys, ctx->afu->adapter->ps_size);
|
||||
}
|
||||
if (ctx->afu->current_mode != CXL_MODE_DEDICATED) {
|
||||
/* make sure there is a valid per process space for this AFU */
|
||||
if ((ctx->master && !ctx->afu->psa) || (!ctx->afu->pp_psa)) {
|
||||
pr_devel("AFU doesn't support mmio space\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* make sure there is a valid per process space for this AFU */
|
||||
if ((ctx->master && !ctx->afu->psa) || (!ctx->afu->pp_psa)) {
|
||||
pr_devel("AFU doesn't support mmio space\n");
|
||||
return -EINVAL;
|
||||
/* Can't mmap until the AFU is enabled */
|
||||
if (!ctx->afu->enabled)
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
/* Can't mmap until the AFU is enabled */
|
||||
if (!ctx->afu->enabled)
|
||||
return -EBUSY;
|
||||
|
||||
pr_devel("%s: mmio physical: %llx pe: %i master:%i\n", __func__,
|
||||
ctx->psn_phys, ctx->pe , ctx->master);
|
||||
|
||||
vma->vm_flags |= VM_IO | VM_PFNMAP;
|
||||
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
|
||||
return vm_iomap_memory(vma, ctx->psn_phys, len);
|
||||
vma->vm_ops = &cxl_mmap_vmops;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -150,12 +189,6 @@ static void __detach_context(struct cxl_context *ctx)
|
|||
afu_release_irqs(ctx);
|
||||
flush_work(&ctx->fault_work); /* Only needed for dedicated process */
|
||||
wake_up_all(&ctx->wq);
|
||||
|
||||
/* Release Problem State Area mapping */
|
||||
mutex_lock(&ctx->mapping_lock);
|
||||
if (ctx->mapping)
|
||||
unmap_mapping_range(ctx->mapping, 0, 0, 1);
|
||||
mutex_unlock(&ctx->mapping_lock);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -184,6 +217,17 @@ void cxl_context_detach_all(struct cxl_afu *afu)
|
|||
* created and torn down after the IDR removed
|
||||
*/
|
||||
__detach_context(ctx);
|
||||
|
||||
/*
|
||||
* We are force detaching - remove any active PSA mappings so
|
||||
* userspace cannot interfere with the card if it comes back.
|
||||
* Easiest way to exercise this is to unbind and rebind the
|
||||
* driver via sysfs while it is in use.
|
||||
*/
|
||||
mutex_lock(&ctx->mapping_lock);
|
||||
if (ctx->mapping)
|
||||
unmap_mapping_range(ctx->mapping, 0, 0, 1);
|
||||
mutex_unlock(&ctx->mapping_lock);
|
||||
}
|
||||
mutex_unlock(&afu->contexts_lock);
|
||||
}
|
||||
|
|
|
@ -140,18 +140,20 @@ static long afu_ioctl_start_work(struct cxl_context *ctx,
|
|||
|
||||
pr_devel("%s: pe: %i\n", __func__, ctx->pe);
|
||||
|
||||
mutex_lock(&ctx->status_mutex);
|
||||
if (ctx->status != OPENED) {
|
||||
rc = -EIO;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Do this outside the status_mutex to avoid a circular dependency with
|
||||
* the locking in cxl_mmap_fault() */
|
||||
if (copy_from_user(&work, uwork,
|
||||
sizeof(struct cxl_ioctl_start_work))) {
|
||||
rc = -EFAULT;
|
||||
goto out;
|
||||
}
|
||||
|
||||
mutex_lock(&ctx->status_mutex);
|
||||
if (ctx->status != OPENED) {
|
||||
rc = -EIO;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/*
|
||||
* if any of the reserved fields are set or any of the unused
|
||||
* flags are set it's invalid
|
||||
|
|
|
@ -234,6 +234,18 @@ static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
|
|||
struct mei_me_hw *hw = to_me_hw(dev);
|
||||
u32 hcsr = mei_hcsr_read(hw);
|
||||
|
||||
/* H_RST may be found lit before reset is started,
|
||||
* for example if preceding reset flow hasn't completed.
|
||||
* In that case asserting H_RST will be ignored, therefore
|
||||
* we need to clean H_RST bit to start a successful reset sequence.
|
||||
*/
|
||||
if ((hcsr & H_RST) == H_RST) {
|
||||
dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr);
|
||||
hcsr &= ~H_RST;
|
||||
mei_me_reg_write(hw, H_CSR, hcsr);
|
||||
hcsr = mei_hcsr_read(hw);
|
||||
}
|
||||
|
||||
hcsr |= H_RST | H_IG | H_IS;
|
||||
|
||||
if (intr_enable)
|
||||
|
|
|
@ -1271,6 +1271,12 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
|
|||
spin_unlock_irq(&host->lock);
|
||||
mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
|
||||
spin_lock_irq(&host->lock);
|
||||
|
||||
if (mode != MMC_POWER_OFF)
|
||||
sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
|
||||
else
|
||||
sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
|
@ -1050,7 +1050,8 @@ static int miphy28lp_init(struct phy *phy)
|
|||
ret = miphy28lp_init_usb3(miphy_phy);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
mutex_unlock(&miphy_dev->miphy_mutex);
|
||||
|
|
|
@ -29,10 +29,9 @@
|
|||
/**
|
||||
* omap_control_pcie_pcs - set the PCS delay count
|
||||
* @dev: the control module device
|
||||
* @id: index of the pcie PHY (should be 1 or 2)
|
||||
* @delay: 8 bit delay value
|
||||
*/
|
||||
void omap_control_pcie_pcs(struct device *dev, u8 id, u8 delay)
|
||||
void omap_control_pcie_pcs(struct device *dev, u8 delay)
|
||||
{
|
||||
u32 val;
|
||||
struct omap_control_phy *control_phy;
|
||||
|
@ -55,8 +54,8 @@ void omap_control_pcie_pcs(struct device *dev, u8 id, u8 delay)
|
|||
|
||||
val = readl(control_phy->pcie_pcs);
|
||||
val &= ~(OMAP_CTRL_PCIE_PCS_MASK <<
|
||||
(id * OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT));
|
||||
val |= delay << (id * OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT);
|
||||
OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT);
|
||||
val |= (delay << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT);
|
||||
writel(val, control_phy->pcie_pcs);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(omap_control_pcie_pcs);
|
||||
|
|
|
@ -244,7 +244,8 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
|
|||
else
|
||||
data->num_phys = 3;
|
||||
|
||||
if (of_device_is_compatible(np, "allwinner,sun4i-a10-usb-phy"))
|
||||
if (of_device_is_compatible(np, "allwinner,sun4i-a10-usb-phy") ||
|
||||
of_device_is_compatible(np, "allwinner,sun6i-a31-usb-phy"))
|
||||
data->disc_thresh = 3;
|
||||
else
|
||||
data->disc_thresh = 2;
|
||||
|
|
|
@ -82,7 +82,6 @@ struct ti_pipe3 {
|
|||
struct clk *refclk;
|
||||
struct clk *div_clk;
|
||||
struct pipe3_dpll_map *dpll_map;
|
||||
u8 id;
|
||||
};
|
||||
|
||||
static struct pipe3_dpll_map dpll_map_usb[] = {
|
||||
|
@ -217,8 +216,13 @@ static int ti_pipe3_init(struct phy *x)
|
|||
u32 val;
|
||||
int ret = 0;
|
||||
|
||||
/*
|
||||
* Set pcie_pcs register to 0x96 for proper functioning of phy
|
||||
* as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table
|
||||
* 18-1804.
|
||||
*/
|
||||
if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {
|
||||
omap_control_pcie_pcs(phy->control_dev, phy->id, 0xF1);
|
||||
omap_control_pcie_pcs(phy->control_dev, 0x96);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -347,8 +351,6 @@ static int ti_pipe3_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
|
||||
if (of_property_read_u8(node, "id", &phy->id) < 0)
|
||||
phy->id = 1;
|
||||
|
||||
clk = devm_clk_get(phy->dev, "dpll_ref");
|
||||
if (IS_ERR(clk)) {
|
||||
|
|
|
@ -102,6 +102,8 @@ static int sunxi_reset_init(struct device_node *np)
|
|||
goto err_alloc;
|
||||
}
|
||||
|
||||
spin_lock_init(&data->lock);
|
||||
|
||||
data->rcdev.owner = THIS_MODULE;
|
||||
data->rcdev.nr_resets = size * 32;
|
||||
data->rcdev.ops = &sunxi_reset_ops;
|
||||
|
@ -157,6 +159,8 @@ static int sunxi_reset_probe(struct platform_device *pdev)
|
|||
if (IS_ERR(data->membase))
|
||||
return PTR_ERR(data->membase);
|
||||
|
||||
spin_lock_init(&data->lock);
|
||||
|
||||
data->rcdev.owner = THIS_MODULE;
|
||||
data->rcdev.nr_resets = resource_size(res) * 32;
|
||||
data->rcdev.ops = &sunxi_reset_ops;
|
||||
|
|
|
@ -591,7 +591,6 @@ static void scsi_free_sgtable(struct scsi_data_buffer *sdb, bool mq)
|
|||
static int scsi_alloc_sgtable(struct scsi_data_buffer *sdb, int nents, bool mq)
|
||||
{
|
||||
struct scatterlist *first_chunk = NULL;
|
||||
gfp_t gfp_mask = mq ? GFP_NOIO : GFP_ATOMIC;
|
||||
int ret;
|
||||
|
||||
BUG_ON(!nents);
|
||||
|
@ -606,7 +605,7 @@ static int scsi_alloc_sgtable(struct scsi_data_buffer *sdb, int nents, bool mq)
|
|||
}
|
||||
|
||||
ret = __sg_alloc_table(&sdb->table, nents, SCSI_MAX_SG_SEGMENTS,
|
||||
first_chunk, gfp_mask, scsi_sg_alloc);
|
||||
first_chunk, GFP_ATOMIC, scsi_sg_alloc);
|
||||
if (unlikely(ret))
|
||||
scsi_free_sgtable(sdb, mq);
|
||||
return ret;
|
||||
|
|
|
@ -2177,7 +2177,7 @@ bool BBbVT3253Init(struct vnt_private *priv)
|
|||
/* Init ANT B select,RX Config CR10 = 0x28->0x2A, 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted) */
|
||||
/*bResult &= BBbWriteEmbedded(dwIoBase,0x0a,0x28);*/
|
||||
/* Select VC1/VC2, CR215 = 0x02->0x06 */
|
||||
bResult &= BBbWriteEmbedded(dwIoBase, 0xd7, 0x06);
|
||||
bResult &= BBbWriteEmbedded(priv, 0xd7, 0x06);
|
||||
/* }} */
|
||||
|
||||
for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
|
||||
|
|
|
@ -182,6 +182,14 @@ bool set_channel(void *pDeviceHandler, unsigned int uConnectionChannel)
|
|||
if (pDevice->byCurrentCh == uConnectionChannel)
|
||||
return bResult;
|
||||
|
||||
/* Set VGA to max sensitivity */
|
||||
if (pDevice->bUpdateBBVGA &&
|
||||
pDevice->byBBVGACurrent != pDevice->abyBBVGA[0]) {
|
||||
pDevice->byBBVGACurrent = pDevice->abyBBVGA[0];
|
||||
|
||||
BBvSetVGAGainOffset(pDevice, pDevice->byBBVGACurrent);
|
||||
}
|
||||
|
||||
/* clear NAV */
|
||||
MACvRegBitsOn(pDevice->PortOffset, MAC_REG_MACCR, MACCR_CLRNAV);
|
||||
|
||||
|
|
|
@ -1232,7 +1232,7 @@ static int vnt_tx_packet(struct vnt_private *priv, struct sk_buff *skb)
|
|||
|
||||
head_td = priv->apCurrTD[dma_idx];
|
||||
|
||||
head_td->m_td1TD1.byTCR = (TCR_EDP|TCR_STP);
|
||||
head_td->m_td1TD1.byTCR = 0;
|
||||
|
||||
head_td->pTDInfo->skb = skb;
|
||||
|
||||
|
@ -1257,6 +1257,11 @@ static int vnt_tx_packet(struct vnt_private *priv, struct sk_buff *skb)
|
|||
|
||||
priv->bPWBitOn = false;
|
||||
|
||||
/* Set TSR1 & ReqCount in TxDescHead */
|
||||
head_td->m_td1TD1.byTCR |= (TCR_STP | TCR_EDP | EDMSDU);
|
||||
head_td->m_td1TD1.wReqCount =
|
||||
cpu_to_le16((u16)head_td->pTDInfo->dwReqCount);
|
||||
|
||||
head_td->pTDInfo->byFlags = TD_FLAGS_NETIF_SKB;
|
||||
|
||||
if (dma_idx == TYPE_AC0DMA)
|
||||
|
@ -1500,9 +1505,11 @@ static void vnt_bss_info_changed(struct ieee80211_hw *hw,
|
|||
if (conf->enable_beacon) {
|
||||
vnt_beacon_enable(priv, vif, conf);
|
||||
|
||||
MACvRegBitsOn(priv, MAC_REG_TCR, TCR_AUTOBCNTX);
|
||||
MACvRegBitsOn(priv->PortOffset, MAC_REG_TCR,
|
||||
TCR_AUTOBCNTX);
|
||||
} else {
|
||||
MACvRegBitsOff(priv, MAC_REG_TCR, TCR_AUTOBCNTX);
|
||||
MACvRegBitsOff(priv->PortOffset, MAC_REG_TCR,
|
||||
TCR_AUTOBCNTX);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -1204,13 +1204,10 @@ s_cbFillTxBufHead(struct vnt_private *pDevice, unsigned char byPktType,
|
|||
|
||||
ptdCurr = (PSTxDesc)pHeadTD;
|
||||
|
||||
ptdCurr->pTDInfo->dwReqCount = cbReqCount - uPadding;
|
||||
ptdCurr->pTDInfo->dwReqCount = cbReqCount;
|
||||
ptdCurr->pTDInfo->dwHeaderLength = cbHeaderLength;
|
||||
ptdCurr->pTDInfo->skb_dma = ptdCurr->pTDInfo->buf_dma;
|
||||
ptdCurr->buff_addr = cpu_to_le32(ptdCurr->pTDInfo->skb_dma);
|
||||
/* Set TSR1 & ReqCount in TxDescHead */
|
||||
ptdCurr->m_td1TD1.byTCR |= (TCR_STP | TCR_EDP | EDMSDU);
|
||||
ptdCurr->m_td1TD1.wReqCount = cpu_to_le16((unsigned short)(cbReqCount));
|
||||
|
||||
return cbHeaderLength;
|
||||
}
|
||||
|
|
|
@ -2399,17 +2399,12 @@ static unsigned int n_tty_poll(struct tty_struct *tty, struct file *file,
|
|||
|
||||
poll_wait(file, &tty->read_wait, wait);
|
||||
poll_wait(file, &tty->write_wait, wait);
|
||||
if (test_bit(TTY_OTHER_CLOSED, &tty->flags))
|
||||
mask |= POLLHUP;
|
||||
if (input_available_p(tty, 1))
|
||||
mask |= POLLIN | POLLRDNORM;
|
||||
else if (mask & POLLHUP) {
|
||||
tty_flush_to_ldisc(tty);
|
||||
if (input_available_p(tty, 1))
|
||||
mask |= POLLIN | POLLRDNORM;
|
||||
}
|
||||
if (tty->packet && tty->link->ctrl_status)
|
||||
mask |= POLLPRI | POLLIN | POLLRDNORM;
|
||||
if (test_bit(TTY_OTHER_CLOSED, &tty->flags))
|
||||
mask |= POLLHUP;
|
||||
if (tty_hung_up_p(file))
|
||||
mask |= POLLHUP;
|
||||
if (!(mask & (POLLHUP | POLLIN | POLLRDNORM))) {
|
||||
|
|
|
@ -1815,7 +1815,7 @@ pci_wch_ch353_setup(struct serial_private *priv,
|
|||
}
|
||||
|
||||
static int
|
||||
pci_wch_ch382_setup(struct serial_private *priv,
|
||||
pci_wch_ch38x_setup(struct serial_private *priv,
|
||||
const struct pciserial_board *board,
|
||||
struct uart_8250_port *port, int idx)
|
||||
{
|
||||
|
@ -1880,6 +1880,7 @@ pci_wch_ch382_setup(struct serial_private *priv,
|
|||
|
||||
#define PCIE_VENDOR_ID_WCH 0x1c00
|
||||
#define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
|
||||
#define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
|
||||
|
||||
/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
|
||||
#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
|
||||
|
@ -2571,13 +2572,21 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
|
|||
.subdevice = PCI_ANY_ID,
|
||||
.setup = pci_wch_ch353_setup,
|
||||
},
|
||||
/* WCH CH382 2S1P card (16750 clone) */
|
||||
/* WCH CH382 2S1P card (16850 clone) */
|
||||
{
|
||||
.vendor = PCIE_VENDOR_ID_WCH,
|
||||
.device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
|
||||
.subvendor = PCI_ANY_ID,
|
||||
.subdevice = PCI_ANY_ID,
|
||||
.setup = pci_wch_ch382_setup,
|
||||
.setup = pci_wch_ch38x_setup,
|
||||
},
|
||||
/* WCH CH384 4S card (16850 clone) */
|
||||
{
|
||||
.vendor = PCIE_VENDOR_ID_WCH,
|
||||
.device = PCIE_DEVICE_ID_WCH_CH384_4S,
|
||||
.subvendor = PCI_ANY_ID,
|
||||
.subdevice = PCI_ANY_ID,
|
||||
.setup = pci_wch_ch38x_setup,
|
||||
},
|
||||
/*
|
||||
* ASIX devices with FIFO bug
|
||||
|
@ -2876,6 +2885,7 @@ enum pci_board_num_t {
|
|||
pbn_fintek_4,
|
||||
pbn_fintek_8,
|
||||
pbn_fintek_12,
|
||||
pbn_wch384_4,
|
||||
};
|
||||
|
||||
/*
|
||||
|
@ -3675,6 +3685,14 @@ static struct pciserial_board pci_boards[] = {
|
|||
.base_baud = 115200,
|
||||
.first_offset = 0x40,
|
||||
},
|
||||
|
||||
[pbn_wch384_4] = {
|
||||
.flags = FL_BASE0,
|
||||
.num_ports = 4,
|
||||
.base_baud = 115200,
|
||||
.uart_offset = 8,
|
||||
.first_offset = 0xC0,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct pci_device_id blacklist[] = {
|
||||
|
@ -3687,6 +3705,7 @@ static const struct pci_device_id blacklist[] = {
|
|||
{ PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
|
||||
{ PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
|
||||
{ PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
|
||||
{ PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
|
||||
};
|
||||
|
||||
/*
|
||||
|
@ -5400,6 +5419,10 @@ static struct pci_device_id serial_pci_tbl[] = {
|
|||
PCI_ANY_ID, PCI_ANY_ID,
|
||||
0, 0, pbn_b0_bt_2_115200 },
|
||||
|
||||
{ PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
|
||||
PCI_ANY_ID, PCI_ANY_ID,
|
||||
0, 0, pbn_wch384_4 },
|
||||
|
||||
/*
|
||||
* Commtech, Inc. Fastcom adapters
|
||||
*/
|
||||
|
|
|
@ -1757,32 +1757,43 @@ static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
|
|||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_EXYNOS)
|
||||
#define EXYNOS_COMMON_SERIAL_DRV_DATA \
|
||||
.info = &(struct s3c24xx_uart_info) { \
|
||||
.name = "Samsung Exynos UART", \
|
||||
.type = PORT_S3C6400, \
|
||||
.has_divslot = 1, \
|
||||
.rx_fifomask = S5PV210_UFSTAT_RXMASK, \
|
||||
.rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
|
||||
.rx_fifofull = S5PV210_UFSTAT_RXFULL, \
|
||||
.tx_fifofull = S5PV210_UFSTAT_TXFULL, \
|
||||
.tx_fifomask = S5PV210_UFSTAT_TXMASK, \
|
||||
.tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
|
||||
.def_clk_sel = S3C2410_UCON_CLKSEL0, \
|
||||
.num_clks = 1, \
|
||||
.clksel_mask = 0, \
|
||||
.clksel_shift = 0, \
|
||||
}, \
|
||||
.def_cfg = &(struct s3c2410_uartcfg) { \
|
||||
.ucon = S5PV210_UCON_DEFAULT, \
|
||||
.ufcon = S5PV210_UFCON_DEFAULT, \
|
||||
.has_fracval = 1, \
|
||||
} \
|
||||
|
||||
static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
|
||||
.info = &(struct s3c24xx_uart_info) {
|
||||
.name = "Samsung Exynos4 UART",
|
||||
.type = PORT_S3C6400,
|
||||
.has_divslot = 1,
|
||||
.rx_fifomask = S5PV210_UFSTAT_RXMASK,
|
||||
.rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
|
||||
.rx_fifofull = S5PV210_UFSTAT_RXFULL,
|
||||
.tx_fifofull = S5PV210_UFSTAT_TXFULL,
|
||||
.tx_fifomask = S5PV210_UFSTAT_TXMASK,
|
||||
.tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
|
||||
.def_clk_sel = S3C2410_UCON_CLKSEL0,
|
||||
.num_clks = 1,
|
||||
.clksel_mask = 0,
|
||||
.clksel_shift = 0,
|
||||
},
|
||||
.def_cfg = &(struct s3c2410_uartcfg) {
|
||||
.ucon = S5PV210_UCON_DEFAULT,
|
||||
.ufcon = S5PV210_UFCON_DEFAULT,
|
||||
.has_fracval = 1,
|
||||
},
|
||||
EXYNOS_COMMON_SERIAL_DRV_DATA,
|
||||
.fifosize = { 256, 64, 16, 16 },
|
||||
};
|
||||
|
||||
static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
|
||||
EXYNOS_COMMON_SERIAL_DRV_DATA,
|
||||
.fifosize = { 64, 256, 16, 256 },
|
||||
};
|
||||
|
||||
#define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
|
||||
#define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
|
||||
#else
|
||||
#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
|
||||
#define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
|
||||
#endif
|
||||
|
||||
static struct platform_device_id s3c24xx_serial_driver_ids[] = {
|
||||
|
@ -1804,6 +1815,9 @@ static struct platform_device_id s3c24xx_serial_driver_ids[] = {
|
|||
}, {
|
||||
.name = "exynos4210-uart",
|
||||
.driver_data = EXYNOS4210_SERIAL_DRV_DATA,
|
||||
}, {
|
||||
.name = "exynos5433-uart",
|
||||
.driver_data = EXYNOS5433_SERIAL_DRV_DATA,
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
@ -1823,6 +1837,8 @@ static const struct of_device_id s3c24xx_uart_dt_match[] = {
|
|||
.data = (void *)S5PV210_SERIAL_DRV_DATA },
|
||||
{ .compatible = "samsung,exynos4210-uart",
|
||||
.data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
|
||||
{ .compatible = "samsung,exynos5433-uart",
|
||||
.data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
|
||||
|
|
|
@ -2164,7 +2164,9 @@ uart_report_port(struct uart_driver *drv, struct uart_port *port)
|
|||
break;
|
||||
}
|
||||
|
||||
dev_info(port->dev, "%s%d at %s (irq = %d, base_baud = %d) is a %s\n",
|
||||
printk(KERN_INFO "%s%s%s%d at %s (irq = %d, base_baud = %d) is a %s\n",
|
||||
port->dev ? dev_name(port->dev) : "",
|
||||
port->dev ? ": " : "",
|
||||
drv->dev_name,
|
||||
drv->tty_driver->name_base + port->line,
|
||||
address, port->irq, port->uartclk / 16, uart_type(port));
|
||||
|
|
|
@ -1464,6 +1464,9 @@ static int tty_reopen(struct tty_struct *tty)
|
|||
driver->subtype == PTY_TYPE_MASTER)
|
||||
return -EIO;
|
||||
|
||||
if (test_bit(TTY_EXCLUSIVE, &tty->flags) && !capable(CAP_SYS_ADMIN))
|
||||
return -EBUSY;
|
||||
|
||||
tty->count++;
|
||||
|
||||
WARN_ON(!tty->ldisc);
|
||||
|
@ -2106,10 +2109,6 @@ retry_open:
|
|||
retval = -ENODEV;
|
||||
filp->f_flags = saved_flags;
|
||||
|
||||
if (!retval && test_bit(TTY_EXCLUSIVE, &tty->flags) &&
|
||||
!capable(CAP_SYS_ADMIN))
|
||||
retval = -EBUSY;
|
||||
|
||||
if (retval) {
|
||||
#ifdef TTY_DEBUG_HANGUP
|
||||
printk(KERN_DEBUG "%s: error %d in opening %s...\n", __func__,
|
||||
|
|
|
@ -669,7 +669,6 @@ static int ci_hdrc_probe(struct platform_device *pdev)
|
|||
if (!ci)
|
||||
return -ENOMEM;
|
||||
|
||||
platform_set_drvdata(pdev, ci);
|
||||
ci->dev = dev;
|
||||
ci->platdata = dev_get_platdata(dev);
|
||||
ci->imx28_write_fix = !!(ci->platdata->flags &
|
||||
|
@ -783,6 +782,7 @@ static int ci_hdrc_probe(struct platform_device *pdev)
|
|||
}
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, ci);
|
||||
ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED,
|
||||
ci->platdata->name, ci);
|
||||
if (ret)
|
||||
|
|
|
@ -91,6 +91,7 @@ static int host_start(struct ci_hdrc *ci)
|
|||
if (!hcd)
|
||||
return -ENOMEM;
|
||||
|
||||
dev_set_drvdata(ci->dev, ci);
|
||||
hcd->rsrc_start = ci->hw_bank.phys;
|
||||
hcd->rsrc_len = ci->hw_bank.size;
|
||||
hcd->regs = ci->hw_bank.abs;
|
||||
|
|
|
@ -2567,7 +2567,7 @@ error:
|
|||
* s3c_hsotg_ep_disable - disable given endpoint
|
||||
* @ep: The endpoint to disable.
|
||||
*/
|
||||
static int s3c_hsotg_ep_disable(struct usb_ep *ep)
|
||||
static int s3c_hsotg_ep_disable_force(struct usb_ep *ep, bool force)
|
||||
{
|
||||
struct s3c_hsotg_ep *hs_ep = our_ep(ep);
|
||||
struct dwc2_hsotg *hsotg = hs_ep->parent;
|
||||
|
@ -2588,7 +2588,7 @@ static int s3c_hsotg_ep_disable(struct usb_ep *ep)
|
|||
|
||||
spin_lock_irqsave(&hsotg->lock, flags);
|
||||
/* terminate all requests with shutdown */
|
||||
kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false);
|
||||
kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, force);
|
||||
|
||||
hsotg->fifo_map &= ~(1<<hs_ep->fifo_index);
|
||||
hs_ep->fifo_index = 0;
|
||||
|
@ -2609,6 +2609,10 @@ static int s3c_hsotg_ep_disable(struct usb_ep *ep)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int s3c_hsotg_ep_disable(struct usb_ep *ep)
|
||||
{
|
||||
return s3c_hsotg_ep_disable_force(ep, false);
|
||||
}
|
||||
/**
|
||||
* on_list - check request is on the given endpoint
|
||||
* @ep: The endpoint to check.
|
||||
|
@ -2924,7 +2928,7 @@ static int s3c_hsotg_udc_stop(struct usb_gadget *gadget)
|
|||
|
||||
/* all endpoints should be shutdown */
|
||||
for (ep = 1; ep < hsotg->num_of_eps; ep++)
|
||||
s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
|
||||
s3c_hsotg_ep_disable_force(&hsotg->eps[ep].ep, true);
|
||||
|
||||
spin_lock_irqsave(&hsotg->lock, flags);
|
||||
|
||||
|
|
|
@ -33,6 +33,8 @@
|
|||
#define PCI_DEVICE_ID_INTEL_BYT 0x0f37
|
||||
#define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
|
||||
#define PCI_DEVICE_ID_INTEL_BSW 0x22B7
|
||||
#define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30
|
||||
#define PCI_DEVICE_ID_INTEL_SPTH 0xa130
|
||||
|
||||
struct dwc3_pci {
|
||||
struct device *dev;
|
||||
|
@ -219,6 +221,8 @@ static const struct pci_device_id dwc3_pci_id_table[] = {
|
|||
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW), },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT), },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MRFLD), },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SPTLP), },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SPTH), },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB), },
|
||||
{ } /* Terminating Entry */
|
||||
};
|
||||
|
|
|
@ -882,8 +882,7 @@ static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
|
|||
|
||||
if (i == (request->num_mapped_sgs - 1) ||
|
||||
sg_is_last(s)) {
|
||||
if (list_is_last(&req->list,
|
||||
&dep->request_list))
|
||||
if (list_empty(&dep->request_list))
|
||||
last_one = true;
|
||||
chain = false;
|
||||
}
|
||||
|
@ -901,6 +900,9 @@ static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
|
|||
if (last_one)
|
||||
break;
|
||||
}
|
||||
|
||||
if (last_one)
|
||||
break;
|
||||
} else {
|
||||
dma = req->request.dma;
|
||||
length = req->request.length;
|
||||
|
|
|
@ -399,8 +399,9 @@ static int hidg_setup(struct usb_function *f,
|
|||
value = __le16_to_cpu(ctrl->wValue);
|
||||
length = __le16_to_cpu(ctrl->wLength);
|
||||
|
||||
VDBG(cdev, "hid_setup crtl_request : bRequestType:0x%x bRequest:0x%x "
|
||||
"Value:0x%x\n", ctrl->bRequestType, ctrl->bRequest, value);
|
||||
VDBG(cdev,
|
||||
"%s crtl_request : bRequestType:0x%x bRequest:0x%x Value:0x%x\n",
|
||||
__func__, ctrl->bRequestType, ctrl->bRequest, value);
|
||||
|
||||
switch ((ctrl->bRequestType << 8) | ctrl->bRequest) {
|
||||
case ((USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE) << 8
|
||||
|
|
|
@ -520,7 +520,7 @@ static void f_midi_transmit(struct f_midi *midi, struct usb_request *req)
|
|||
req = midi_alloc_ep_req(ep, midi->buflen);
|
||||
|
||||
if (!req) {
|
||||
ERROR(midi, "gmidi_transmit: alloc_ep_request failed\n");
|
||||
ERROR(midi, "%s: alloc_ep_request failed\n", __func__);
|
||||
return;
|
||||
}
|
||||
req->length = 0;
|
||||
|
|
|
@ -897,7 +897,6 @@ static void f_audio_free_inst(struct usb_function_instance *f)
|
|||
struct f_uac1_opts *opts;
|
||||
|
||||
opts = container_of(f, struct f_uac1_opts, func_inst);
|
||||
gaudio_cleanup(opts->card);
|
||||
if (opts->fn_play_alloc)
|
||||
kfree(opts->fn_play);
|
||||
if (opts->fn_cap_alloc)
|
||||
|
@ -935,6 +934,7 @@ static void f_audio_free(struct usb_function *f)
|
|||
struct f_audio *audio = func_to_audio(f);
|
||||
struct f_uac1_opts *opts;
|
||||
|
||||
gaudio_cleanup(&audio->card);
|
||||
opts = container_of(f->fi, struct f_uac1_opts, func_inst);
|
||||
kfree(audio);
|
||||
mutex_lock(&opts->lock);
|
||||
|
|
|
@ -441,6 +441,7 @@ ep_write (struct file *fd, const char __user *buf, size_t len, loff_t *ptr)
|
|||
kbuf = memdup_user(buf, len);
|
||||
if (IS_ERR(kbuf)) {
|
||||
value = PTR_ERR(kbuf);
|
||||
kbuf = NULL;
|
||||
goto free1;
|
||||
}
|
||||
|
||||
|
@ -449,6 +450,7 @@ ep_write (struct file *fd, const char __user *buf, size_t len, loff_t *ptr)
|
|||
data->name, len, (int) value);
|
||||
free1:
|
||||
mutex_unlock(&data->lock);
|
||||
kfree (kbuf);
|
||||
return value;
|
||||
}
|
||||
|
||||
|
|
|
@ -716,10 +716,10 @@ static int queue_dma(struct usba_udc *udc, struct usba_ep *ep,
|
|||
req->using_dma = 1;
|
||||
req->ctrl = USBA_BF(DMA_BUF_LEN, req->req.length)
|
||||
| USBA_DMA_CH_EN | USBA_DMA_END_BUF_IE
|
||||
| USBA_DMA_END_TR_EN | USBA_DMA_END_TR_IE;
|
||||
| USBA_DMA_END_BUF_EN;
|
||||
|
||||
if (ep->is_in)
|
||||
req->ctrl |= USBA_DMA_END_BUF_EN;
|
||||
if (!ep->is_in)
|
||||
req->ctrl |= USBA_DMA_END_TR_EN | USBA_DMA_END_TR_IE;
|
||||
|
||||
/*
|
||||
* Add this request to the queue and submit for DMA if
|
||||
|
@ -828,7 +828,7 @@ static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
|
|||
{
|
||||
struct usba_ep *ep = to_usba_ep(_ep);
|
||||
struct usba_udc *udc = ep->udc;
|
||||
struct usba_request *req = to_usba_req(_req);
|
||||
struct usba_request *req;
|
||||
unsigned long flags;
|
||||
u32 status;
|
||||
|
||||
|
@ -837,6 +837,16 @@ static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
|
|||
|
||||
spin_lock_irqsave(&udc->lock, flags);
|
||||
|
||||
list_for_each_entry(req, &ep->queue, queue) {
|
||||
if (&req->req == _req)
|
||||
break;
|
||||
}
|
||||
|
||||
if (&req->req != _req) {
|
||||
spin_unlock_irqrestore(&udc->lock, flags);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (req->using_dma) {
|
||||
/*
|
||||
* If this request is currently being transferred,
|
||||
|
@ -1563,7 +1573,6 @@ static void usba_ep_irq(struct usba_udc *udc, struct usba_ep *ep)
|
|||
if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
|
||||
DBG(DBG_BUS, "%s: RX data ready\n", ep->ep.name);
|
||||
receive_data(ep);
|
||||
usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -718,10 +718,11 @@ static int ep_queue(struct bdc_ep *ep, struct bdc_req *req)
|
|||
struct bdc *bdc;
|
||||
int ret = 0;
|
||||
|
||||
bdc = ep->bdc;
|
||||
if (!req || !ep || !ep->usb_ep.desc)
|
||||
return -EINVAL;
|
||||
|
||||
bdc = ep->bdc;
|
||||
|
||||
req->usb_req.actual = 0;
|
||||
req->usb_req.status = -EINPROGRESS;
|
||||
req->epnum = ep->ep_num;
|
||||
|
|
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