ASoC: codecs: Add Awinic AW88395 audio amplifier
Merge series from wangweidong.a@awinic.com: The Awinic AW88395 is an I2S/TDM input, high efficiency digital Smart K audio amplifier with an integrated 10.25V smart boost converter. Add a DT schema for describing Awinic AW88395 audio amplifiers. They are controlled using I2C
This commit is contained in:
Mark Brown
Коммит
41e0207f16
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@ -0,0 +1,53 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/sound/awinic,aw88395.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Awinic AW88395 Smart Audio Amplifier
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maintainers:
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- Weidong Wang <wangweidong.a@awinic.com>
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description:
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The Awinic AW88395 is an I2S/TDM input, high efficiency
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digital Smart K audio amplifier with an integrated 10.25V
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smart boost convert.
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allOf:
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- $ref: dai-common.yaml#
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properties:
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compatible:
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const: awinic,aw88395
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reg:
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maxItems: 1
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'#sound-dai-cells':
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const: 0
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reset-gpios:
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maxItems: 1
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required:
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- compatible
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- reg
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- '#sound-dai-cells'
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- reset-gpios
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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i2c {
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#address-cells = <1>;
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#size-cells = <0>;
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audio-codec@34 {
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compatible = "awinic,aw88395";
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reg = <0x34>;
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#sound-dai-cells = <0>;
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reset-gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
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};
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};
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@ -54,6 +54,7 @@ config SND_SOC_ALL_CODECS
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imply SND_SOC_ALC5623
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imply SND_SOC_ALC5632
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imply SND_SOC_AW8738
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imply SND_SOC_AW88395
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imply SND_SOC_BT_SCO
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imply SND_SOC_BD28623
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imply SND_SOC_CQ0093VC
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@ -601,6 +602,22 @@ config SND_SOC_AW8738
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SND_SOC_SIMPLE_AMPLIFIER, but additionally allows setting the
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operation mode using the Awinic-specific one-wire pulse control.
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config SND_SOC_AW88395_LIB
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tristate
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config SND_SOC_AW88395
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tristate "Soc Audio for awinic aw88395"
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depends on I2C
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select CRC8
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select CRC32
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select REGMAP_I2C
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select SND_SOC_AW88395_LIB
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help
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this option enables support for aw88395 Smart PA.
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The Awinic AW88395 is an I2S/TDM input, high efficiency
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digital Smart K audio amplifier with an integrated 10V
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smart boost convert.
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config SND_SOC_BD28623
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tristate "ROHM BD28623 CODEC"
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help
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@ -46,6 +46,9 @@ snd-soc-ak5386-objs := ak5386.o
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snd-soc-ak5558-objs := ak5558.o
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snd-soc-arizona-objs := arizona.o arizona-jack.o
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snd-soc-aw8738-objs := aw8738.o
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snd-soc-aw88395-lib-objs := aw88395/aw88395_lib.o
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snd-soc-aw88395-objs := aw88395/aw88395.o \
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aw88395/aw88395_device.o
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snd-soc-bd28623-objs := bd28623.o
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snd-soc-bt-sco-objs := bt-sco.o
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snd-soc-cpcap-objs := cpcap.o
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@ -409,6 +412,8 @@ obj-$(CONFIG_SND_SOC_ALC5623) += snd-soc-alc5623.o
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obj-$(CONFIG_SND_SOC_ALC5632) += snd-soc-alc5632.o
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obj-$(CONFIG_SND_SOC_ARIZONA) += snd-soc-arizona.o
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obj-$(CONFIG_SND_SOC_AW8738) += snd-soc-aw8738.o
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obj-$(CONFIG_SND_SOC_AW88395_LIB) += snd-soc-aw88395-lib.o
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obj-$(CONFIG_SND_SOC_AW88395) +=snd-soc-aw88395.o
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obj-$(CONFIG_SND_SOC_BD28623) += snd-soc-bd28623.o
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obj-$(CONFIG_SND_SOC_BT_SCO) += snd-soc-bt-sco.o
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obj-$(CONFIG_SND_SOC_CQ0093VC) += snd-soc-cq93vc.o
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@ -0,0 +1,580 @@
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// SPDX-License-Identifier: GPL-2.0-only
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//
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// aw88395.c -- ALSA SoC AW88395 codec support
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//
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// Copyright (c) 2022-2023 AWINIC Technology CO., LTD
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//
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// Author: Bruce zhao <zhaolei@awinic.com>
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// Author: Weidong Wang <wangweidong.a@awinic.com>
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//
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#include <linux/i2c.h>
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#include <linux/firmware.h>
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#include <linux/of_gpio.h>
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#include <linux/regmap.h>
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#include <sound/soc.h>
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#include "aw88395.h"
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#include "aw88395_device.h"
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#include "aw88395_lib.h"
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#include "aw88395_reg.h"
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static const struct regmap_config aw88395_remap_config = {
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.val_bits = 16,
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.reg_bits = 8,
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.max_register = AW88395_REG_MAX - 1,
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.reg_format_endian = REGMAP_ENDIAN_LITTLE,
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.val_format_endian = REGMAP_ENDIAN_BIG,
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};
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static void aw88395_start_pa(struct aw88395 *aw88395)
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{
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int ret, i;
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for (i = 0; i < AW88395_START_RETRIES; i++) {
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ret = aw88395_dev_start(aw88395->aw_pa);
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if (ret) {
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dev_err(aw88395->aw_pa->dev, "aw88395 device start failed. retry = %d", i);
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ret = aw88395_dev_fw_update(aw88395->aw_pa, AW88395_DSP_FW_UPDATE_ON, true);
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if (ret < 0) {
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dev_err(aw88395->aw_pa->dev, "fw update failed");
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continue;
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}
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} else {
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dev_info(aw88395->aw_pa->dev, "start success\n");
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break;
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}
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}
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}
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static void aw88395_startup_work(struct work_struct *work)
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{
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struct aw88395 *aw88395 =
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container_of(work, struct aw88395, start_work.work);
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mutex_lock(&aw88395->lock);
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aw88395_start_pa(aw88395);
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mutex_unlock(&aw88395->lock);
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}
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static void aw88395_start(struct aw88395 *aw88395, bool sync_start)
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{
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int ret;
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if (aw88395->aw_pa->fw_status != AW88395_DEV_FW_OK)
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return;
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if (aw88395->aw_pa->status == AW88395_DEV_PW_ON)
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return;
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ret = aw88395_dev_fw_update(aw88395->aw_pa, AW88395_DSP_FW_UPDATE_OFF, true);
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if (ret < 0) {
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dev_err(aw88395->aw_pa->dev, "fw update failed.");
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return;
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}
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if (sync_start == AW88395_SYNC_START)
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aw88395_start_pa(aw88395);
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else
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queue_delayed_work(system_wq,
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&aw88395->start_work,
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AW88395_START_WORK_DELAY_MS);
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}
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static struct snd_soc_dai_driver aw88395_dai[] = {
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{
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.name = "aw88395-aif",
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.id = 1,
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.playback = {
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.stream_name = "Speaker_Playback",
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.channels_min = 1,
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.channels_max = 2,
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.rates = AW88395_RATES,
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.formats = AW88395_FORMATS,
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},
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.capture = {
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.stream_name = "Speaker_Capture",
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.channels_min = 1,
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.channels_max = 2,
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.rates = AW88395_RATES,
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.formats = AW88395_FORMATS,
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},
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},
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};
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static int aw88395_get_fade_in_time(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
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struct aw88395 *aw88395 = snd_soc_component_get_drvdata(component);
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struct aw_device *aw_dev = aw88395->aw_pa;
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ucontrol->value.integer.value[0] = aw_dev->fade_in_time;
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return 0;
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}
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static int aw88395_set_fade_in_time(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
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struct aw88395 *aw88395 = snd_soc_component_get_drvdata(component);
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struct soc_mixer_control *mc =
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(struct soc_mixer_control *)kcontrol->private_value;
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struct aw_device *aw_dev = aw88395->aw_pa;
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int time;
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time = ucontrol->value.integer.value[0];
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if (time < mc->min || time > mc->max)
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return -EINVAL;
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if (time != aw_dev->fade_in_time) {
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aw_dev->fade_in_time = time;
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return 1;
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}
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return 0;
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}
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static int aw88395_get_fade_out_time(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
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struct aw88395 *aw88395 = snd_soc_component_get_drvdata(component);
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struct aw_device *aw_dev = aw88395->aw_pa;
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ucontrol->value.integer.value[0] = aw_dev->fade_out_time;
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return 0;
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}
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static int aw88395_set_fade_out_time(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
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struct aw88395 *aw88395 = snd_soc_component_get_drvdata(component);
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struct soc_mixer_control *mc =
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(struct soc_mixer_control *)kcontrol->private_value;
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struct aw_device *aw_dev = aw88395->aw_pa;
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int time;
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time = ucontrol->value.integer.value[0];
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if (time < mc->min || time > mc->max)
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return -EINVAL;
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if (time != aw_dev->fade_out_time) {
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aw_dev->fade_out_time = time;
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return 1;
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}
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return 0;
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}
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static int aw88395_profile_info(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_info *uinfo)
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{
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struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
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struct aw88395 *aw88395 = snd_soc_component_get_drvdata(codec);
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const char *prof_name;
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char *name;
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int count;
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uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
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uinfo->count = 1;
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count = aw88395_dev_get_profile_count(aw88395->aw_pa);
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if (count <= 0) {
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uinfo->value.enumerated.items = 0;
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return 0;
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}
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uinfo->value.enumerated.items = count;
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if (uinfo->value.enumerated.item >= count)
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uinfo->value.enumerated.item = count - 1;
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name = uinfo->value.enumerated.name;
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count = uinfo->value.enumerated.item;
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prof_name = aw88395_dev_get_prof_name(aw88395->aw_pa, count);
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if (!prof_name) {
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strscpy(uinfo->value.enumerated.name, "null",
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strlen("null") + 1);
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return 0;
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}
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strscpy(name, prof_name, sizeof(uinfo->value.enumerated.name));
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return 0;
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}
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static int aw88395_profile_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
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struct aw88395 *aw88395 = snd_soc_component_get_drvdata(codec);
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ucontrol->value.integer.value[0] = aw88395_dev_get_profile_index(aw88395->aw_pa);
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return 0;
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}
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static int aw88395_profile_set(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
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struct aw88395 *aw88395 = snd_soc_component_get_drvdata(codec);
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int ret;
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/* pa stop or stopping just set profile */
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mutex_lock(&aw88395->lock);
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ret = aw88395_dev_set_profile_index(aw88395->aw_pa, ucontrol->value.integer.value[0]);
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if (ret < 0) {
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dev_dbg(codec->dev, "profile index does not change");
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mutex_unlock(&aw88395->lock);
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return 0;
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}
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if (aw88395->aw_pa->status) {
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aw88395_dev_stop(aw88395->aw_pa);
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aw88395_start(aw88395, AW88395_SYNC_START);
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}
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mutex_unlock(&aw88395->lock);
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return 1;
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}
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static int aw88395_volume_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
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struct aw88395 *aw88395 = snd_soc_component_get_drvdata(codec);
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struct aw_volume_desc *vol_desc = &aw88395->aw_pa->volume_desc;
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ucontrol->value.integer.value[0] = vol_desc->ctl_volume;
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return 0;
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}
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static int aw88395_volume_set(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
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struct aw88395 *aw88395 = snd_soc_component_get_drvdata(codec);
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struct aw_volume_desc *vol_desc = &aw88395->aw_pa->volume_desc;
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struct soc_mixer_control *mc =
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(struct soc_mixer_control *)kcontrol->private_value;
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int value;
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value = ucontrol->value.integer.value[0];
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if (value < mc->min || value > mc->max)
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return -EINVAL;
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if (vol_desc->ctl_volume != value) {
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vol_desc->ctl_volume = value;
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aw88395_dev_set_volume(aw88395->aw_pa, vol_desc->ctl_volume);
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return 1;
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}
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return 0;
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}
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static int aw88395_get_fade_step(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
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struct aw88395 *aw88395 = snd_soc_component_get_drvdata(codec);
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ucontrol->value.integer.value[0] = aw88395->aw_pa->fade_step;
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return 0;
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}
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static int aw88395_set_fade_step(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
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struct aw88395 *aw88395 = snd_soc_component_get_drvdata(codec);
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struct soc_mixer_control *mc =
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(struct soc_mixer_control *)kcontrol->private_value;
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int value;
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value = ucontrol->value.integer.value[0];
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if (value < mc->min || value > mc->max)
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return -EINVAL;
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if (aw88395->aw_pa->fade_step != value) {
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aw88395->aw_pa->fade_step = value;
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return 1;
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}
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return 0;
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}
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static int aw88395_re_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
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struct aw88395 *aw88395 = snd_soc_component_get_drvdata(codec);
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struct aw_device *aw_dev = aw88395->aw_pa;
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ucontrol->value.integer.value[0] = aw_dev->cali_desc.cali_re;
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||||
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return 0;
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}
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static int aw88395_re_set(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
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||||
struct aw88395 *aw88395 = snd_soc_component_get_drvdata(codec);
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struct soc_mixer_control *mc =
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(struct soc_mixer_control *)kcontrol->private_value;
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struct aw_device *aw_dev = aw88395->aw_pa;
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||||
int value;
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||||
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||||
value = ucontrol->value.integer.value[0];
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||||
if (value < mc->min || value > mc->max)
|
||||
return -EINVAL;
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||||
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||||
if (aw_dev->cali_desc.cali_re != value) {
|
||||
aw_dev->cali_desc.cali_re = value;
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct snd_kcontrol_new aw88395_controls[] = {
|
||||
SOC_SINGLE_EXT("PCM Playback Volume", AW88395_SYSCTRL2_REG,
|
||||
6, AW88395_MUTE_VOL, 0, aw88395_volume_get,
|
||||
aw88395_volume_set),
|
||||
SOC_SINGLE_EXT("Fade Step", 0, 0, AW88395_MUTE_VOL, 0,
|
||||
aw88395_get_fade_step, aw88395_set_fade_step),
|
||||
SOC_SINGLE_EXT("Volume Ramp Up Step", 0, 0, FADE_TIME_MAX, FADE_TIME_MIN,
|
||||
aw88395_get_fade_in_time, aw88395_set_fade_in_time),
|
||||
SOC_SINGLE_EXT("Volume Ramp Down Step", 0, 0, FADE_TIME_MAX, FADE_TIME_MIN,
|
||||
aw88395_get_fade_out_time, aw88395_set_fade_out_time),
|
||||
SOC_SINGLE_EXT("Calib", 0, 0, 100, 0,
|
||||
aw88395_re_get, aw88395_re_set),
|
||||
AW88395_PROFILE_EXT("Profile Set", aw88395_profile_info,
|
||||
aw88395_profile_get, aw88395_profile_set),
|
||||
};
|
||||
|
||||
static int aw88395_plack_event(struct snd_soc_dapm_widget *w,
|
||||
struct snd_kcontrol *k, int event)
|
||||
{
|
||||
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
|
||||
struct aw88395 *aw88395 = snd_soc_component_get_drvdata(component);
|
||||
|
||||
mutex_lock(&aw88395->lock);
|
||||
switch (event) {
|
||||
case SND_SOC_DAPM_PRE_PMU:
|
||||
aw88395_start(aw88395, AW88395_ASYNC_START);
|
||||
break;
|
||||
case SND_SOC_DAPM_POST_PMD:
|
||||
aw88395_dev_stop(aw88395->aw_pa);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
mutex_unlock(&aw88395->lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct snd_soc_dapm_widget aw88395_dapm_widgets[] = {
|
||||
/* playback */
|
||||
SND_SOC_DAPM_AIF_IN_E("AIF_RX", "Speaker_Playback", 0, 0, 0, 0,
|
||||
aw88395_plack_event,
|
||||
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
|
||||
SND_SOC_DAPM_OUTPUT("DAC Output"),
|
||||
|
||||
/* capture */
|
||||
SND_SOC_DAPM_AIF_OUT("AIF_TX", "Speaker_Capture", 0, SND_SOC_NOPM, 0, 0),
|
||||
SND_SOC_DAPM_INPUT("ADC Input"),
|
||||
};
|
||||
|
||||
static const struct snd_soc_dapm_route aw88395_audio_map[] = {
|
||||
{"DAC Output", NULL, "AIF_RX"},
|
||||
{"AIF_TX", NULL, "ADC Input"},
|
||||
};
|
||||
|
||||
static int aw88395_codec_probe(struct snd_soc_component *component)
|
||||
{
|
||||
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
|
||||
struct aw88395 *aw88395 = snd_soc_component_get_drvdata(component);
|
||||
int ret;
|
||||
|
||||
INIT_DELAYED_WORK(&aw88395->start_work, aw88395_startup_work);
|
||||
|
||||
/* add widgets */
|
||||
ret = snd_soc_dapm_new_controls(dapm, aw88395_dapm_widgets,
|
||||
ARRAY_SIZE(aw88395_dapm_widgets));
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* add route */
|
||||
ret = snd_soc_dapm_add_routes(dapm, aw88395_audio_map,
|
||||
ARRAY_SIZE(aw88395_audio_map));
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = snd_soc_add_component_controls(component, aw88395_controls,
|
||||
ARRAY_SIZE(aw88395_controls));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void aw88395_codec_remove(struct snd_soc_component *aw_codec)
|
||||
{
|
||||
struct aw88395 *aw88395 = snd_soc_component_get_drvdata(aw_codec);
|
||||
|
||||
cancel_delayed_work_sync(&aw88395->start_work);
|
||||
}
|
||||
|
||||
static const struct snd_soc_component_driver soc_codec_dev_aw88395 = {
|
||||
.probe = aw88395_codec_probe,
|
||||
.remove = aw88395_codec_remove,
|
||||
};
|
||||
|
||||
static struct aw88395 *aw88395_malloc_init(struct i2c_client *i2c)
|
||||
{
|
||||
struct aw88395 *aw88395 = devm_kzalloc(&i2c->dev,
|
||||
sizeof(struct aw88395), GFP_KERNEL);
|
||||
if (!aw88395)
|
||||
return NULL;
|
||||
|
||||
mutex_init(&aw88395->lock);
|
||||
|
||||
return aw88395;
|
||||
}
|
||||
|
||||
static void aw88395_hw_reset(struct aw88395 *aw88395)
|
||||
{
|
||||
if (aw88395->reset_gpio) {
|
||||
gpiod_set_value_cansleep(aw88395->reset_gpio, 0);
|
||||
usleep_range(AW88395_1000_US, AW88395_1000_US + 10);
|
||||
gpiod_set_value_cansleep(aw88395->reset_gpio, 1);
|
||||
usleep_range(AW88395_1000_US, AW88395_1000_US + 10);
|
||||
} else {
|
||||
dev_err(aw88395->aw_pa->dev, "%s failed", __func__);
|
||||
}
|
||||
}
|
||||
|
||||
static int aw88395_request_firmware_file(struct aw88395 *aw88395)
|
||||
{
|
||||
const struct firmware *cont = NULL;
|
||||
int ret;
|
||||
|
||||
aw88395->aw_pa->fw_status = AW88395_DEV_FW_FAILED;
|
||||
|
||||
ret = request_firmware(&cont, AW88395_ACF_FILE, aw88395->aw_pa->dev);
|
||||
if ((ret < 0) || (!cont)) {
|
||||
dev_err(aw88395->aw_pa->dev, "load [%s] failed!", AW88395_ACF_FILE);
|
||||
return ret;
|
||||
}
|
||||
|
||||
dev_info(aw88395->aw_pa->dev, "loaded %s - size: %zu\n",
|
||||
AW88395_ACF_FILE, cont ? cont->size : 0);
|
||||
|
||||
aw88395->aw_cfg = devm_kzalloc(aw88395->aw_pa->dev, cont->size + sizeof(int), GFP_KERNEL);
|
||||
if (!aw88395->aw_cfg) {
|
||||
release_firmware(cont);
|
||||
return -ENOMEM;
|
||||
}
|
||||
aw88395->aw_cfg->len = (int)cont->size;
|
||||
memcpy(aw88395->aw_cfg->data, cont->data, cont->size);
|
||||
release_firmware(cont);
|
||||
|
||||
ret = aw88395_dev_load_acf_check(aw88395->aw_pa, aw88395->aw_cfg);
|
||||
if (ret < 0) {
|
||||
dev_err(aw88395->aw_pa->dev, "Load [%s] failed ....!", AW88395_ACF_FILE);
|
||||
return ret;
|
||||
}
|
||||
|
||||
dev_dbg(aw88395->aw_pa->dev, "%s : bin load success\n", __func__);
|
||||
|
||||
mutex_lock(&aw88395->lock);
|
||||
/* aw device init */
|
||||
ret = aw88395_dev_init(aw88395->aw_pa, aw88395->aw_cfg);
|
||||
if (ret < 0)
|
||||
dev_err(aw88395->aw_pa->dev, "dev init failed");
|
||||
mutex_unlock(&aw88395->lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int aw88395_i2c_probe(struct i2c_client *i2c)
|
||||
{
|
||||
struct aw88395 *aw88395;
|
||||
int ret;
|
||||
|
||||
if (!i2c_check_functionality(i2c->adapter, I2C_FUNC_I2C)) {
|
||||
dev_err(&i2c->dev, "check_functionality failed");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
aw88395 = aw88395_malloc_init(i2c);
|
||||
if (!aw88395) {
|
||||
dev_err(&i2c->dev, "malloc aw88395 failed");
|
||||
return -ENOMEM;
|
||||
}
|
||||
i2c_set_clientdata(i2c, aw88395);
|
||||
|
||||
aw88395->reset_gpio = devm_gpiod_get_optional(&i2c->dev, "reset", GPIOD_OUT_LOW);
|
||||
if (IS_ERR(aw88395->reset_gpio))
|
||||
dev_info(&i2c->dev, "reset gpio not defined\n");
|
||||
|
||||
/* hardware reset */
|
||||
aw88395_hw_reset(aw88395);
|
||||
|
||||
aw88395->regmap = devm_regmap_init_i2c(i2c, &aw88395_remap_config);
|
||||
if (IS_ERR(aw88395->regmap)) {
|
||||
ret = PTR_ERR(aw88395->regmap);
|
||||
dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* aw pa init */
|
||||
ret = aw88395_init(&aw88395->aw_pa, i2c, aw88395->regmap);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = aw88395_request_firmware_file(aw88395);
|
||||
if (ret < 0) {
|
||||
dev_err(&i2c->dev, "%s failed\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devm_snd_soc_register_component(&i2c->dev,
|
||||
&soc_codec_dev_aw88395,
|
||||
aw88395_dai, ARRAY_SIZE(aw88395_dai));
|
||||
if (ret < 0) {
|
||||
dev_err(&i2c->dev, "failed to register aw88395: %d", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct i2c_device_id aw88395_i2c_id[] = {
|
||||
{ AW88395_I2C_NAME, 0 },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(i2c, aw88395_i2c_id);
|
||||
|
||||
static struct i2c_driver aw88395_i2c_driver = {
|
||||
.driver = {
|
||||
.name = AW88395_I2C_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
.probe_new = aw88395_i2c_probe,
|
||||
.id_table = aw88395_i2c_id,
|
||||
};
|
||||
module_i2c_driver(aw88395_i2c_driver);
|
||||
|
||||
MODULE_DESCRIPTION("ASoC AW88395 Smart PA Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
//
|
||||
// aw88395.h -- ALSA SoC AW88395 codec support
|
||||
//
|
||||
// Copyright (c) 2022-2023 AWINIC Technology CO., LTD
|
||||
//
|
||||
// Author: Bruce zhao <zhaolei@awinic.com>
|
||||
//
|
||||
|
||||
#ifndef __AW88395_H__
|
||||
#define __AW88395_H__
|
||||
|
||||
#define AW88395_CHIP_ID_REG (0x00)
|
||||
#define AW88395_START_RETRIES (5)
|
||||
#define AW88395_START_WORK_DELAY_MS (0)
|
||||
|
||||
#define AW88395_DSP_16_DATA_MASK (0x0000ffff)
|
||||
|
||||
#define AW88395_I2C_NAME "aw88395_smartpa"
|
||||
|
||||
#define AW88395_RATES (SNDRV_PCM_RATE_8000_48000 | \
|
||||
SNDRV_PCM_RATE_96000)
|
||||
#define AW88395_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
|
||||
SNDRV_PCM_FMTBIT_S24_LE | \
|
||||
SNDRV_PCM_FMTBIT_S32_LE)
|
||||
|
||||
#define FADE_TIME_MAX 100000
|
||||
#define FADE_TIME_MIN 0
|
||||
|
||||
#define AW88395_PROFILE_EXT(xname, profile_info, profile_get, profile_set) \
|
||||
{ \
|
||||
.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
|
||||
.name = xname, \
|
||||
.info = profile_info, \
|
||||
.get = profile_get, \
|
||||
.put = profile_set, \
|
||||
}
|
||||
|
||||
enum {
|
||||
AW88395_SYNC_START = 0,
|
||||
AW88395_ASYNC_START,
|
||||
};
|
||||
|
||||
enum {
|
||||
AW88395_STREAM_CLOSE = 0,
|
||||
AW88395_STREAM_OPEN,
|
||||
};
|
||||
|
||||
struct aw88395 {
|
||||
struct aw_device *aw_pa;
|
||||
struct mutex lock;
|
||||
struct gpio_desc *reset_gpio;
|
||||
struct delayed_work start_work;
|
||||
struct regmap *regmap;
|
||||
struct aw_container *aw_cfg;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,142 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
//
|
||||
// aw883_data_type.h -- The data type of the AW88395 chip
|
||||
//
|
||||
// Copyright (c) 2022-2023 AWINIC Technology CO., LTD
|
||||
//
|
||||
// Author: Bruce zhao <zhaolei@awinic.com>
|
||||
//
|
||||
|
||||
#ifndef __AW88395_DATA_TYPE_H__
|
||||
#define __AW88395_DATA_TYPE_H__
|
||||
|
||||
#define PROJECT_NAME_MAX (24)
|
||||
#define CUSTOMER_NAME_MAX (16)
|
||||
#define CFG_VERSION_MAX (4)
|
||||
#define DEV_NAME_MAX (16)
|
||||
#define PROFILE_STR_MAX (32)
|
||||
|
||||
#define ACF_FILE_ID (0xa15f908)
|
||||
|
||||
enum aw_cfg_hdr_version {
|
||||
AW88395_CFG_HDR_VER = 0x00000001,
|
||||
AW88395_CFG_HDR_VER_V1 = 0x01000000,
|
||||
};
|
||||
|
||||
enum aw_cfg_dde_type {
|
||||
AW88395_DEV_NONE_TYPE_ID = 0xFFFFFFFF,
|
||||
AW88395_DEV_TYPE_ID = 0x00000000,
|
||||
AW88395_SKT_TYPE_ID = 0x00000001,
|
||||
AW88395_DEV_DEFAULT_TYPE_ID = 0x00000002,
|
||||
};
|
||||
|
||||
enum aw_sec_type {
|
||||
ACF_SEC_TYPE_REG = 0,
|
||||
ACF_SEC_TYPE_DSP,
|
||||
ACF_SEC_TYPE_DSP_CFG,
|
||||
ACF_SEC_TYPE_DSP_FW,
|
||||
ACF_SEC_TYPE_HDR_REG,
|
||||
ACF_SEC_TYPE_HDR_DSP_CFG,
|
||||
ACF_SEC_TYPE_HDR_DSP_FW,
|
||||
ACF_SEC_TYPE_MULTIPLE_BIN,
|
||||
ACF_SEC_TYPE_SKT_PROJECT,
|
||||
ACF_SEC_TYPE_DSP_PROJECT,
|
||||
ACF_SEC_TYPE_MONITOR,
|
||||
ACF_SEC_TYPE_MAX,
|
||||
};
|
||||
|
||||
enum profile_data_type {
|
||||
AW88395_DATA_TYPE_REG = 0,
|
||||
AW88395_DATA_TYPE_DSP_CFG,
|
||||
AW88395_DATA_TYPE_DSP_FW,
|
||||
AW88395_DATA_TYPE_MAX,
|
||||
};
|
||||
|
||||
enum aw_prof_type {
|
||||
AW88395_PROFILE_MUSIC = 0,
|
||||
AW88395_PROFILE_VOICE,
|
||||
AW88395_PROFILE_VOIP,
|
||||
AW88395_PROFILE_RINGTONE,
|
||||
AW88395_PROFILE_RINGTONE_HS,
|
||||
AW88395_PROFILE_LOWPOWER,
|
||||
AW88395_PROFILE_BYPASS,
|
||||
AW88395_PROFILE_MMI,
|
||||
AW88395_PROFILE_FM,
|
||||
AW88395_PROFILE_NOTIFICATION,
|
||||
AW88395_PROFILE_RECEIVER,
|
||||
AW88395_PROFILE_MAX,
|
||||
};
|
||||
|
||||
enum aw_profile_status {
|
||||
AW88395_PROFILE_WAIT = 0,
|
||||
AW88395_PROFILE_OK,
|
||||
};
|
||||
|
||||
struct aw_cfg_hdr {
|
||||
u32 id;
|
||||
char project[PROJECT_NAME_MAX];
|
||||
char custom[CUSTOMER_NAME_MAX];
|
||||
char version[CFG_VERSION_MAX];
|
||||
u32 author_id;
|
||||
u32 ddt_size;
|
||||
u32 ddt_num;
|
||||
u32 hdr_offset;
|
||||
u32 hdr_version;
|
||||
u32 reserved[3];
|
||||
};
|
||||
|
||||
struct aw_cfg_dde {
|
||||
u32 type;
|
||||
char dev_name[DEV_NAME_MAX];
|
||||
u16 dev_index;
|
||||
u16 dev_bus;
|
||||
u16 dev_addr;
|
||||
u16 dev_profile;
|
||||
u32 data_type;
|
||||
u32 data_size;
|
||||
u32 data_offset;
|
||||
u32 data_crc;
|
||||
u32 reserved[5];
|
||||
};
|
||||
|
||||
struct aw_cfg_dde_v1 {
|
||||
u32 type;
|
||||
char dev_name[DEV_NAME_MAX];
|
||||
u16 dev_index;
|
||||
u16 dev_bus;
|
||||
u16 dev_addr;
|
||||
u16 dev_profile;
|
||||
u32 data_type;
|
||||
u32 data_size;
|
||||
u32 data_offset;
|
||||
u32 data_crc;
|
||||
char dev_profile_str[PROFILE_STR_MAX];
|
||||
u32 chip_id;
|
||||
u32 reserved[4];
|
||||
};
|
||||
|
||||
struct aw_sec_data_desc {
|
||||
u32 len;
|
||||
u8 *data;
|
||||
};
|
||||
|
||||
struct aw_prof_desc {
|
||||
u32 id;
|
||||
u32 prof_st;
|
||||
char *prf_str;
|
||||
u32 fw_ver;
|
||||
struct aw_sec_data_desc sec_desc[AW88395_DATA_TYPE_MAX];
|
||||
};
|
||||
|
||||
struct aw_all_prof_info {
|
||||
struct aw_prof_desc prof_desc[AW88395_PROFILE_MAX];
|
||||
};
|
||||
|
||||
struct aw_prof_info {
|
||||
int count;
|
||||
int prof_type;
|
||||
char **prof_name_list;
|
||||
struct aw_prof_desc *prof_desc;
|
||||
};
|
||||
|
||||
#endif
|
||||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -0,0 +1,194 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
//
|
||||
// aw88395_device.h -- AW88395 function for ALSA Audio Driver
|
||||
//
|
||||
// Copyright (c) 2022-2023 AWINIC Technology CO., LTD
|
||||
//
|
||||
// Author: Bruce zhao <zhaolei@awinic.com>
|
||||
//
|
||||
|
||||
#ifndef __AW88395_DEVICE_FILE_H__
|
||||
#define __AW88395_DEVICE_FILE_H__
|
||||
|
||||
#include "aw88395.h"
|
||||
#include "aw88395_data_type.h"
|
||||
#include "aw88395_lib.h"
|
||||
|
||||
#define AW88395_DEV_DEFAULT_CH (0)
|
||||
#define AW88395_DEV_DSP_CHECK_MAX (5)
|
||||
#define AW88395_DSP_I2C_WRITES
|
||||
#define AW88395_MAX_RAM_WRITE_BYTE_SIZE (128)
|
||||
#define AW88395_DSP_ODD_NUM_BIT_TEST (0x5555)
|
||||
#define AW88395_DSP_EVEN_NUM_BIT_TEST (0xAAAA)
|
||||
#define AW88395_DSP_ST_CHECK_MAX (2)
|
||||
#define AW88395_FADE_IN_OUT_DEFAULT (0)
|
||||
#define AW88395_CALI_RE_MAX (15000)
|
||||
#define AW88395_CALI_RE_MIN (4000)
|
||||
#define AW88395_CALI_DELAY_CACL(value) ((value * 32) / 48)
|
||||
|
||||
#define AW88395_DSP_RE_TO_SHOW_RE(re, shift) (((re) * (1000)) >> (shift))
|
||||
#define AW88395_SHOW_RE_TO_DSP_RE(re, shift) (((re) << shift) / (1000))
|
||||
|
||||
#define AW88395_ACF_FILE "aw88395_acf.bin"
|
||||
#define AW88395_DEV_SYSST_CHECK_MAX (10)
|
||||
|
||||
enum {
|
||||
AW88395_DEV_VDSEL_DAC = 0,
|
||||
AW88395_DEV_VDSEL_VSENSE = 1,
|
||||
};
|
||||
|
||||
enum {
|
||||
AW88395_DSP_CRC_NA = 0,
|
||||
AW88395_DSP_CRC_OK = 1,
|
||||
};
|
||||
|
||||
enum {
|
||||
AW88395_DSP_FW_UPDATE_OFF = 0,
|
||||
AW88395_DSP_FW_UPDATE_ON = 1,
|
||||
};
|
||||
|
||||
enum {
|
||||
AW88395_FORCE_UPDATE_OFF = 0,
|
||||
AW88395_FORCE_UPDATE_ON = 1,
|
||||
};
|
||||
|
||||
enum {
|
||||
AW88395_1000_US = 1000,
|
||||
AW88395_2000_US = 2000,
|
||||
AW88395_3000_US = 3000,
|
||||
AW88395_4000_US = 4000,
|
||||
AW88395_5000_US = 5000,
|
||||
AW88395_10000_US = 10000,
|
||||
AW88395_100000_US = 100000,
|
||||
};
|
||||
|
||||
enum {
|
||||
AW88395_DEV_TYPE_OK = 0,
|
||||
AW88395_DEV_TYPE_NONE = 1,
|
||||
};
|
||||
|
||||
|
||||
enum AW88395_DEV_STATUS {
|
||||
AW88395_DEV_PW_OFF = 0,
|
||||
AW88395_DEV_PW_ON,
|
||||
};
|
||||
|
||||
enum AW88395_DEV_FW_STATUS {
|
||||
AW88395_DEV_FW_FAILED = 0,
|
||||
AW88395_DEV_FW_OK,
|
||||
};
|
||||
|
||||
enum AW88395_DEV_MEMCLK {
|
||||
AW88395_DEV_MEMCLK_OSC = 0,
|
||||
AW88395_DEV_MEMCLK_PLL = 1,
|
||||
};
|
||||
|
||||
enum AW88395_DEV_DSP_CFG {
|
||||
AW88395_DEV_DSP_WORK = 0,
|
||||
AW88395_DEV_DSP_BYPASS = 1,
|
||||
};
|
||||
|
||||
enum {
|
||||
AW88395_DSP_16_DATA = 0,
|
||||
AW88395_DSP_32_DATA = 1,
|
||||
};
|
||||
|
||||
enum {
|
||||
AW88395_NOT_RCV_MODE = 0,
|
||||
AW88395_RCV_MODE = 1,
|
||||
};
|
||||
|
||||
struct aw_profctrl_desc {
|
||||
unsigned int cur_mode;
|
||||
};
|
||||
|
||||
struct aw_volume_desc {
|
||||
unsigned int init_volume;
|
||||
unsigned int mute_volume;
|
||||
unsigned int ctl_volume;
|
||||
unsigned int max_volume;
|
||||
};
|
||||
|
||||
struct aw_dsp_mem_desc {
|
||||
unsigned int dsp_madd_reg;
|
||||
unsigned int dsp_mdat_reg;
|
||||
unsigned int dsp_fw_base_addr;
|
||||
unsigned int dsp_cfg_base_addr;
|
||||
};
|
||||
|
||||
struct aw_vmax_desc {
|
||||
unsigned int init_vmax;
|
||||
};
|
||||
|
||||
struct aw_cali_delay_desc {
|
||||
unsigned int delay;
|
||||
};
|
||||
|
||||
struct aw_cali_desc {
|
||||
u32 cali_re;
|
||||
u32 ra;
|
||||
};
|
||||
|
||||
struct aw_container {
|
||||
int len;
|
||||
u8 data[];
|
||||
};
|
||||
|
||||
struct aw_device {
|
||||
int status;
|
||||
struct mutex dsp_lock;
|
||||
|
||||
unsigned char prof_cur;
|
||||
unsigned char prof_index;
|
||||
unsigned char dsp_crc_st;
|
||||
u16 chip_id;
|
||||
|
||||
unsigned int channel;
|
||||
unsigned int fade_step;
|
||||
|
||||
struct i2c_client *i2c;
|
||||
struct device *dev;
|
||||
struct regmap *regmap;
|
||||
char *acf;
|
||||
|
||||
u32 fade_en;
|
||||
unsigned char dsp_cfg;
|
||||
|
||||
u32 dsp_fw_len;
|
||||
u32 dsp_cfg_len;
|
||||
u8 platform;
|
||||
u8 fw_status;
|
||||
|
||||
unsigned int fade_in_time;
|
||||
unsigned int fade_out_time;
|
||||
|
||||
struct aw_prof_info prof_info;
|
||||
struct aw_sec_data_desc crc_dsp_cfg;
|
||||
struct aw_profctrl_desc profctrl_desc;
|
||||
struct aw_volume_desc volume_desc;
|
||||
struct aw_dsp_mem_desc dsp_mem_desc;
|
||||
struct aw_vmax_desc vmax_desc;
|
||||
|
||||
struct aw_cali_delay_desc cali_delay_desc;
|
||||
struct aw_cali_desc cali_desc;
|
||||
|
||||
};
|
||||
|
||||
int aw88395_init(struct aw_device **aw_dev, struct i2c_client *i2c, struct regmap *regmap);
|
||||
int aw88395_dev_init(struct aw_device *aw_dev, struct aw_container *aw_cfg);
|
||||
int aw88395_dev_start(struct aw_device *aw_dev);
|
||||
int aw88395_dev_stop(struct aw_device *aw_dev);
|
||||
int aw88395_dev_fw_update(struct aw_device *aw_dev, bool up_dsp_fw_en, bool force_up_en);
|
||||
|
||||
void aw88395_dev_set_volume(struct aw_device *aw_dev, unsigned short set_vol);
|
||||
int aw88395_dev_get_prof_data(struct aw_device *aw_dev, int index,
|
||||
struct aw_prof_desc **prof_desc);
|
||||
char *aw88395_dev_get_prof_name(struct aw_device *aw_dev, int index);
|
||||
int aw88395_dev_set_profile_index(struct aw_device *aw_dev, int index);
|
||||
int aw88395_dev_get_profile_index(struct aw_device *aw_dev);
|
||||
int aw88395_dev_get_profile_count(struct aw_device *aw_dev);
|
||||
int aw88395_dev_load_acf_check(struct aw_device *aw_dev, struct aw_container *aw_cfg);
|
||||
int aw88395_dev_cfg_load(struct aw_device *aw_dev, struct aw_container *aw_cfg);
|
||||
void aw88395_dev_mute(struct aw_device *aw_dev, bool is_mute);
|
||||
|
||||
#endif
|
||||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -0,0 +1,92 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
//
|
||||
// aw88395_lib.h -- ACF bin parsing and check library file for aw88395
|
||||
//
|
||||
// Copyright (c) 2022-2023 AWINIC Technology CO., LTD
|
||||
//
|
||||
// Author: Bruce zhao <zhaolei@awinic.com>
|
||||
//
|
||||
|
||||
#ifndef __AW88395_LIB_H__
|
||||
#define __AW88395_LIB_H__
|
||||
|
||||
#define CHECK_REGISTER_NUM_OFFSET (4)
|
||||
#define VALID_DATA_LEN (4)
|
||||
#define VALID_DATA_ADDR (4)
|
||||
#define PARSE_DSP_REG_NUM (4)
|
||||
#define REG_DATA_BYTP_LEN (8)
|
||||
#define CHECK_DSP_REG_NUM (12)
|
||||
#define DSP_VALID_DATA_LEN (12)
|
||||
#define DSP_VALID_DATA_ADDR (12)
|
||||
#define PARSE_SOC_APP_NUM (8)
|
||||
#define CHECK_SOC_APP_NUM (12)
|
||||
#define APP_DOWNLOAD_ADDR (4)
|
||||
#define APP_VALID_DATA_LEN (12)
|
||||
#define APP_VALID_DATA_ADDR (12)
|
||||
#define BIN_NUM_MAX (100)
|
||||
#define HEADER_LEN (60)
|
||||
#define BIN_DATA_TYPE_OFFSET (8)
|
||||
#define DATA_LEN (44)
|
||||
#define VALID_DATA_ADDR_OFFSET (60)
|
||||
#define START_ADDR_OFFSET (64)
|
||||
|
||||
#define AW88395_FW_CHECK_PART (10)
|
||||
#define HDADER_LEN (60)
|
||||
|
||||
#define HEADER_VERSION_OFFSET (4)
|
||||
|
||||
enum bin_header_version_enum {
|
||||
HEADER_VERSION_V1 = 0x01000000,
|
||||
};
|
||||
|
||||
enum data_type_enum {
|
||||
DATA_TYPE_REGISTER = 0x00000000,
|
||||
DATA_TYPE_DSP_REG = 0x00000010,
|
||||
DATA_TYPE_DSP_CFG = 0x00000011,
|
||||
DATA_TYPE_SOC_REG = 0x00000020,
|
||||
DATA_TYPE_SOC_APP = 0x00000021,
|
||||
DATA_TYPE_DSP_FW = 0x00000022,
|
||||
DATA_TYPE_MULTI_BINS = 0x00002000,
|
||||
};
|
||||
|
||||
enum data_version_enum {
|
||||
DATA_VERSION_V1 = 0x00000001,
|
||||
DATA_VERSION_MAX,
|
||||
};
|
||||
|
||||
struct bin_header_info {
|
||||
unsigned int check_sum;
|
||||
unsigned int header_ver;
|
||||
unsigned int bin_data_type;
|
||||
unsigned int bin_data_ver;
|
||||
unsigned int bin_data_len;
|
||||
unsigned int ui_ver;
|
||||
unsigned char chip_type[8];
|
||||
unsigned int reg_byte_len;
|
||||
unsigned int data_byte_len;
|
||||
unsigned int device_addr;
|
||||
unsigned int valid_data_len;
|
||||
unsigned int valid_data_addr;
|
||||
|
||||
unsigned int reg_num;
|
||||
unsigned int reg_data_byte_len;
|
||||
unsigned int download_addr;
|
||||
unsigned int app_version;
|
||||
unsigned int header_len;
|
||||
};
|
||||
|
||||
struct bin_container {
|
||||
unsigned int len;
|
||||
unsigned char data[];
|
||||
};
|
||||
|
||||
struct aw_bin {
|
||||
unsigned char *p_addr;
|
||||
unsigned int all_bin_parse_num;
|
||||
unsigned int multi_bin_parse_num;
|
||||
unsigned int single_bin_parse_num;
|
||||
struct bin_header_info header_info[BIN_NUM_MAX];
|
||||
struct bin_container info;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,383 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
//
|
||||
// aw88395_reg.h -- AW88395 chip register file
|
||||
//
|
||||
// Copyright (c) 2022-2023 AWINIC Technology CO., LTD
|
||||
//
|
||||
// Author: Bruce zhao <zhaolei@awinic.com>
|
||||
//
|
||||
|
||||
#ifndef __AW88395_REG_H__
|
||||
#define __AW88395_REG_H__
|
||||
|
||||
#define AW88395_ID_REG (0x00)
|
||||
#define AW88395_SYSST_REG (0x01)
|
||||
#define AW88395_SYSINT_REG (0x02)
|
||||
#define AW88395_SYSINTM_REG (0x03)
|
||||
#define AW88395_SYSCTRL_REG (0x04)
|
||||
#define AW88395_SYSCTRL2_REG (0x05)
|
||||
#define AW88395_I2SCTRL_REG (0x06)
|
||||
#define AW88395_I2SCFG1_REG (0x07)
|
||||
#define AW88395_I2SCFG2_REG (0x08)
|
||||
#define AW88395_HAGCCFG1_REG (0x09)
|
||||
#define AW88395_HAGCCFG2_REG (0x0A)
|
||||
#define AW88395_HAGCCFG3_REG (0x0B)
|
||||
#define AW88395_HAGCCFG4_REG (0x0C)
|
||||
#define AW88395_HAGCCFG5_REG (0x0D)
|
||||
#define AW88395_HAGCCFG6_REG (0x0E)
|
||||
#define AW88395_HAGCCFG7_REG (0x0F)
|
||||
#define AW88395_MPDCFG_REG (0x10)
|
||||
#define AW88395_PWMCTRL_REG (0x11)
|
||||
#define AW88395_I2SCFG3_REG (0x12)
|
||||
#define AW88395_DBGCTRL_REG (0x13)
|
||||
#define AW88395_HAGCST_REG (0x20)
|
||||
#define AW88395_VBAT_REG (0x21)
|
||||
#define AW88395_TEMP_REG (0x22)
|
||||
#define AW88395_PVDD_REG (0x23)
|
||||
#define AW88395_ISNDAT_REG (0x24)
|
||||
#define AW88395_VSNDAT_REG (0x25)
|
||||
#define AW88395_I2SINT_REG (0x26)
|
||||
#define AW88395_I2SCAPCNT_REG (0x27)
|
||||
#define AW88395_ANASTA1_REG (0x28)
|
||||
#define AW88395_ANASTA2_REG (0x29)
|
||||
#define AW88395_ANASTA3_REG (0x2A)
|
||||
#define AW88395_ANASTA4_REG (0x2B)
|
||||
#define AW88395_TESTDET_REG (0x2C)
|
||||
#define AW88395_TESTIN_REG (0x38)
|
||||
#define AW88395_TESTOUT_REG (0x39)
|
||||
#define AW88395_DSPMADD_REG (0x40)
|
||||
#define AW88395_DSPMDAT_REG (0x41)
|
||||
#define AW88395_WDT_REG (0x42)
|
||||
#define AW88395_ACR1_REG (0x43)
|
||||
#define AW88395_ACR2_REG (0x44)
|
||||
#define AW88395_ASR1_REG (0x45)
|
||||
#define AW88395_ASR2_REG (0x46)
|
||||
#define AW88395_DSPCFG_REG (0x47)
|
||||
#define AW88395_ASR3_REG (0x48)
|
||||
#define AW88395_ASR4_REG (0x49)
|
||||
#define AW88395_VSNCTRL1_REG (0x50)
|
||||
#define AW88395_ISNCTRL1_REG (0x51)
|
||||
#define AW88395_PLLCTRL1_REG (0x52)
|
||||
#define AW88395_PLLCTRL2_REG (0x53)
|
||||
#define AW88395_PLLCTRL3_REG (0x54)
|
||||
#define AW88395_CDACTRL1_REG (0x55)
|
||||
#define AW88395_CDACTRL2_REG (0x56)
|
||||
#define AW88395_SADCCTRL1_REG (0x57)
|
||||
#define AW88395_SADCCTRL2_REG (0x58)
|
||||
#define AW88395_CPCTRL1_REG (0x59)
|
||||
#define AW88395_BSTCTRL1_REG (0x60)
|
||||
#define AW88395_BSTCTRL2_REG (0x61)
|
||||
#define AW88395_BSTCTRL3_REG (0x62)
|
||||
#define AW88395_BSTCTRL4_REG (0x63)
|
||||
#define AW88395_BSTCTRL5_REG (0x64)
|
||||
#define AW88395_BSTCTRL6_REG (0x65)
|
||||
#define AW88395_BSTCTRL7_REG (0x66)
|
||||
#define AW88395_DSMCFG1_REG (0x67)
|
||||
#define AW88395_DSMCFG2_REG (0x68)
|
||||
#define AW88395_DSMCFG3_REG (0x69)
|
||||
#define AW88395_DSMCFG4_REG (0x6A)
|
||||
#define AW88395_DSMCFG5_REG (0x6B)
|
||||
#define AW88395_DSMCFG6_REG (0x6C)
|
||||
#define AW88395_DSMCFG7_REG (0x6D)
|
||||
#define AW88395_DSMCFG8_REG (0x6E)
|
||||
#define AW88395_TESTCTRL1_REG (0x70)
|
||||
#define AW88395_TESTCTRL2_REG (0x71)
|
||||
#define AW88395_EFCTRL1_REG (0x72)
|
||||
#define AW88395_EFCTRL2_REG (0x73)
|
||||
#define AW88395_EFWH_REG (0x74)
|
||||
#define AW88395_EFWM2_REG (0x75)
|
||||
#define AW88395_EFWM1_REG (0x76)
|
||||
#define AW88395_EFWL_REG (0x77)
|
||||
#define AW88395_EFRH_REG (0x78)
|
||||
#define AW88395_EFRM2_REG (0x79)
|
||||
#define AW88395_EFRM1_REG (0x7A)
|
||||
#define AW88395_EFRL_REG (0x7B)
|
||||
#define AW88395_TM_REG (0x7C)
|
||||
|
||||
enum aw88395_id {
|
||||
AW88395_CHIP_ID = 0x2049,
|
||||
};
|
||||
|
||||
#define AW88395_REG_MAX (0x7D)
|
||||
|
||||
#define AW88395_VOLUME_STEP_DB (6 * 8)
|
||||
|
||||
#define AW88395_UVLS_START_BIT (14)
|
||||
#define AW88395_UVLS_NORMAL (0)
|
||||
#define AW88395_UVLS_NORMAL_VALUE \
|
||||
(AW88395_UVLS_NORMAL << AW88395_UVLS_START_BIT)
|
||||
|
||||
#define AW88395_DSPS_START_BIT (12)
|
||||
#define AW88395_DSPS_BITS_LEN (1)
|
||||
#define AW88395_DSPS_MASK \
|
||||
(~(((1<<AW88395_DSPS_BITS_LEN)-1) << AW88395_DSPS_START_BIT))
|
||||
|
||||
#define AW88395_DSPS_NORMAL (0)
|
||||
#define AW88395_DSPS_NORMAL_VALUE \
|
||||
(AW88395_DSPS_NORMAL << AW88395_DSPS_START_BIT)
|
||||
|
||||
#define AW88395_BSTOCS_START_BIT (11)
|
||||
#define AW88395_BSTOCS_OVER_CURRENT (1)
|
||||
#define AW88395_BSTOCS_OVER_CURRENT_VALUE \
|
||||
(AW88395_BSTOCS_OVER_CURRENT << AW88395_BSTOCS_START_BIT)
|
||||
|
||||
#define AW88395_BSTS_START_BIT (9)
|
||||
#define AW88395_BSTS_FINISHED (1)
|
||||
#define AW88395_BSTS_FINISHED_VALUE \
|
||||
(AW88395_BSTS_FINISHED << AW88395_BSTS_START_BIT)
|
||||
|
||||
#define AW88395_SWS_START_BIT (8)
|
||||
#define AW88395_SWS_SWITCHING (1)
|
||||
#define AW88395_SWS_SWITCHING_VALUE \
|
||||
(AW88395_SWS_SWITCHING << AW88395_SWS_START_BIT)
|
||||
|
||||
#define AW88395_NOCLKS_START_BIT (5)
|
||||
#define AW88395_NOCLKS_NO_CLOCK (1)
|
||||
#define AW88395_NOCLKS_NO_CLOCK_VALUE \
|
||||
(AW88395_NOCLKS_NO_CLOCK << AW88395_NOCLKS_START_BIT)
|
||||
|
||||
#define AW88395_CLKS_START_BIT (4)
|
||||
#define AW88395_CLKS_STABLE (1)
|
||||
#define AW88395_CLKS_STABLE_VALUE \
|
||||
(AW88395_CLKS_STABLE << AW88395_CLKS_START_BIT)
|
||||
|
||||
#define AW88395_OCDS_START_BIT (3)
|
||||
#define AW88395_OCDS_OC (1)
|
||||
#define AW88395_OCDS_OC_VALUE \
|
||||
(AW88395_OCDS_OC << AW88395_OCDS_START_BIT)
|
||||
|
||||
#define AW88395_OTHS_START_BIT (1)
|
||||
#define AW88395_OTHS_OT (1)
|
||||
#define AW88395_OTHS_OT_VALUE \
|
||||
(AW88395_OTHS_OT << AW88395_OTHS_START_BIT)
|
||||
|
||||
#define AW88395_PLLS_START_BIT (0)
|
||||
#define AW88395_PLLS_LOCKED (1)
|
||||
#define AW88395_PLLS_LOCKED_VALUE \
|
||||
(AW88395_PLLS_LOCKED << AW88395_PLLS_START_BIT)
|
||||
|
||||
#define AW88395_BIT_PLL_CHECK \
|
||||
(AW88395_CLKS_STABLE_VALUE | \
|
||||
AW88395_PLLS_LOCKED_VALUE)
|
||||
|
||||
#define AW88395_BIT_SYSST_CHECK_MASK \
|
||||
(~(AW88395_UVLS_NORMAL_VALUE | \
|
||||
AW88395_BSTOCS_OVER_CURRENT_VALUE | \
|
||||
AW88395_BSTS_FINISHED_VALUE | \
|
||||
AW88395_SWS_SWITCHING_VALUE | \
|
||||
AW88395_NOCLKS_NO_CLOCK_VALUE | \
|
||||
AW88395_CLKS_STABLE_VALUE | \
|
||||
AW88395_OCDS_OC_VALUE | \
|
||||
AW88395_OTHS_OT_VALUE | \
|
||||
AW88395_PLLS_LOCKED_VALUE))
|
||||
|
||||
#define AW88395_BIT_SYSST_CHECK \
|
||||
(AW88395_BSTS_FINISHED_VALUE | \
|
||||
AW88395_SWS_SWITCHING_VALUE | \
|
||||
AW88395_CLKS_STABLE_VALUE | \
|
||||
AW88395_PLLS_LOCKED_VALUE)
|
||||
|
||||
#define AW88395_WDI_START_BIT (6)
|
||||
#define AW88395_WDI_INT_VALUE (1)
|
||||
#define AW88395_WDI_INTERRUPT \
|
||||
(AW88395_WDI_INT_VALUE << AW88395_WDI_START_BIT)
|
||||
|
||||
#define AW88395_NOCLKI_START_BIT (5)
|
||||
#define AW88395_NOCLKI_INT_VALUE (1)
|
||||
#define AW88395_NOCLKI_INTERRUPT \
|
||||
(AW88395_NOCLKI_INT_VALUE << AW88395_NOCLKI_START_BIT)
|
||||
|
||||
#define AW88395_CLKI_START_BIT (4)
|
||||
#define AW88395_CLKI_INT_VALUE (1)
|
||||
#define AW88395_CLKI_INTERRUPT \
|
||||
(AW88395_CLKI_INT_VALUE << AW88395_CLKI_START_BIT)
|
||||
|
||||
#define AW88395_PLLI_START_BIT (0)
|
||||
#define AW88395_PLLI_INT_VALUE (1)
|
||||
#define AW88395_PLLI_INTERRUPT \
|
||||
(AW88395_PLLI_INT_VALUE << AW88395_PLLI_START_BIT)
|
||||
|
||||
#define AW88395_BIT_SYSINT_CHECK \
|
||||
(AW88395_WDI_INTERRUPT | \
|
||||
AW88395_CLKI_INTERRUPT | \
|
||||
AW88395_NOCLKI_INTERRUPT | \
|
||||
AW88395_PLLI_INTERRUPT)
|
||||
|
||||
#define AW88395_HMUTE_START_BIT (8)
|
||||
#define AW88395_HMUTE_BITS_LEN (1)
|
||||
#define AW88395_HMUTE_MASK \
|
||||
(~(((1<<AW88395_HMUTE_BITS_LEN)-1) << AW88395_HMUTE_START_BIT))
|
||||
|
||||
#define AW88395_HMUTE_DISABLE (0)
|
||||
#define AW88395_HMUTE_DISABLE_VALUE \
|
||||
(AW88395_HMUTE_DISABLE << AW88395_HMUTE_START_BIT)
|
||||
|
||||
#define AW88395_HMUTE_ENABLE (1)
|
||||
#define AW88395_HMUTE_ENABLE_VALUE \
|
||||
(AW88395_HMUTE_ENABLE << AW88395_HMUTE_START_BIT)
|
||||
|
||||
#define AW88395_RCV_MODE_START_BIT (7)
|
||||
#define AW88395_RCV_MODE_BITS_LEN (1)
|
||||
#define AW88395_RCV_MODE_MASK \
|
||||
(~(((1<<AW88395_RCV_MODE_BITS_LEN)-1) << AW88395_RCV_MODE_START_BIT))
|
||||
|
||||
#define AW88395_RCV_MODE_RECEIVER (1)
|
||||
#define AW88395_RCV_MODE_RECEIVER_VALUE \
|
||||
(AW88395_RCV_MODE_RECEIVER << AW88395_RCV_MODE_START_BIT)
|
||||
|
||||
#define AW88395_DSPBY_START_BIT (2)
|
||||
#define AW88395_DSPBY_BITS_LEN (1)
|
||||
#define AW88395_DSPBY_MASK \
|
||||
(~(((1<<AW88395_DSPBY_BITS_LEN)-1) << AW88395_DSPBY_START_BIT))
|
||||
|
||||
#define AW88395_DSPBY_WORKING (0)
|
||||
#define AW88395_DSPBY_WORKING_VALUE \
|
||||
(AW88395_DSPBY_WORKING << AW88395_DSPBY_START_BIT)
|
||||
|
||||
#define AW88395_DSPBY_BYPASS (1)
|
||||
#define AW88395_DSPBY_BYPASS_VALUE \
|
||||
(AW88395_DSPBY_BYPASS << AW88395_DSPBY_START_BIT)
|
||||
|
||||
#define AW88395_AMPPD_START_BIT (1)
|
||||
#define AW88395_AMPPD_BITS_LEN (1)
|
||||
#define AW88395_AMPPD_MASK \
|
||||
(~(((1<<AW88395_AMPPD_BITS_LEN)-1) << AW88395_AMPPD_START_BIT))
|
||||
|
||||
#define AW88395_AMPPD_WORKING (0)
|
||||
#define AW88395_AMPPD_WORKING_VALUE \
|
||||
(AW88395_AMPPD_WORKING << AW88395_AMPPD_START_BIT)
|
||||
|
||||
#define AW88395_AMPPD_POWER_DOWN (1)
|
||||
#define AW88395_AMPPD_POWER_DOWN_VALUE \
|
||||
(AW88395_AMPPD_POWER_DOWN << AW88395_AMPPD_START_BIT)
|
||||
|
||||
#define AW88395_PWDN_START_BIT (0)
|
||||
#define AW88395_PWDN_BITS_LEN (1)
|
||||
#define AW88395_PWDN_MASK \
|
||||
(~(((1<<AW88395_PWDN_BITS_LEN)-1) << AW88395_PWDN_START_BIT))
|
||||
|
||||
#define AW88395_PWDN_WORKING (0)
|
||||
#define AW88395_PWDN_WORKING_VALUE \
|
||||
(AW88395_PWDN_WORKING << AW88395_PWDN_START_BIT)
|
||||
|
||||
#define AW88395_PWDN_POWER_DOWN (1)
|
||||
#define AW88395_PWDN_POWER_DOWN_VALUE \
|
||||
(AW88395_PWDN_POWER_DOWN << AW88395_PWDN_START_BIT)
|
||||
|
||||
#define AW88395_MUTE_VOL (90 * 8)
|
||||
#define AW88395_VOLUME_STEP_DB (6 * 8)
|
||||
|
||||
#define AW88395_VOL_6DB_START (6)
|
||||
#define AW88395_VOL_START_BIT (6)
|
||||
#define AW88395_VOL_BITS_LEN (10)
|
||||
#define AW88395_VOL_MASK \
|
||||
(~(((1<<AW88395_VOL_BITS_LEN)-1) << AW88395_VOL_START_BIT))
|
||||
|
||||
#define AW88395_VOL_DEFAULT_VALUE (0)
|
||||
|
||||
#define AW88395_I2STXEN_START_BIT (0)
|
||||
#define AW88395_I2STXEN_BITS_LEN (1)
|
||||
#define AW88395_I2STXEN_MASK \
|
||||
(~(((1<<AW88395_I2STXEN_BITS_LEN)-1) << AW88395_I2STXEN_START_BIT))
|
||||
|
||||
#define AW88395_I2STXEN_DISABLE (0)
|
||||
#define AW88395_I2STXEN_DISABLE_VALUE \
|
||||
(AW88395_I2STXEN_DISABLE << AW88395_I2STXEN_START_BIT)
|
||||
|
||||
#define AW88395_I2STXEN_ENABLE (1)
|
||||
#define AW88395_I2STXEN_ENABLE_VALUE \
|
||||
(AW88395_I2STXEN_ENABLE << AW88395_I2STXEN_START_BIT)
|
||||
|
||||
#define AW88395_AGC_DSP_CTL_START_BIT (15)
|
||||
#define AW88395_AGC_DSP_CTL_BITS_LEN (1)
|
||||
#define AW88395_AGC_DSP_CTL_MASK \
|
||||
(~(((1<<AW88395_AGC_DSP_CTL_BITS_LEN)-1) << AW88395_AGC_DSP_CTL_START_BIT))
|
||||
|
||||
#define AW88395_AGC_DSP_CTL_DISABLE (0)
|
||||
#define AW88395_AGC_DSP_CTL_DISABLE_VALUE \
|
||||
(AW88395_AGC_DSP_CTL_DISABLE << AW88395_AGC_DSP_CTL_START_BIT)
|
||||
|
||||
#define AW88395_AGC_DSP_CTL_ENABLE (1)
|
||||
#define AW88395_AGC_DSP_CTL_ENABLE_VALUE \
|
||||
(AW88395_AGC_DSP_CTL_ENABLE << AW88395_AGC_DSP_CTL_START_BIT)
|
||||
|
||||
#define AW88395_VDSEL_START_BIT (0)
|
||||
#define AW88395_VDSEL_BITS_LEN (1)
|
||||
#define AW88395_VDSEL_MASK \
|
||||
(~(((1<<AW88395_VDSEL_BITS_LEN)-1) << AW88395_VDSEL_START_BIT))
|
||||
|
||||
#define AW88395_MEM_CLKSEL_START_BIT (3)
|
||||
#define AW88395_MEM_CLKSEL_BITS_LEN (1)
|
||||
#define AW88395_MEM_CLKSEL_MASK \
|
||||
(~(((1<<AW88395_MEM_CLKSEL_BITS_LEN)-1) << AW88395_MEM_CLKSEL_START_BIT))
|
||||
|
||||
#define AW88395_MEM_CLKSEL_OSC_CLK (0)
|
||||
#define AW88395_MEM_CLKSEL_OSC_CLK_VALUE \
|
||||
(AW88395_MEM_CLKSEL_OSC_CLK << AW88395_MEM_CLKSEL_START_BIT)
|
||||
|
||||
#define AW88395_MEM_CLKSEL_DAP_HCLK (1)
|
||||
#define AW88395_MEM_CLKSEL_DAP_HCLK_VALUE \
|
||||
(AW88395_MEM_CLKSEL_DAP_HCLK << AW88395_MEM_CLKSEL_START_BIT)
|
||||
|
||||
#define AW88395_CCO_MUX_START_BIT (14)
|
||||
#define AW88395_CCO_MUX_BITS_LEN (1)
|
||||
#define AW88395_CCO_MUX_MASK \
|
||||
(~(((1<<AW88395_CCO_MUX_BITS_LEN)-1) << AW88395_CCO_MUX_START_BIT))
|
||||
|
||||
#define AW88395_CCO_MUX_DIVIDED (0)
|
||||
#define AW88395_CCO_MUX_DIVIDED_VALUE \
|
||||
(AW88395_CCO_MUX_DIVIDED << AW88395_CCO_MUX_START_BIT)
|
||||
|
||||
#define AW88395_CCO_MUX_BYPASS (1)
|
||||
#define AW88395_CCO_MUX_BYPASS_VALUE \
|
||||
(AW88395_CCO_MUX_BYPASS << AW88395_CCO_MUX_START_BIT)
|
||||
|
||||
#define AW88395_EF_VSN_GESLP_START_BIT (0)
|
||||
#define AW88395_EF_VSN_GESLP_BITS_LEN (10)
|
||||
#define AW88395_EF_VSN_GESLP_MASK \
|
||||
(~(((1<<AW88395_EF_VSN_GESLP_BITS_LEN)-1) << AW88395_EF_VSN_GESLP_START_BIT))
|
||||
|
||||
#define AW88395_EF_VSN_GESLP_SIGN_MASK (~(1 << 9))
|
||||
#define AW88395_EF_VSN_GESLP_SIGN_NEG (0xfe00)
|
||||
|
||||
#define AW88395_EF_ISN_GESLP_START_BIT (0)
|
||||
#define AW88395_EF_ISN_GESLP_BITS_LEN (10)
|
||||
#define AW88395_EF_ISN_GESLP_MASK \
|
||||
(~(((1<<AW88395_EF_ISN_GESLP_BITS_LEN)-1) << AW88395_EF_ISN_GESLP_START_BIT))
|
||||
|
||||
#define AW88395_EF_ISN_GESLP_SIGN_MASK (~(1 << 9))
|
||||
#define AW88395_EF_ISN_GESLP_SIGN_NEG (0xfe00)
|
||||
|
||||
#define AW88395_CABL_BASE_VALUE (1000)
|
||||
#define AW88395_ICABLK_FACTOR (1)
|
||||
#define AW88395_VCABLK_FACTOR (1)
|
||||
#define AW88395_VCAL_FACTOR (1 << 12)
|
||||
#define AW88395_VSCAL_FACTOR (16500)
|
||||
#define AW88395_ISCAL_FACTOR (3667)
|
||||
#define AW88395_EF_VSENSE_GAIN_SHIFT (0)
|
||||
|
||||
#define AW88395_VCABLK_FACTOR_DAC (2)
|
||||
#define AW88395_VSCAL_FACTOR_DAC (11790)
|
||||
#define AW88395_EF_DAC_GESLP_SHIFT (10)
|
||||
#define AW88395_EF_DAC_GESLP_SIGN_MASK (1 << 5)
|
||||
#define AW88395_EF_DAC_GESLP_SIGN_NEG (0xffc0)
|
||||
|
||||
#define AW88395_VCALB_ADJ_FACTOR (12)
|
||||
|
||||
#define AW88395_WDT_CNT_START_BIT (0)
|
||||
#define AW88395_WDT_CNT_BITS_LEN (8)
|
||||
#define AW88395_WDT_CNT_MASK \
|
||||
(~(((1<<AW88395_WDT_CNT_BITS_LEN)-1) << AW88395_WDT_CNT_START_BIT))
|
||||
|
||||
#define AW88395_DSP_CFG_ADDR (0x9C80)
|
||||
#define AW88395_DSP_FW_ADDR (0x8C00)
|
||||
#define AW88395_DSP_REG_VMAX (0x9C94)
|
||||
#define AW88395_DSP_REG_CFG_ADPZ_RE (0x9D00)
|
||||
#define AW88395_DSP_REG_VCALB (0x9CF7)
|
||||
#define AW88395_DSP_RE_SHIFT (12)
|
||||
|
||||
#define AW88395_DSP_REG_CFG_ADPZ_RA (0x9D02)
|
||||
#define AW88395_DSP_REG_CRC_ADDR (0x9F42)
|
||||
#define AW88395_DSP_CALI_F0_DELAY (0x9CFD)
|
||||
|
||||
#endif
|
||||
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