KVM: arm64: vgic-v3: Add ICV_BPR0_EL1 handler
Add a handler for reading/writing the guest's view of the ICC_BPR0_EL1 register, which is located in the ICH_VMCR_EL2.BPR0 field. Tested-by: Alexander Graf <agraf@suse.de> Acked-by: David Daney <david.daney@cavium.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Christoffer Dall <cdall@linaro.org> Signed-off-by: Christoffer Dall <cdall@linaro.org>
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@ -180,6 +180,7 @@
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#define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
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#define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
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#define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
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#define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
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#define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
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@ -706,11 +706,33 @@ static void __hyp_text __vgic_v3_write_igrpen1(struct kvm_vcpu *vcpu, u32 vmcr,
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__vgic_v3_write_vmcr(vmcr);
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}
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static void __hyp_text __vgic_v3_read_bpr0(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
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{
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vcpu_set_reg(vcpu, rt, __vgic_v3_get_bpr0(vmcr));
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}
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static void __hyp_text __vgic_v3_read_bpr1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
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{
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vcpu_set_reg(vcpu, rt, __vgic_v3_get_bpr1(vmcr));
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}
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static void __hyp_text __vgic_v3_write_bpr0(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
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{
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u64 val = vcpu_get_reg(vcpu, rt);
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u8 bpr_min = __vgic_v3_bpr_min() - 1;
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/* Enforce BPR limiting */
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if (val < bpr_min)
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val = bpr_min;
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val <<= ICH_VMCR_BPR0_SHIFT;
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val &= ICH_VMCR_BPR0_MASK;
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vmcr &= ~ICH_VMCR_BPR0_MASK;
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vmcr |= val;
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__vgic_v3_write_vmcr(vmcr);
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}
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static void __hyp_text __vgic_v3_write_bpr1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
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{
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u64 val = vcpu_get_reg(vcpu, rt);
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@ -888,6 +910,12 @@ int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu)
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case SYS_ICC_HPPIR1_EL1:
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fn = __vgic_v3_read_hppir;
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break;
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case SYS_ICC_BPR0_EL1:
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if (is_read)
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fn = __vgic_v3_read_bpr0;
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else
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fn = __vgic_v3_write_bpr0;
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break;
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default:
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return 0;
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}
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