qla2xxx: Adjust adapter reset routine to the changes in firmware specification for ISPFx00.
Signed-off-by: Armen Baloyan <armen.baloyan@qlogic.com> Signed-off-by: Saurav Kashyap <saurav.kashyap@qlogic.com> Signed-off-by: Christoph Hellwig <hch@lst.de>
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f934c9d082
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42543fb946
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@ -527,21 +527,63 @@ qlafx00_soc_cpu_reset(scsi_qla_host_t *vha)
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struct qla_hw_data *ha = vha->hw;
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int i, core;
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uint32_t cnt;
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uint32_t reg_val;
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spin_lock_irqsave(&ha->hardware_lock, flags);
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QLAFX00_SET_HBA_SOC_REG(ha, 0x80004, 0);
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QLAFX00_SET_HBA_SOC_REG(ha, 0x82004, 0);
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/* stop the XOR DMA engines */
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QLAFX00_SET_HBA_SOC_REG(ha, 0x60920, 0x02);
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QLAFX00_SET_HBA_SOC_REG(ha, 0x60924, 0x02);
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QLAFX00_SET_HBA_SOC_REG(ha, 0xf0920, 0x02);
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QLAFX00_SET_HBA_SOC_REG(ha, 0xf0924, 0x02);
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/* stop the IDMA engines */
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reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60840);
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reg_val &= ~(1<<12);
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QLAFX00_SET_HBA_SOC_REG(ha, 0x60840, reg_val);
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reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60844);
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reg_val &= ~(1<<12);
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QLAFX00_SET_HBA_SOC_REG(ha, 0x60844, reg_val);
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reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60848);
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reg_val &= ~(1<<12);
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QLAFX00_SET_HBA_SOC_REG(ha, 0x60848, reg_val);
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reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x6084C);
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reg_val &= ~(1<<12);
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QLAFX00_SET_HBA_SOC_REG(ha, 0x6084C, reg_val);
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for (i = 0; i < 100000; i++) {
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if ((QLAFX00_GET_HBA_SOC_REG(ha, 0xd0000) & 0x10000000) == 0 &&
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(QLAFX00_GET_HBA_SOC_REG(ha, 0x10600) & 0x1) == 0)
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break;
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udelay(100);
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}
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/* Set all 4 cores in reset */
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for (i = 0; i < 4; i++) {
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QLAFX00_SET_HBA_SOC_REG(ha,
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(SOC_SW_RST_CONTROL_REG_CORE0 + 8*i), (0xF01));
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}
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/* Set all 4 core Clock gating control */
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for (i = 0; i < 4; i++) {
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QLAFX00_SET_HBA_SOC_REG(ha,
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(SOC_SW_RST_CONTROL_REG_CORE0 + 4 + 8*i), (0x01010101));
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}
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/* Reset all units in Fabric */
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QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x11F0101));
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QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x011f0101));
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/* */
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QLAFX00_SET_HBA_SOC_REG(ha, 0x10610, 1);
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QLAFX00_SET_HBA_SOC_REG(ha, 0x10600, 0);
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/* Set all 4 core Memory Power Down Registers */
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for (i = 0; i < 5; i++) {
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QLAFX00_SET_HBA_SOC_REG(ha,
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(SOC_PWR_MANAGEMENT_PWR_DOWN_REG + 4*i), (0x0));
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}
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/* Reset all interrupt control registers */
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for (i = 0; i < 115; i++) {
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@ -564,8 +606,6 @@ qlafx00_soc_cpu_reset(scsi_qla_host_t *vha)
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QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONTROL_REG, (0x2));
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QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONFIG_REG, (0x3));
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spin_lock_irqsave(&ha->hardware_lock, flags);
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/* Kick in Fabric units */
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QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x0));
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@ -598,7 +638,6 @@ qlafx00_soft_reset(scsi_qla_host_t *vha)
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ha->isp_ops->disable_intrs(ha);
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qlafx00_soc_cpu_reset(vha);
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ha->isp_ops->enable_intrs(ha);
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}
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/**
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@ -351,6 +351,7 @@ struct config_info_data {
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#define SOC_FABRIC_RST_CONTROL_REG 0x0020840
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#define SOC_FABRIC_CONTROL_REG 0x0020200
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#define SOC_FABRIC_CONFIG_REG 0x0020204
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#define SOC_PWR_MANAGEMENT_PWR_DOWN_REG 0x001820C
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#define SOC_INTERRUPT_SOURCE_I_CONTROL_REG 0x0020B00
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#define SOC_CORE_TIMER_REG 0x0021850
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