crypto: nx-842 - Mask XERS0 bit in return value
[ Upstream commit 6333ed8f26
]
NX842 coprocessor sets 3rd bit in CR register with XER[S0] which is
nothing to do with NX request. Since this bit can be set with other
valuable return status, mast this bit.
One of other bits (INITIATED, BUSY or REJECTED) will be returned for
any given NX request.
Signed-off-by: Haren Myneni <haren@us.ibm.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Родитель
f88503578d
Коммит
4259821921
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@ -164,6 +164,7 @@ struct coprocessor_request_block {
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#define ICSWX_INITIATED (0x8)
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#define ICSWX_INITIATED (0x8)
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#define ICSWX_BUSY (0x4)
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#define ICSWX_BUSY (0x4)
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#define ICSWX_REJECTED (0x2)
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#define ICSWX_REJECTED (0x2)
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#define ICSWX_XERS0 (0x1) /* undefined or set from XERSO. */
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static inline int icswx(__be32 ccw, struct coprocessor_request_block *crb)
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static inline int icswx(__be32 ccw, struct coprocessor_request_block *crb)
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{
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{
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@ -442,6 +442,14 @@ static int nx842_powernv_function(const unsigned char *in, unsigned int inlen,
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(unsigned int)ccw,
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(unsigned int)ccw,
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(unsigned int)be32_to_cpu(crb->ccw));
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(unsigned int)be32_to_cpu(crb->ccw));
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/*
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* NX842 coprocessor sets 3rd bit in CR register with XER[S0].
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* XER[S0] is the integer summary overflow bit which is nothing
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* to do NX. Since this bit can be set with other return values,
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* mask this bit.
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*/
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ret &= ~ICSWX_XERS0;
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switch (ret) {
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switch (ret) {
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case ICSWX_INITIATED:
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case ICSWX_INITIATED:
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ret = wait_for_csb(wmem, csb);
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ret = wait_for_csb(wmem, csb);
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@ -454,10 +462,6 @@ static int nx842_powernv_function(const unsigned char *in, unsigned int inlen,
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pr_err_ratelimited("ICSWX rejected\n");
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pr_err_ratelimited("ICSWX rejected\n");
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ret = -EPROTO;
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ret = -EPROTO;
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break;
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break;
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default:
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pr_err_ratelimited("Invalid ICSWX return code %x\n", ret);
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ret = -EPROTO;
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break;
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}
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}
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if (!ret)
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if (!ret)
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