fpga: dfl: fme: add thermal management support
This patch adds support to thermal management private feature for DFL FPGA Management Engine (FME). This private feature driver registers a hwmon for thermal/temperature monitoring (hwmon temp1_input). If hardware automatic throttling is supported by this hardware, then driver also exposes sysfs interfaces under hwmon for thresholds (temp1_max/ crit/ emergency), threshold alarms (temp1_max_alarm/ temp1_crit_alarm) and throttling policy (temp1_max_policy). Signed-off-by: Luwei Kang <luwei.kang@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Moritz Fischer <mdf@kernel.org> Signed-off-by: Moritz Fischer <mdf@kernel.org>
This commit is contained in:
Wu Hao
Moritz Fischer
Родитель
214be7470e
Коммит
4284c65a9f
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@ -106,3 +106,67 @@ KernelVersion: 5.4
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-only. Read this file to get the second error detected by
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hardware.
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What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/name
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Date: October 2019
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KernelVersion: 5.5
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-Only. Read this file to get the name of hwmon device, it
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supports values:
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'dfl_fme_thermal' - thermal hwmon device name
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What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/temp1_input
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Date: October 2019
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KernelVersion: 5.5
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-Only. It returns FPGA device temperature in millidegrees
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Celsius.
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What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/temp1_max
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Date: October 2019
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KernelVersion: 5.5
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-Only. It returns hardware threshold1 temperature in
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millidegrees Celsius. If temperature rises at or above this
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threshold, hardware starts 50% or 90% throttling (see
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'temp1_max_policy').
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What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/temp1_crit
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Date: October 2019
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KernelVersion: 5.5
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-Only. It returns hardware threshold2 temperature in
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millidegrees Celsius. If temperature rises at or above this
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threshold, hardware starts 100% throttling.
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What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/temp1_emergency
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Date: October 2019
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KernelVersion: 5.5
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-Only. It returns hardware trip threshold temperature in
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millidegrees Celsius. If temperature rises at or above this
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threshold, a fatal event will be triggered to board management
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controller (BMC) to shutdown FPGA.
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What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/temp1_max_alarm
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Date: October 2019
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KernelVersion: 5.5
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-only. It returns 1 if temperature is currently at or above
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hardware threshold1 (see 'temp1_max'), otherwise 0.
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What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/temp1_crit_alarm
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Date: October 2019
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KernelVersion: 5.5
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-only. It returns 1 if temperature is currently at or above
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hardware threshold2 (see 'temp1_crit'), otherwise 0.
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What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/temp1_max_policy
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Date: October 2019
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KernelVersion: 5.5
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-Only. Read this file to get the policy of hardware threshold1
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(see 'temp1_max'). It only supports two values (policies):
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0 - AP2 state (90% throttling)
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1 - AP1 state (50% throttling)
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@ -156,7 +156,7 @@ config FPGA_DFL
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config FPGA_DFL_FME
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tristate "FPGA DFL FME Driver"
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depends on FPGA_DFL
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depends on FPGA_DFL && HWMON
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help
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The FPGA Management Engine (FME) is a feature device implemented
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under Device Feature List (DFL) framework. Select this option to
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@ -14,6 +14,8 @@
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* Henry Mitchel <henry.mitchel@intel.com>
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*/
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#include <linux/hwmon.h>
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#include <linux/hwmon-sysfs.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/uaccess.h>
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@ -181,6 +183,178 @@ static const struct dfl_feature_ops fme_hdr_ops = {
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.ioctl = fme_hdr_ioctl,
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};
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#define FME_THERM_THRESHOLD 0x8
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#define TEMP_THRESHOLD1 GENMASK_ULL(6, 0)
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#define TEMP_THRESHOLD1_EN BIT_ULL(7)
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#define TEMP_THRESHOLD2 GENMASK_ULL(14, 8)
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#define TEMP_THRESHOLD2_EN BIT_ULL(15)
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#define TRIP_THRESHOLD GENMASK_ULL(30, 24)
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#define TEMP_THRESHOLD1_STATUS BIT_ULL(32) /* threshold1 reached */
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#define TEMP_THRESHOLD2_STATUS BIT_ULL(33) /* threshold2 reached */
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/* threshold1 policy: 0 - AP2 (90% throttle) / 1 - AP1 (50% throttle) */
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#define TEMP_THRESHOLD1_POLICY BIT_ULL(44)
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#define FME_THERM_RDSENSOR_FMT1 0x10
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#define FPGA_TEMPERATURE GENMASK_ULL(6, 0)
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#define FME_THERM_CAP 0x20
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#define THERM_NO_THROTTLE BIT_ULL(0)
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#define MD_PRE_DEG
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static bool fme_thermal_throttle_support(void __iomem *base)
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{
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u64 v = readq(base + FME_THERM_CAP);
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return FIELD_GET(THERM_NO_THROTTLE, v) ? false : true;
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}
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static umode_t thermal_hwmon_attrs_visible(const void *drvdata,
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enum hwmon_sensor_types type,
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u32 attr, int channel)
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{
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const struct dfl_feature *feature = drvdata;
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/* temperature is always supported, and check hardware cap for others */
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if (attr == hwmon_temp_input)
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return 0444;
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return fme_thermal_throttle_support(feature->ioaddr) ? 0444 : 0;
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}
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static int thermal_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
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u32 attr, int channel, long *val)
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{
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struct dfl_feature *feature = dev_get_drvdata(dev);
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u64 v;
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switch (attr) {
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case hwmon_temp_input:
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v = readq(feature->ioaddr + FME_THERM_RDSENSOR_FMT1);
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*val = (long)(FIELD_GET(FPGA_TEMPERATURE, v) * 1000);
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break;
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case hwmon_temp_max:
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v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
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*val = (long)(FIELD_GET(TEMP_THRESHOLD1, v) * 1000);
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break;
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case hwmon_temp_crit:
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v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
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*val = (long)(FIELD_GET(TEMP_THRESHOLD2, v) * 1000);
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break;
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case hwmon_temp_emergency:
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v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
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*val = (long)(FIELD_GET(TRIP_THRESHOLD, v) * 1000);
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break;
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case hwmon_temp_max_alarm:
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v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
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*val = (long)FIELD_GET(TEMP_THRESHOLD1_STATUS, v);
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break;
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case hwmon_temp_crit_alarm:
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v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
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*val = (long)FIELD_GET(TEMP_THRESHOLD2_STATUS, v);
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break;
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default:
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return -EOPNOTSUPP;
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}
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return 0;
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}
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static const struct hwmon_ops thermal_hwmon_ops = {
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.is_visible = thermal_hwmon_attrs_visible,
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.read = thermal_hwmon_read,
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};
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static const struct hwmon_channel_info *thermal_hwmon_info[] = {
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HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT | HWMON_T_EMERGENCY |
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HWMON_T_MAX | HWMON_T_MAX_ALARM |
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HWMON_T_CRIT | HWMON_T_CRIT_ALARM),
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NULL
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};
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static const struct hwmon_chip_info thermal_hwmon_chip_info = {
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.ops = &thermal_hwmon_ops,
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.info = thermal_hwmon_info,
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};
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static ssize_t temp1_max_policy_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct dfl_feature *feature = dev_get_drvdata(dev);
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u64 v;
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v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
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return sprintf(buf, "%u\n",
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(unsigned int)FIELD_GET(TEMP_THRESHOLD1_POLICY, v));
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}
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static DEVICE_ATTR_RO(temp1_max_policy);
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static struct attribute *thermal_extra_attrs[] = {
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&dev_attr_temp1_max_policy.attr,
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NULL,
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};
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static umode_t thermal_extra_attrs_visible(struct kobject *kobj,
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struct attribute *attr, int index)
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{
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struct device *dev = kobj_to_dev(kobj);
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struct dfl_feature *feature = dev_get_drvdata(dev);
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return fme_thermal_throttle_support(feature->ioaddr) ? attr->mode : 0;
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}
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static const struct attribute_group thermal_extra_group = {
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.attrs = thermal_extra_attrs,
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.is_visible = thermal_extra_attrs_visible,
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};
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__ATTRIBUTE_GROUPS(thermal_extra);
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static int fme_thermal_mgmt_init(struct platform_device *pdev,
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struct dfl_feature *feature)
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{
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struct device *hwmon;
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/*
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* create hwmon to allow userspace monitoring temperature and other
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* threshold information.
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*
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* temp1_input -> FPGA device temperature
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* temp1_max -> hardware threshold 1 -> 50% or 90% throttling
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* temp1_crit -> hardware threshold 2 -> 100% throttling
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* temp1_emergency -> hardware trip_threshold to shutdown FPGA
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* temp1_max_alarm -> hardware threshold 1 alarm
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* temp1_crit_alarm -> hardware threshold 2 alarm
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*
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* create device specific sysfs interfaces, e.g. read temp1_max_policy
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* to understand the actual hardware throttling action (50% vs 90%).
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*
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* If hardware doesn't support automatic throttling per thresholds,
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* then all above sysfs interfaces are not visible except temp1_input
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* for temperature.
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*/
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hwmon = devm_hwmon_device_register_with_info(&pdev->dev,
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"dfl_fme_thermal", feature,
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&thermal_hwmon_chip_info,
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thermal_extra_groups);
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if (IS_ERR(hwmon)) {
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dev_err(&pdev->dev, "Fail to register thermal hwmon\n");
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return PTR_ERR(hwmon);
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}
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return 0;
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}
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static const struct dfl_feature_id fme_thermal_mgmt_id_table[] = {
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{.id = FME_FEATURE_ID_THERMAL_MGMT,},
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{0,}
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};
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static const struct dfl_feature_ops fme_thermal_mgmt_ops = {
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.init = fme_thermal_mgmt_init,
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};
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static struct dfl_feature_driver fme_feature_drvs[] = {
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{
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.id_table = fme_hdr_id_table,
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@ -194,6 +368,10 @@ static struct dfl_feature_driver fme_feature_drvs[] = {
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.id_table = fme_global_err_id_table,
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.ops = &fme_global_err_ops,
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},
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{
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.id_table = fme_thermal_mgmt_id_table,
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.ops = &fme_thermal_mgmt_ops,
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},
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{
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.ops = NULL,
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},
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