Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 fixes from Peter Anvin:
"One (hopefully) last batch of x86 fixes. You asked for the patch by
patch justifications, so here they are:
x86, MCE: Retract most UAPI exports
This one unexports from userspace a bunch of definitions which should
never have been exported. We really don't want to create an
accidental legacy here.
x86, doc: Add a bootloader ID for OVMF
This is a documentation-only patch, just recording the official
assignment of a boot loader ID.
x86: Do not leak kernel page mapping locations
Security: avoid making it needlessly easy for user space to probe the
kernel memory layout.
x86/mm: Check if PUD is large when validating a kernel address
Prevent failures using /proc/kcore when using 1G pages.
x86/apic: Work around boot failure on HP ProLiant DL980 G7 Server systems
Works around a BIOS problem causing boot failures on affected hardware."
* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/mm: Check if PUD is large when validating a kernel address
x86/apic: Work around boot failure on HP ProLiant DL980 G7 Server systems
x86, doc: Add a bootloader ID for OVMF
x86: Do not leak kernel page mapping locations
x86, MCE: Retract most UAPI exports
This commit is contained in:
Linus Torvalds
Коммит
42976ad0b2
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@ -390,6 +390,7 @@ Protocol: 2.00+
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F Special (0xFF = undefined)
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10 Reserved
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11 Minimal Linux Bootloader <http://sebastian-plotz.blogspot.de>
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12 OVMF UEFI virtualization stack
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Please contact <hpa@zytor.com> if you need a bootloader ID
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value assigned.
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@ -3,6 +3,90 @@
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#include <uapi/asm/mce.h>
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/*
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* Machine Check support for x86
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*/
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/* MCG_CAP register defines */
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#define MCG_BANKCNT_MASK 0xff /* Number of Banks */
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#define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */
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#define MCG_EXT_P (1ULL<<9) /* Extended registers available */
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#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
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#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
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#define MCG_EXT_CNT_SHIFT 16
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#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
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#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
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/* MCG_STATUS register defines */
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#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
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#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
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#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
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/* MCi_STATUS register defines */
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#define MCI_STATUS_VAL (1ULL<<63) /* valid error */
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#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
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#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
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#define MCI_STATUS_EN (1ULL<<60) /* error enabled */
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#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
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#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
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#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
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#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
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#define MCI_STATUS_AR (1ULL<<55) /* Action required */
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#define MCACOD 0xffff /* MCA Error Code */
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/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
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#define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */
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#define MCACOD_SCRUBMSK 0xfff0
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#define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */
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#define MCACOD_DATA 0x0134 /* Data Load */
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#define MCACOD_INSTR 0x0150 /* Instruction Fetch */
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/* MCi_MISC register defines */
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#define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
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#define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
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#define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */
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#define MCI_MISC_ADDR_LINEAR 1 /* linear address */
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#define MCI_MISC_ADDR_PHYS 2 /* physical address */
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#define MCI_MISC_ADDR_MEM 3 /* memory address */
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#define MCI_MISC_ADDR_GENERIC 7 /* generic */
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/* CTL2 register defines */
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#define MCI_CTL2_CMCI_EN (1ULL << 30)
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#define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
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#define MCJ_CTX_MASK 3
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#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
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#define MCJ_CTX_RANDOM 0 /* inject context: random */
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#define MCJ_CTX_PROCESS 0x1 /* inject context: process */
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#define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */
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#define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */
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#define MCJ_EXCEPTION 0x8 /* raise as exception */
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#define MCJ_IRQ_BRAODCAST 0x10 /* do IRQ broadcasting */
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#define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
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/* Software defined banks */
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#define MCE_EXTENDED_BANK 128
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#define MCE_THERMAL_BANK (MCE_EXTENDED_BANK + 0)
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#define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1)
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#define MCE_LOG_LEN 32
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#define MCE_LOG_SIGNATURE "MACHINECHECK"
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/*
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* This structure contains all data related to the MCE log. Also
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* carries a signature to make it easier to find from external
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* debugging tools. Each entry is only valid when its finished flag
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* is set.
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*/
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struct mce_log {
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char signature[12]; /* "MACHINECHECK" */
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unsigned len; /* = MCE_LOG_LEN */
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unsigned next;
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unsigned flags;
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unsigned recordlen; /* length of struct mce */
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struct mce entry[MCE_LOG_LEN];
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};
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struct mca_config {
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bool dont_log_ce;
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@ -142,6 +142,11 @@ static inline unsigned long pmd_pfn(pmd_t pmd)
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return (pmd_val(pmd) & PTE_PFN_MASK) >> PAGE_SHIFT;
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}
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static inline unsigned long pud_pfn(pud_t pud)
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{
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return (pud_val(pud) & PTE_PFN_MASK) >> PAGE_SHIFT;
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}
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#define pte_page(pte) pfn_to_page(pte_pfn(pte))
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static inline int pmd_large(pmd_t pte)
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@ -4,66 +4,6 @@
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#include <linux/types.h>
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#include <asm/ioctls.h>
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/*
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* Machine Check support for x86
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*/
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/* MCG_CAP register defines */
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#define MCG_BANKCNT_MASK 0xff /* Number of Banks */
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#define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */
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#define MCG_EXT_P (1ULL<<9) /* Extended registers available */
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#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
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#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
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#define MCG_EXT_CNT_SHIFT 16
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#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
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#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
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/* MCG_STATUS register defines */
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#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
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#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
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#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
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/* MCi_STATUS register defines */
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#define MCI_STATUS_VAL (1ULL<<63) /* valid error */
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#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
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#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
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#define MCI_STATUS_EN (1ULL<<60) /* error enabled */
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#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
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#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
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#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
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#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
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#define MCI_STATUS_AR (1ULL<<55) /* Action required */
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#define MCACOD 0xffff /* MCA Error Code */
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/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
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#define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */
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#define MCACOD_SCRUBMSK 0xfff0
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#define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */
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#define MCACOD_DATA 0x0134 /* Data Load */
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#define MCACOD_INSTR 0x0150 /* Instruction Fetch */
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/* MCi_MISC register defines */
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#define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
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#define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
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#define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */
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#define MCI_MISC_ADDR_LINEAR 1 /* linear address */
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#define MCI_MISC_ADDR_PHYS 2 /* physical address */
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#define MCI_MISC_ADDR_MEM 3 /* memory address */
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#define MCI_MISC_ADDR_GENERIC 7 /* generic */
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/* CTL2 register defines */
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#define MCI_CTL2_CMCI_EN (1ULL << 30)
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#define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
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#define MCJ_CTX_MASK 3
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#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
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#define MCJ_CTX_RANDOM 0 /* inject context: random */
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#define MCJ_CTX_PROCESS 0x1 /* inject context: process */
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#define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */
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#define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */
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#define MCJ_EXCEPTION 0x8 /* raise as exception */
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#define MCJ_IRQ_BRAODCAST 0x10 /* do IRQ broadcasting */
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/* Fields are zero when not available */
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struct mce {
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__u64 status;
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@ -87,35 +27,8 @@ struct mce {
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__u64 mcgcap; /* MCGCAP MSR: machine check capabilities of CPU */
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};
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/*
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* This structure contains all data related to the MCE log. Also
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* carries a signature to make it easier to find from external
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* debugging tools. Each entry is only valid when its finished flag
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* is set.
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*/
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#define MCE_LOG_LEN 32
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struct mce_log {
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char signature[12]; /* "MACHINECHECK" */
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unsigned len; /* = MCE_LOG_LEN */
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unsigned next;
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unsigned flags;
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unsigned recordlen; /* length of struct mce */
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struct mce entry[MCE_LOG_LEN];
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};
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#define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
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#define MCE_LOG_SIGNATURE "MACHINECHECK"
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#define MCE_GET_RECORD_LEN _IOR('M', 1, int)
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#define MCE_GET_LOG_LEN _IOR('M', 2, int)
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#define MCE_GETCLEAR_FLAGS _IOR('M', 3, int)
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/* Software defined banks */
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#define MCE_EXTENDED_BANK 128
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#define MCE_THERMAL_BANK MCE_EXTENDED_BANK + 0
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#define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1)
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#endif /* _UAPI_ASM_X86_MCE_H */
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@ -20,18 +20,19 @@ static int set_x2apic_phys_mode(char *arg)
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}
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early_param("x2apic_phys", set_x2apic_phys_mode);
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static bool x2apic_fadt_phys(void)
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{
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if ((acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID) &&
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(acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL)) {
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printk(KERN_DEBUG "System requires x2apic physical mode\n");
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return true;
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}
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return false;
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}
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static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
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{
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if (x2apic_phys)
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return x2apic_enabled();
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else if ((acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID) &&
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(acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL) &&
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x2apic_enabled()) {
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printk(KERN_DEBUG "System requires x2apic physical mode\n");
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return 1;
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}
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else
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return 0;
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return x2apic_enabled() && (x2apic_phys || x2apic_fadt_phys());
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}
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static void
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@ -82,7 +83,7 @@ static void init_x2apic_ldr(void)
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static int x2apic_phys_probe(void)
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{
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if (x2apic_mode && x2apic_phys)
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if (x2apic_mode && (x2apic_phys || x2apic_fadt_phys()))
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return 1;
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return apic == &apic_x2apic_phys;
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@ -748,13 +748,15 @@ __bad_area_nosemaphore(struct pt_regs *regs, unsigned long error_code,
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return;
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}
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#endif
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/* Kernel addresses are always protection faults: */
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if (address >= TASK_SIZE)
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error_code |= PF_PROT;
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if (unlikely(show_unhandled_signals))
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if (likely(show_unhandled_signals))
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show_signal_msg(regs, error_code, address, tsk);
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/* Kernel addresses are always protection faults: */
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tsk->thread.cr2 = address;
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tsk->thread.error_code = error_code | (address >= TASK_SIZE);
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tsk->thread.error_code = error_code;
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tsk->thread.trap_nr = X86_TRAP_PF;
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force_sig_info_fault(SIGSEGV, si_code, address, tsk, 0);
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@ -831,6 +831,9 @@ int kern_addr_valid(unsigned long addr)
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if (pud_none(*pud))
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return 0;
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if (pud_large(*pud))
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return pfn_valid(pud_pfn(*pud));
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pmd = pmd_offset(pud, addr);
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if (pmd_none(*pmd))
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return 0;
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