pinctrl: Device tree bindings for Qualcomm PMIC GPIO block
This introduced the device tree bindings for the GPIO block found in PMIC's from Qualcomm. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Bjorn Andersson
Linus Walleij
Родитель
c654b6bf2c
Коммит
43059f6ba2
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Qualcomm PMIC GPIO block
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This binding describes the GPIO block(s) found in the 8xxx series of
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PMIC's from Qualcomm.
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- compatible:
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Usage: required
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Value type: <string>
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Definition: must be one of:
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"qcom,pm8018-gpio"
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"qcom,pm8038-gpio"
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"qcom,pm8058-gpio"
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"qcom,pm8917-gpio"
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"qcom,pm8921-gpio"
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"qcom,pm8941-gpio"
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"qcom,pma8084-gpio"
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- reg:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: Register base of the GPIO block and length.
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- interrupts:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: Must contain an array of encoded interrupt specifiers for
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each available GPIO
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- gpio-controller:
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Usage: required
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Value type: <none>
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Definition: Mark the device node as a GPIO controller
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- #gpio-cells:
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Usage: required
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Value type: <u32>
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Definition: Must be 2;
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the first cell will be used to define gpio number and the
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second denotes the flags for this gpio
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Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
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a general description of GPIO and interrupt bindings.
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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The pin configuration nodes act as a container for an arbitrary number of
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subnodes. Each of these subnodes represents some desired configuration for a
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pin or a list of pins. This configuration can include the
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mux function to select on those pin(s), and various pin configuration
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parameters, as listed below.
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SUBNODES:
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The name of each subnode is not important; all subnodes should be enumerated
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and processed purely based on their content.
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Each subnode only affects those parameters that are explicitly listed. In
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other words, a subnode that lists a mux function but no pin configuration
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parameters implies no information about any pin configuration parameters.
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Similarly, a pin subnode that describes a pullup parameter implies no
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information about e.g. the mux function.
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The following generic properties as defined in pinctrl-bindings.txt are valid
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to specify in a pin configuration subnode:
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- pins:
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Usage: required
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Value type: <string-array>
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Definition: List of gpio pins affected by the properties specified in
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this subnode. Valid pins are:
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gpio1-gpio6 for pm8018
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gpio1-gpio12 for pm8038
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gpio1-gpio40 for pm8058
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gpio1-gpio38 for pm8917
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gpio1-gpio44 for pm8921
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gpio1-gpio36 for pm8941
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gpio1-gpio22 for pma8084
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- function:
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Usage: required
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Value type: <string>
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Definition: Specify the alternative function to be configured for the
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specified pins. Valid values are:
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"normal",
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"paired",
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"func1",
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"func2",
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"dtest1",
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"dtest2",
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"dtest3",
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"dtest4"
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- bias-disable:
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Usage: optional
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Value type: <none>
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Definition: The specified pins should be configured as no pull.
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- bias-pull-down:
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Usage: optional
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Value type: <none>
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Definition: The specified pins should be configured as pull down.
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- bias-pull-up:
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Usage: optional
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Value type: <empty>
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Definition: The specified pins should be configured as pull up.
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- qcom,pull-up-strength:
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Usage: optional
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Value type: <u32>
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Definition: Specifies the strength to use for pull up, if selected.
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Valid values are; as defined in
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<dt-bindings/pinctrl/qcom,pmic-gpio.h>:
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1: 30uA (PMIC_GPIO_PULL_UP_30)
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2: 1.5uA (PMIC_GPIO_PULL_UP_1P5)
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3: 31.5uA (PMIC_GPIO_PULL_UP_31P5)
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4: 1.5uA + 30uA boost (PMIC_GPIO_PULL_UP_1P5_30)
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If this property is ommited 30uA strength will be used if
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pull up is selected
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- bias-high-impedance:
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Usage: optional
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Value type: <none>
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Definition: The specified pins will put in high-Z mode and disabled.
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- input-enable:
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Usage: optional
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Value type: <none>
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Definition: The specified pins are put in input mode.
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- output-high:
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Usage: optional
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Value type: <none>
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Definition: The specified pins are configured in output mode, driven
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high.
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- output-low:
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Usage: optional
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Value type: <none>
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Definition: The specified pins are configured in output mode, driven
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low.
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- power-source:
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Usage: optional
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Value type: <u32>
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Definition: Selects the power source for the specified pins. Valid
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power sources are defined per chip in
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<dt-bindings/pinctrl/qcom,pmic-gpio.h>
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- qcom,drive-strength:
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Usage: optional
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Value type: <u32>
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Definition: Selects the drive strength for the specified pins. Value
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drive strengths are:
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0: no (PMIC_GPIO_STRENGTH_NO)
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1: high (PMIC_GPIO_STRENGTH_HIGH) 0.9mA @ 1.8V - 1.9mA @ 2.6V
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2: medium (PMIC_GPIO_STRENGTH_MED) 0.6mA @ 1.8V - 1.25mA @ 2.6V
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3: low (PMIC_GPIO_STRENGTH_LOW) 0.15mA @ 1.8V - 0.3mA @ 2.6V
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as defined in <dt-bindings/pinctrl/qcom,pmic-gpio.h>
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- drive-push-pull:
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Usage: optional
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Value type: <none>
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Definition: The specified pins are configured in push-pull mode.
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- drive-open-drain:
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Usage: optional
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Value type: <none>
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Definition: The specified pins are configured in open-drain mode.
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- drive-open-source:
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Usage: optional
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Value type: <none>
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Definition: The specified pins are configured in open-source mode.
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Example:
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pm8921_gpio: gpio@150 {
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compatible = "qcom,pm8921-gpio";
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reg = <0x150 0x160>;
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interrupts = <192 1>, <193 1>, <194 1>,
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<195 1>, <196 1>, <197 1>,
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<198 1>, <199 1>, <200 1>,
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<201 1>, <202 1>, <203 1>,
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<204 1>, <205 1>, <206 1>,
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<207 1>, <208 1>, <209 1>,
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<210 1>, <211 1>, <212 1>,
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<213 1>, <214 1>, <215 1>,
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<216 1>, <217 1>, <218 1>,
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<219 1>, <220 1>, <221 1>,
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<222 1>, <223 1>, <224 1>,
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<225 1>, <226 1>, <227 1>,
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<228 1>, <229 1>, <230 1>,
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<231 1>, <232 1>, <233 1>,
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<234 1>, <235 1>;
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gpio-controller;
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#gpio-cells = <2>;
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pm8921_gpio_keys: gpio-keys {
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volume-keys {
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pins = "gpio20", "gpio21";
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function = "normal";
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input-enable;
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bias-pull-up;
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drive-push-pull;
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qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
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power-source = <PM8921_GPIO_S4>;
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};
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};
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};
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/*
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* This header provides constants for the Qualcomm PMIC GPIO binding.
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*/
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#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H
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#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H
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#define PMIC_GPIO_PULL_UP_30 0
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#define PMIC_GPIO_PULL_UP_1P5 1
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#define PMIC_GPIO_PULL_UP_31P5 2
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#define PMIC_GPIO_PULL_UP_1P5_30 3
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#define PMIC_GPIO_STRENGTH_NO 0
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#define PMIC_GPIO_STRENGTH_HIGH 1
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#define PMIC_GPIO_STRENGTH_MED 2
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#define PMIC_GPIO_STRENGTH_LOW 3
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/*
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* Note: PM8018 GPIO3 and GPIO4 are supporting
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* only S3 and L2 options (1.8V)
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*/
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#define PM8018_GPIO_L6 0
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#define PM8018_GPIO_L5 1
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#define PM8018_GPIO_S3 2
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#define PM8018_GPIO_L14 3
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#define PM8018_GPIO_L2 4
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#define PM8018_GPIO_L4 5
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#define PM8018_GPIO_VDD 6
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/*
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* Note: PM8038 GPIO7 and GPIO8 are supporting
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* only L11 and L4 options (1.8V)
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*/
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#define PM8038_GPIO_VPH 0
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#define PM8038_GPIO_BB 1
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#define PM8038_GPIO_L11 2
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#define PM8038_GPIO_L15 3
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#define PM8038_GPIO_L4 4
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#define PM8038_GPIO_L3 5
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#define PM8038_GPIO_L17 6
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#define PM8058_GPIO_VPH 0
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#define PM8058_GPIO_BB 1
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#define PM8058_GPIO_S3 2
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#define PM8058_GPIO_L3 3
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#define PM8058_GPIO_L7 4
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#define PM8058_GPIO_L6 5
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#define PM8058_GPIO_L5 6
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#define PM8058_GPIO_L2 7
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#define PM8917_GPIO_VPH 0
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#define PM8917_GPIO_S4 2
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#define PM8917_GPIO_L15 3
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#define PM8917_GPIO_L4 4
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#define PM8917_GPIO_L3 5
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#define PM8917_GPIO_L17 6
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#define PM8921_GPIO_VPH 0
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#define PM8921_GPIO_BB 1
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#define PM8921_GPIO_S4 2
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#define PM8921_GPIO_L15 3
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#define PM8921_GPIO_L4 4
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#define PM8921_GPIO_L3 5
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#define PM8921_GPIO_L17 6
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/*
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* Note: PM8941 gpios from 15 to 18 are supporting
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* only S3 and L6 options (1.8V)
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*/
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#define PM8941_GPIO_VPH 0
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#define PM8941_GPIO_L1 1
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#define PM8941_GPIO_S3 2
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#define PM8941_GPIO_L6 3
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/*
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* Note: PMA8084 gpios from 15 to 18 are supporting
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* only S4 and L6 options (1.8V)
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*/
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#define PMA8084_GPIO_VPH 0
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#define PMA8084_GPIO_L1 1
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#define PMA8084_GPIO_S4 2
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#define PMA8084_GPIO_L6 3
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/* To be used with "function" */
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#define PMIC_GPIO_FUNC_NORMAL "normal"
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#define PMIC_GPIO_FUNC_PAIRED "paired"
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#define PMIC_GPIO_FUNC_FUNC1 "func1"
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#define PMIC_GPIO_FUNC_FUNC2 "func2"
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#define PMIC_GPIO_FUNC_DTEST1 "dtest1"
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#define PMIC_GPIO_FUNC_DTEST2 "dtest2"
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#define PMIC_GPIO_FUNC_DTEST3 "dtest3"
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#define PMIC_GPIO_FUNC_DTEST4 "dtest4"
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#define PM8038_GPIO1_2_LPG_DRV PMIC_GPIO_FUNC_FUNC1
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#define PM8038_GPIO3_5V_BOOST_EN PMIC_GPIO_FUNC_FUNC1
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#define PM8038_GPIO4_SSBI_ALT_CLK PMIC_GPIO_FUNC_FUNC1
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#define PM8038_GPIO5_6_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1
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#define PM8038_GPIO10_11_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1
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#define PM8038_GPIO6_7_CLK PMIC_GPIO_FUNC_FUNC1
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#define PM8038_GPIO9_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1
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#define PM8038_GPIO6_12_KYPD_DRV PMIC_GPIO_FUNC_FUNC2
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#define PM8058_GPIO7_8_MP3_CLK PMIC_GPIO_FUNC_FUNC1
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#define PM8058_GPIO7_8_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC2
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#define PM8058_GPIO9_26_KYPD_DRV PMIC_GPIO_FUNC_FUNC1
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#define PM8058_GPIO21_23_UART_TX PMIC_GPIO_FUNC_FUNC2
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#define PM8058_GPIO24_26_LPG_DRV PMIC_GPIO_FUNC_FUNC2
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#define PM8058_GPIO33_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC1
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#define PM8058_GPIO34_35_MP3_CLK PMIC_GPIO_FUNC_FUNC1
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#define PM8058_GPIO36_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC1
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#define PM8058_GPIO37_UPL_OUT PMIC_GPIO_FUNC_FUNC1
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#define PM8058_GPIO37_UART_M_RX PMIC_GPIO_FUNC_FUNC2
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#define PM8058_GPIO38_XO_SLEEP_CLK PMIC_GPIO_FUNC_FUNC1
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#define PM8058_GPIO38_39_CLK_32KHZ PMIC_GPIO_FUNC_FUNC2
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#define PM8058_GPIO39_MP3_CLK PMIC_GPIO_FUNC_FUNC1
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#define PM8058_GPIO40_EXT_BB_EN PMIC_GPIO_FUNC_FUNC1
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#define PM8917_GPIO9_18_KEYP_DRV PMIC_GPIO_FUNC_FUNC1
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#define PM8917_GPIO20_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1
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#define PM8917_GPIO21_23_UART_TX PMIC_GPIO_FUNC_FUNC2
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#define PM8917_GPIO25_26_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1
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#define PM8917_GPIO37_38_XO_SLEEP_CLK PMIC_GPIO_FUNC_FUNC1
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#define PM8917_GPIO37_38_MP3_CLK PMIC_GPIO_FUNC_FUNC2
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#define PM8941_GPIO9_14_KYPD_DRV PMIC_GPIO_FUNC_FUNC1
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#define PM8941_GPIO15_18_DIV_CLK PMIC_GPIO_FUNC_FUNC1
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#define PM8941_GPIO15_18_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2
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#define PM8941_GPIO23_26_KYPD_DRV PMIC_GPIO_FUNC_FUNC1
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#define PM8941_GPIO23_26_LPG_DRV_HI PMIC_GPIO_FUNC_FUNC2
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#define PM8941_GPIO31_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1
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#define PM8941_GPIO33_36_LPG_DRV_3D PMIC_GPIO_FUNC_FUNC1
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#define PM8941_GPIO33_36_LPG_DRV_HI PMIC_GPIO_FUNC_FUNC2
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#define PMA8084_GPIO4_5_LPG_DRV PMIC_GPIO_FUNC_FUNC1
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#define PMA8084_GPIO7_10_LPG_DRV PMIC_GPIO_FUNC_FUNC1
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#define PMA8084_GPIO5_14_KEYP_DRV PMIC_GPIO_FUNC_FUNC2
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#define PMA8084_GPIO19_21_KEYP_DRV PMIC_GPIO_FUNC_FUNC2
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#define PMA8084_GPIO15_18_DIV_CLK PMIC_GPIO_FUNC_FUNC1
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#define PMA8084_GPIO15_18_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2
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#define PMA8084_GPIO22_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1
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#endif
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