memory: mtk-smi: mt8195: Add initial setting for smi-common
To improve the performance, add initial setting for smi-common. some register use some fix setting(suggested from DE). Signed-off-by: Yong Wu <yong.wu@mediatek.com> Link: https://lore.kernel.org/r/20210914113703.31466-12-yong.wu@mediatek.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
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@ -18,11 +18,19 @@
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#include <dt-bindings/memory/mtk-memory-port.h>
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/* SMI COMMON */
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#define SMI_L1LEN 0x100
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#define SMI_BUS_SEL 0x220
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#define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1)
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/* All are MMU0 defaultly. Only specialize mmu1 here. */
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#define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid))
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#define SMI_M4U_TH 0x234
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#define SMI_FIFO_TH1 0x238
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#define SMI_FIFO_TH2 0x23c
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#define SMI_DCM 0x300
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#define SMI_DUMMY 0x444
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/* SMI LARB */
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/* Below are about mmu enable registers, they are different in SoCs */
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@ -59,6 +67,13 @@
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(_id << 8 | _id << 10 | _id << 12 | _id << 14); \
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})
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#define SMI_COMMON_INIT_REGS_NR 6
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struct mtk_smi_reg_pair {
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unsigned int offset;
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u32 value;
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};
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enum mtk_smi_type {
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MTK_SMI_GEN1,
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MTK_SMI_GEN2, /* gen2 smi common */
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@ -85,6 +100,8 @@ struct mtk_smi_common_plat {
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enum mtk_smi_type type;
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bool has_gals;
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u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */
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const struct mtk_smi_reg_pair *init;
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};
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struct mtk_smi_larb_gen {
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@ -419,6 +436,15 @@ static struct platform_driver mtk_smi_larb_driver = {
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}
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};
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static const struct mtk_smi_reg_pair mtk_smi_common_mt8195_init[SMI_COMMON_INIT_REGS_NR] = {
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{SMI_L1LEN, 0xb},
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{SMI_M4U_TH, 0xe100e10},
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{SMI_FIFO_TH1, 0x506090a},
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{SMI_FIFO_TH2, 0x506090a},
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{SMI_DCM, 0x4f1},
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{SMI_DUMMY, 0x1},
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};
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static const struct mtk_smi_common_plat mtk_smi_common_gen1 = {
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.type = MTK_SMI_GEN1,
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};
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@ -453,12 +479,14 @@ static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vdo = {
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.has_gals = true,
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.bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) |
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F_MMU1_LARB(7),
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.init = mtk_smi_common_mt8195_init,
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};
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static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vpp = {
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.type = MTK_SMI_GEN2,
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.has_gals = true,
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.bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7),
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.init = mtk_smi_common_mt8195_init,
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};
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static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8195 = {
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@ -551,15 +579,21 @@ static int mtk_smi_common_remove(struct platform_device *pdev)
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static int __maybe_unused mtk_smi_common_resume(struct device *dev)
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{
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struct mtk_smi *common = dev_get_drvdata(dev);
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u32 bus_sel = common->plat->bus_sel;
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int ret;
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const struct mtk_smi_reg_pair *init = common->plat->init;
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u32 bus_sel = common->plat->bus_sel; /* default is 0 */
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int ret, i;
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ret = clk_bulk_prepare_enable(common->clk_num, common->clks);
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if (ret)
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return ret;
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if (common->plat->type == MTK_SMI_GEN2 && bus_sel)
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writel(bus_sel, common->base + SMI_BUS_SEL);
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if (common->plat->type != MTK_SMI_GEN2)
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return 0;
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for (i = 0; i < SMI_COMMON_INIT_REGS_NR && init && init[i].offset; i++)
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writel_relaxed(init[i].value, common->base + init[i].offset);
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writel(bus_sel, common->base + SMI_BUS_SEL);
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return 0;
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}
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