ARM: at91/gpio: change comments and one variable name
What was true only on at91sam9263 about the sharing of a single AIC IRQ line for several GPIO banks is now used by several Atmel SoCs. Change a variable name to allow better understanding while introducing IRQ domains in following patches. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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@ -29,8 +29,8 @@
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struct at91_gpio_chip {
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struct at91_gpio_chip {
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struct gpio_chip chip;
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struct gpio_chip chip;
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struct at91_gpio_chip *next; /* Bank sharing same clock */
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struct at91_gpio_chip *next; /* Bank sharing same clock */
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int id; /* ID of register bank */
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int pioc_hwirq; /* PIO bank interrupt identifier on AIC */
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void __iomem *regbase; /* Base of register bank */
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void __iomem *regbase; /* PIO bank virtual address */
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struct clk *clock; /* associated clock */
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struct clk *clock; /* associated clock */
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};
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};
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@ -285,7 +285,7 @@ static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
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else
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else
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wakeups[bank] &= ~mask;
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wakeups[bank] &= ~mask;
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irq_set_irq_wake(gpio_chip[bank].id, state);
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irq_set_irq_wake(gpio_chip[bank].pioc_hwirq, state);
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return 0;
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return 0;
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}
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}
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@ -499,7 +499,7 @@ void __init at91_gpio_irq_setup(void)
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for (pioc = 0, this = gpio_chip, prev = NULL;
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for (pioc = 0, this = gpio_chip, prev = NULL;
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pioc++ < gpio_banks;
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pioc++ < gpio_banks;
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prev = this, this++) {
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prev = this, this++) {
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unsigned id = this->id;
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unsigned pioc_hwirq = this->pioc_hwirq;
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unsigned i;
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unsigned i;
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__raw_writel(~0, this->regbase + PIO_IDR);
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__raw_writel(~0, this->regbase + PIO_IDR);
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@ -518,14 +518,14 @@ void __init at91_gpio_irq_setup(void)
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}
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}
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/* The toplevel handler handles one bank of GPIOs, except
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/* The toplevel handler handles one bank of GPIOs, except
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* AT91SAM9263_ID_PIOCDE handles three... PIOC is first in
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* on some SoC it can handles up to three...
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* the list, so we only set up that handler.
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* We only set up the handler for the first of the list.
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*/
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*/
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if (prev && prev->next == this)
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if (prev && prev->next == this)
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continue;
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continue;
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irq_set_chip_data(id, this);
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irq_set_chip_data(pioc_hwirq, this);
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irq_set_chained_handler(id, gpio_irq_handler);
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irq_set_chained_handler(pioc_hwirq, gpio_irq_handler);
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}
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}
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pr_info("AT91: %d gpio irqs in %d banks\n", irq - gpio_to_irq(0), gpio_banks);
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pr_info("AT91: %d gpio irqs in %d banks\n", irq - gpio_to_irq(0), gpio_banks);
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}
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}
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@ -615,7 +615,7 @@ void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
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for (i = 0; i < nr_banks; i++) {
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for (i = 0; i < nr_banks; i++) {
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at91_gpio = &gpio_chip[i];
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at91_gpio = &gpio_chip[i];
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at91_gpio->id = data[i].id;
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at91_gpio->pioc_hwirq = data[i].pioc_hwirq;
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at91_gpio->chip.base = i * 32;
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at91_gpio->chip.base = i * 32;
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at91_gpio->regbase = ioremap(data[i].regbase, 512);
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at91_gpio->regbase = ioremap(data[i].regbase, 512);
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@ -633,8 +633,11 @@ void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
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/* enable PIO controller's clock */
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/* enable PIO controller's clock */
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clk_enable(at91_gpio->clock);
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clk_enable(at91_gpio->clock);
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/* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */
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/*
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if (last && last->id == at91_gpio->id)
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* GPIO controller are grouped on some SoC:
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* PIOC, PIOD and PIOE can share the same IRQ line
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*/
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if (last && last->pioc_hwirq == at91_gpio->pioc_hwirq)
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last->next = at91_gpio;
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last->next = at91_gpio;
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last = at91_gpio;
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last = at91_gpio;
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