[PATCH] ppc64: SMU based macs cpufreq support
CPU freq support using 970FX powertune facility for iMac G5 and SMU based single CPU desktop. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Benjamin Herrenschmidt
Paul Mackerras
Родитель
a82765b6ee
Коммит
4350147a81
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@ -404,6 +404,14 @@ config CPU_FREQ_PMAC
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this currently includes some models of iBook & Titanium
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PowerBook.
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config CPU_FREQ_PMAC64
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bool "Support for some Apple G5s"
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depends on CPU_FREQ && PMAC_SMU && PPC64
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select CPU_FREQ_TABLE
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help
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This adds support for frequency switching on Apple iMac G5,
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and some of the more recent desktop G5 machines as well.
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config PPC601_SYNC_FIX
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bool "Workarounds for PPC601 bugs"
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depends on 6xx && (PPC_PREP || PPC_PMAC)
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@ -603,6 +603,76 @@ _GLOBAL(real_writeb)
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blr
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#endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */
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/*
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* SCOM access functions for 970 (FX only for now)
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*
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* unsigned long scom970_read(unsigned int address);
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* void scom970_write(unsigned int address, unsigned long value);
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*
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* The address passed in is the 24 bits register address. This code
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* is 970 specific and will not check the status bits, so you should
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* know what you are doing.
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*/
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_GLOBAL(scom970_read)
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/* interrupts off */
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mfmsr r4
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ori r0,r4,MSR_EE
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xori r0,r0,MSR_EE
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mtmsrd r0,1
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/* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
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* (including parity). On current CPUs they must be 0'd,
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* and finally or in RW bit
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*/
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rlwinm r3,r3,8,0,15
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ori r3,r3,0x8000
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/* do the actual scom read */
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sync
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mtspr SPRN_SCOMC,r3
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isync
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mfspr r3,SPRN_SCOMD
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isync
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mfspr r0,SPRN_SCOMC
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isync
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/* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah
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* that's the best we can do). Not implemented yet as we don't use
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* the scom on any of the bogus CPUs yet, but may have to be done
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* ultimately
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*/
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/* restore interrupts */
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mtmsrd r4,1
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blr
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_GLOBAL(scom970_write)
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/* interrupts off */
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mfmsr r5
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ori r0,r5,MSR_EE
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xori r0,r0,MSR_EE
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mtmsrd r0,1
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/* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
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* (including parity). On current CPUs they must be 0'd.
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*/
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rlwinm r3,r3,8,0,15
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sync
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mtspr SPRN_SCOMD,r4 /* write data */
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isync
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mtspr SPRN_SCOMC,r3 /* write command */
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isync
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mfspr 3,SPRN_SCOMC
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isync
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/* restore interrupts */
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mtmsrd r5,1
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blr
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/*
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* Create a kernel thread
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* kernel_thread(fn, arg, flags)
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@ -1,7 +1,8 @@
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obj-y += pic.o setup.o time.o feature.o pci.o \
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sleep.o low_i2c.o cache.o
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obj-$(CONFIG_PMAC_BACKLIGHT) += backlight.o
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obj-$(CONFIG_CPU_FREQ_PMAC) += cpufreq.o
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obj-$(CONFIG_CPU_FREQ_PMAC) += cpufreq_32.o
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obj-$(CONFIG_CPU_FREQ_PMAC64) += cpufreq_64.o
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obj-$(CONFIG_NVRAM) += nvram.o
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# ppc64 pmac doesn't define CONFIG_NVRAM but needs nvram stuff
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obj-$(CONFIG_PPC64) += nvram.o
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@ -397,18 +397,16 @@ static int pmac_cpufreq_target( struct cpufreq_policy *policy,
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unsigned int relation)
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{
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unsigned int newstate = 0;
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int rc;
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if (cpufreq_frequency_table_target(policy, pmac_cpu_freqs,
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target_freq, relation, &newstate))
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return -EINVAL;
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return do_set_cpu_speed(newstate, 1);
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}
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rc = do_set_cpu_speed(newstate, 1);
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unsigned int pmac_get_one_cpufreq(int i)
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{
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/* Supports only one CPU for now */
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return (i == 0) ? cur_freq : 0;
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ppc_proc_freq = cur_freq * 1000ul;
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return rc;
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}
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static int pmac_cpufreq_cpu_init(struct cpufreq_policy *policy)
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@ -464,7 +462,7 @@ static int pmac_cpufreq_resume(struct cpufreq_policy *policy)
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/* If we resume, first check if we have a get() function */
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if (get_speed_proc)
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cur_freq = get_speed_proc();
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else
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else)
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cur_freq = 0;
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/* We don't, hrm... we don't really know our speed here, best
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@ -474,6 +472,8 @@ static int pmac_cpufreq_resume(struct cpufreq_policy *policy)
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do_set_cpu_speed(sleep_freq == low_freq ?
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CPUFREQ_LOW : CPUFREQ_HIGH, 0);
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ppc_proc_freq = cur_freq * 1000ul;
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no_schedule = 0;
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return 0;
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}
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@ -714,6 +714,7 @@ out:
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pmac_cpu_freqs[CPUFREQ_LOW].frequency = low_freq;
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pmac_cpu_freqs[CPUFREQ_HIGH].frequency = hi_freq;
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ppc_proc_freq = cur_freq * 1000ul;
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printk(KERN_INFO "Registering PowerMac CPU frequency driver\n");
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printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Boot: %d Mhz\n",
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@ -0,0 +1,323 @@
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/*
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* Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
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* and Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
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* that is iMac G5 and latest single CPU desktop.
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/cpufreq.h>
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#include <linux/init.h>
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#include <linux/completion.h>
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#include <asm/prom.h>
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#include <asm/machdep.h>
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#include <asm/irq.h>
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#include <asm/sections.h>
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#include <asm/cputable.h>
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#include <asm/time.h>
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#include <asm/smu.h>
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(fmt...) printk(fmt)
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#else
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#define DBG(fmt...)
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#endif
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/* see 970FX user manual */
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#define SCOM_PCR 0x0aa001 /* PCR scom addr */
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#define PCR_HILO_SELECT 0x80000000U /* 1 = PCR, 0 = PCRH */
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#define PCR_SPEED_FULL 0x00000000U /* 1:1 speed value */
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#define PCR_SPEED_HALF 0x00020000U /* 1:2 speed value */
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#define PCR_SPEED_QUARTER 0x00040000U /* 1:4 speed value */
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#define PCR_SPEED_MASK 0x000e0000U /* speed mask */
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#define PCR_SPEED_SHIFT 17
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#define PCR_FREQ_REQ_VALID 0x00010000U /* freq request valid */
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#define PCR_VOLT_REQ_VALID 0x00008000U /* volt request valid */
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#define PCR_TARGET_TIME_MASK 0x00006000U /* target time */
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#define PCR_STATLAT_MASK 0x00001f00U /* STATLAT value */
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#define PCR_SNOOPLAT_MASK 0x000000f0U /* SNOOPLAT value */
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#define PCR_SNOOPACC_MASK 0x0000000fU /* SNOOPACC value */
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#define SCOM_PSR 0x408001 /* PSR scom addr */
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/* warning: PSR is a 64 bits register */
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#define PSR_CMD_RECEIVED 0x2000000000000000U /* command received */
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#define PSR_CMD_COMPLETED 0x1000000000000000U /* command completed */
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#define PSR_CUR_SPEED_MASK 0x0300000000000000U /* current speed */
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#define PSR_CUR_SPEED_SHIFT (56)
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/*
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* The G5 only supports two frequencies (Quarter speed is not supported)
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*/
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#define CPUFREQ_HIGH 0
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#define CPUFREQ_LOW 1
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static struct cpufreq_frequency_table g5_cpu_freqs[] = {
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{CPUFREQ_HIGH, 0},
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{CPUFREQ_LOW, 0},
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{0, CPUFREQ_TABLE_END},
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};
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static struct freq_attr* g5_cpu_freqs_attr[] = {
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&cpufreq_freq_attr_scaling_available_freqs,
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NULL,
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};
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/* Power mode data is an array of the 32 bits PCR values to use for
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* the various frequencies, retreived from the device-tree
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*/
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static u32 *g5_pmode_data;
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static int g5_pmode_max;
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static int g5_pmode_cur;
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static DECLARE_MUTEX(g5_switch_mutex);
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static struct smu_sdbp_fvt *g5_fvt_table; /* table of op. points */
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static int g5_fvt_count; /* number of op. points */
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static int g5_fvt_cur; /* current op. point */
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/* ----------------- real hardware interface */
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static void g5_switch_volt(int speed_mode)
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{
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struct smu_simple_cmd cmd;
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DECLARE_COMPLETION(comp);
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smu_queue_simple(&cmd, SMU_CMD_POWER_COMMAND, 8, smu_done_complete,
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&comp, 'V', 'S', 'L', 'E', 'W',
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0xff, g5_fvt_cur+1, speed_mode);
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wait_for_completion(&comp);
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}
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static int g5_switch_freq(int speed_mode)
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{
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struct cpufreq_freqs freqs;
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int to;
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if (g5_pmode_cur == speed_mode)
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return 0;
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down(&g5_switch_mutex);
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freqs.old = g5_cpu_freqs[g5_pmode_cur].frequency;
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freqs.new = g5_cpu_freqs[speed_mode].frequency;
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freqs.cpu = 0;
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cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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/* If frequency is going up, first ramp up the voltage */
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if (speed_mode < g5_pmode_cur)
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g5_switch_volt(speed_mode);
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/* Clear PCR high */
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scom970_write(SCOM_PCR, 0);
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/* Clear PCR low */
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scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0);
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/* Set PCR low */
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scom970_write(SCOM_PCR, PCR_HILO_SELECT |
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g5_pmode_data[speed_mode]);
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/* Wait for completion */
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for (to = 0; to < 10; to++) {
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unsigned long psr = scom970_read(SCOM_PSR);
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if ((psr & PSR_CMD_RECEIVED) == 0 &&
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(((psr >> PSR_CUR_SPEED_SHIFT) ^
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(g5_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
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== 0)
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break;
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if (psr & PSR_CMD_COMPLETED)
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break;
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udelay(100);
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}
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/* If frequency is going down, last ramp the voltage */
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if (speed_mode > g5_pmode_cur)
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g5_switch_volt(speed_mode);
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g5_pmode_cur = speed_mode;
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ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
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cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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up(&g5_switch_mutex);
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return 0;
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}
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static int g5_query_freq(void)
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{
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unsigned long psr = scom970_read(SCOM_PSR);
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int i;
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for (i = 0; i <= g5_pmode_max; i++)
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if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
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(g5_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
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break;
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return i;
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}
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/* ----------------- cpufreq bookkeeping */
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static int g5_cpufreq_verify(struct cpufreq_policy *policy)
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{
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return cpufreq_frequency_table_verify(policy, g5_cpu_freqs);
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}
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static int g5_cpufreq_target(struct cpufreq_policy *policy,
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unsigned int target_freq, unsigned int relation)
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{
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unsigned int newstate = 0;
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if (cpufreq_frequency_table_target(policy, g5_cpu_freqs,
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target_freq, relation, &newstate))
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return -EINVAL;
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return g5_switch_freq(newstate);
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}
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static unsigned int g5_cpufreq_get_speed(unsigned int cpu)
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{
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return g5_cpu_freqs[g5_pmode_cur].frequency;
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}
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static int g5_cpufreq_cpu_init(struct cpufreq_policy *policy)
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{
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if (policy->cpu != 0)
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return -ENODEV;
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policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
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policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
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policy->cur = g5_cpu_freqs[g5_query_freq()].frequency;
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cpufreq_frequency_table_get_attr(g5_cpu_freqs, policy->cpu);
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return cpufreq_frequency_table_cpuinfo(policy,
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g5_cpu_freqs);
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}
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static struct cpufreq_driver g5_cpufreq_driver = {
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.name = "powermac",
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.owner = THIS_MODULE,
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.flags = CPUFREQ_CONST_LOOPS,
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.init = g5_cpufreq_cpu_init,
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.verify = g5_cpufreq_verify,
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.target = g5_cpufreq_target,
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.get = g5_cpufreq_get_speed,
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.attr = g5_cpu_freqs_attr,
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};
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static int __init g5_cpufreq_init(void)
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{
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struct device_node *cpunode;
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unsigned int psize, ssize;
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struct smu_sdbp_header *shdr;
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unsigned long max_freq;
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u32 *valp;
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int rc = -ENODEV;
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/* Look for CPU and SMU nodes */
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cpunode = of_find_node_by_type(NULL, "cpu");
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if (!cpunode) {
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DBG("No CPU node !\n");
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return -ENODEV;
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}
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/* Check 970FX for now */
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valp = (u32 *)get_property(cpunode, "cpu-version", NULL);
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if (!valp) {
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DBG("No cpu-version property !\n");
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goto bail_noprops;
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}
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if (((*valp) >> 16) != 0x3c) {
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DBG("Wrong CPU version: %08x\n", *valp);
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goto bail_noprops;
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}
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/* Look for the powertune data in the device-tree */
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g5_pmode_data = (u32 *)get_property(cpunode, "power-mode-data",&psize);
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if (!g5_pmode_data) {
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DBG("No power-mode-data !\n");
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goto bail_noprops;
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}
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g5_pmode_max = psize / sizeof(u32) - 1;
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/* Look for the FVT table */
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shdr = smu_get_sdb_partition(SMU_SDB_FVT_ID, NULL);
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if (!shdr)
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goto bail_noprops;
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g5_fvt_table = (struct smu_sdbp_fvt *)&shdr[1];
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ssize = (shdr->len * sizeof(u32)) - sizeof(struct smu_sdbp_header);
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g5_fvt_count = ssize / sizeof(struct smu_sdbp_fvt);
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g5_fvt_cur = 0;
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/* Sanity checking */
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if (g5_fvt_count < 1 || g5_pmode_max < 1)
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goto bail_noprops;
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/*
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* From what I see, clock-frequency is always the maximal frequency.
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* The current driver can not slew sysclk yet, so we really only deal
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* with powertune steps for now. We also only implement full freq and
|
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* half freq in this version. So far, I haven't yet seen a machine
|
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* supporting anything else.
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*/
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valp = (u32 *)get_property(cpunode, "clock-frequency", NULL);
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if (!valp)
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return -ENODEV;
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max_freq = (*valp)/1000;
|
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g5_cpu_freqs[0].frequency = max_freq;
|
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g5_cpu_freqs[1].frequency = max_freq/2;
|
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|
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/* Check current frequency */
|
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g5_pmode_cur = g5_query_freq();
|
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if (g5_pmode_cur > 1)
|
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/* We don't support anything but 1:1 and 1:2, fixup ... */
|
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g5_pmode_cur = 1;
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|
||||
/* Force apply current frequency to make sure everything is in
|
||||
* sync (voltage is right for example). Firmware may leave us with
|
||||
* a strange setting ...
|
||||
*/
|
||||
g5_switch_freq(g5_pmode_cur);
|
||||
|
||||
printk(KERN_INFO "Registering G5 CPU frequency driver\n");
|
||||
printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
|
||||
g5_cpu_freqs[1].frequency/1000,
|
||||
g5_cpu_freqs[0].frequency/1000,
|
||||
g5_cpu_freqs[g5_pmode_cur].frequency/1000);
|
||||
|
||||
rc = cpufreq_register_driver(&g5_cpufreq_driver);
|
||||
|
||||
/* We keep the CPU node on hold... hopefully, Apple G5 don't have
|
||||
* hotplug CPU with a dynamic device-tree ...
|
||||
*/
|
||||
return rc;
|
||||
|
||||
bail_noprops:
|
||||
of_node_put(cpunode);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
module_init(g5_cpufreq_init);
|
||||
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -193,18 +193,6 @@ static void pmac_show_cpuinfo(struct seq_file *m)
|
|||
pmac_newworld ? "NewWorld" : "OldWorld");
|
||||
}
|
||||
|
||||
static void pmac_show_percpuinfo(struct seq_file *m, int i)
|
||||
{
|
||||
#ifdef CONFIG_CPU_FREQ_PMAC
|
||||
extern unsigned int pmac_get_one_cpufreq(int i);
|
||||
unsigned int freq = pmac_get_one_cpufreq(i);
|
||||
if (freq != 0) {
|
||||
seq_printf(m, "clock\t\t: %dMHz\n", freq/1000);
|
||||
return;
|
||||
}
|
||||
#endif /* CONFIG_CPU_FREQ_PMAC */
|
||||
}
|
||||
|
||||
#ifndef CONFIG_ADB_CUDA
|
||||
int find_via_cuda(void)
|
||||
{
|
||||
|
|
@ -767,7 +755,6 @@ struct machdep_calls __initdata pmac_md = {
|
|||
.setup_arch = pmac_setup_arch,
|
||||
.init_early = pmac_init_early,
|
||||
.show_cpuinfo = pmac_show_cpuinfo,
|
||||
.show_percpuinfo = pmac_show_percpuinfo,
|
||||
.init_IRQ = pmac_pic_init,
|
||||
.get_irq = mpic_get_irq, /* changed later */
|
||||
.pcibios_fixup = pmac_pcibios_fixup,
|
||||
|
|
|
|||
|
|
@ -173,6 +173,16 @@ config KEXEC
|
|||
support. As of this writing the exact hardware interface is
|
||||
strongly in flux, so no good recommendation can be made.
|
||||
|
||||
source "drivers/cpufreq/Kconfig"
|
||||
|
||||
config CPU_FREQ_PMAC64
|
||||
bool "Support for some Apple G5s"
|
||||
depends on CPU_FREQ && PMAC_SMU && PPC64
|
||||
select CPU_FREQ_TABLE
|
||||
help
|
||||
This adds support for frequency switching on Apple iMac G5,
|
||||
and some of the more recent desktop G5 machines as well.
|
||||
|
||||
config IBMVIO
|
||||
depends on PPC_PSERIES || PPC_ISERIES
|
||||
bool
|
||||
|
|
|
|||
|
|
@ -560,7 +560,7 @@ _GLOBAL(real_readb)
|
|||
isync
|
||||
blr
|
||||
|
||||
/*
|
||||
/*
|
||||
* Do an IO access in real mode
|
||||
*/
|
||||
_GLOBAL(real_writeb)
|
||||
|
|
@ -592,6 +592,76 @@ _GLOBAL(real_writeb)
|
|||
blr
|
||||
#endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */
|
||||
|
||||
/*
|
||||
* SCOM access functions for 970 (FX only for now)
|
||||
*
|
||||
* unsigned long scom970_read(unsigned int address);
|
||||
* void scom970_write(unsigned int address, unsigned long value);
|
||||
*
|
||||
* The address passed in is the 24 bits register address. This code
|
||||
* is 970 specific and will not check the status bits, so you should
|
||||
* know what you are doing.
|
||||
*/
|
||||
_GLOBAL(scom970_read)
|
||||
/* interrupts off */
|
||||
mfmsr r4
|
||||
ori r0,r4,MSR_EE
|
||||
xori r0,r0,MSR_EE
|
||||
mtmsrd r0,1
|
||||
|
||||
/* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
|
||||
* (including parity). On current CPUs they must be 0'd,
|
||||
* and finally or in RW bit
|
||||
*/
|
||||
rlwinm r3,r3,8,0,15
|
||||
ori r3,r3,0x8000
|
||||
|
||||
/* do the actual scom read */
|
||||
sync
|
||||
mtspr SPRN_SCOMC,r3
|
||||
isync
|
||||
mfspr r3,SPRN_SCOMD
|
||||
isync
|
||||
mfspr r0,SPRN_SCOMC
|
||||
isync
|
||||
|
||||
/* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah
|
||||
* that's the best we can do). Not implemented yet as we don't use
|
||||
* the scom on any of the bogus CPUs yet, but may have to be done
|
||||
* ultimately
|
||||
*/
|
||||
|
||||
/* restore interrupts */
|
||||
mtmsrd r4,1
|
||||
blr
|
||||
|
||||
|
||||
_GLOBAL(scom970_write)
|
||||
/* interrupts off */
|
||||
mfmsr r5
|
||||
ori r0,r5,MSR_EE
|
||||
xori r0,r0,MSR_EE
|
||||
mtmsrd r0,1
|
||||
|
||||
/* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
|
||||
* (including parity). On current CPUs they must be 0'd.
|
||||
*/
|
||||
|
||||
rlwinm r3,r3,8,0,15
|
||||
|
||||
sync
|
||||
mtspr SPRN_SCOMD,r4 /* write data */
|
||||
isync
|
||||
mtspr SPRN_SCOMC,r3 /* write command */
|
||||
isync
|
||||
mfspr 3,SPRN_SCOMC
|
||||
isync
|
||||
|
||||
/* restore interrupts */
|
||||
mtmsrd r5,1
|
||||
blr
|
||||
|
||||
|
||||
/*
|
||||
* Create a kernel thread
|
||||
* kernel_thread(fn, arg, flags)
|
||||
|
|
|
|||
|
|
@ -845,6 +845,18 @@ int smu_queue_i2c(struct smu_i2c_cmd *cmd)
|
|||
return 0;
|
||||
}
|
||||
|
||||
struct smu_sdbp_header *smu_get_sdb_partition(int id, unsigned int *size)
|
||||
{
|
||||
char pname[32];
|
||||
|
||||
if (!smu)
|
||||
return NULL;
|
||||
|
||||
sprintf(pname, "sdb-partition-%02x", id);
|
||||
return (struct smu_sdbp_header *)get_property(smu->of_node,
|
||||
pname, size);
|
||||
}
|
||||
EXPORT_SYMBOL(smu_get_sdb_partition);
|
||||
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -396,6 +396,9 @@
|
|||
#define SPRN_VRSAVE 0x100 /* Vector Register Save Register */
|
||||
#define SPRN_XER 0x001 /* Fixed Point Exception Register */
|
||||
|
||||
#define SPRN_SCOMC 0x114 /* SCOM Access Control */
|
||||
#define SPRN_SCOMD 0x115 /* SCOM Access DATA */
|
||||
|
||||
/* Performance monitor SPRs */
|
||||
#ifdef CONFIG_PPC64
|
||||
#define SPRN_MMCR0 795
|
||||
|
|
@ -594,7 +597,11 @@ static inline void ppc64_runlatch_off(void)
|
|||
mtspr(SPRN_CTRLT, ctrl);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
extern unsigned long scom970_read(unsigned int address);
|
||||
extern void scom970_write(unsigned int address, unsigned long value);
|
||||
|
||||
#endif /* CONFIG_PPC64 */
|
||||
|
||||
#define __get_SP() ({unsigned long sp; \
|
||||
asm volatile("mr %0,1": "=r" (sp)); sp;})
|
||||
|
|
|
|||
|
|
@ -144,7 +144,11 @@
|
|||
* - lenght 8 ("VSLEWxyz") has 3 additional bytes appended, and is
|
||||
* used to set the voltage slewing point. The SMU replies with "DONE"
|
||||
* I yet have to figure out their exact meaning of those 3 bytes in
|
||||
* both cases.
|
||||
* both cases. They seem to be:
|
||||
* x = processor mask
|
||||
* y = op. point index
|
||||
* z = processor freq. step index
|
||||
* I haven't yet decyphered result codes
|
||||
*
|
||||
*/
|
||||
#define SMU_CMD_POWER_COMMAND 0xaa
|
||||
|
|
@ -333,6 +337,60 @@ extern int smu_queue_i2c(struct smu_i2c_cmd *cmd);
|
|||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
|
||||
/*
|
||||
* - SMU "sdb" partitions informations -
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Partition header format
|
||||
*/
|
||||
struct smu_sdbp_header {
|
||||
__u8 id;
|
||||
__u8 len;
|
||||
__u8 version;
|
||||
__u8 flags;
|
||||
};
|
||||
|
||||
/*
|
||||
* 32 bits integers are usually encoded with 2x16 bits swapped,
|
||||
* this demangles them
|
||||
*/
|
||||
#define SMU_U32_MIX(x) ((((x) << 16) & 0xffff0000u) | (((x) >> 16) & 0xffffu))
|
||||
|
||||
/* This is the definition of the SMU sdb-partition-0x12 table (called
|
||||
* CPU F/V/T operating points in Darwin). The definition for all those
|
||||
* SMU tables should be moved to some separate file
|
||||
*/
|
||||
#define SMU_SDB_FVT_ID 0x12
|
||||
|
||||
struct smu_sdbp_fvt {
|
||||
__u32 sysclk; /* Base SysClk frequency in Hz for
|
||||
* this operating point
|
||||
*/
|
||||
__u8 pad;
|
||||
__u8 maxtemp; /* Max temp. supported by this
|
||||
* operating point
|
||||
*/
|
||||
|
||||
__u16 volts[3]; /* CPU core voltage for the 3
|
||||
* PowerTune modes, a mode with
|
||||
* 0V = not supported.
|
||||
*/
|
||||
};
|
||||
|
||||
#ifdef __KERNEL__
|
||||
/*
|
||||
* This returns the pointer to an SMU "sdb" partition data or NULL
|
||||
* if not found. The data format is described below
|
||||
*/
|
||||
extern struct smu_sdbp_header *smu_get_sdb_partition(int id,
|
||||
unsigned int *size);
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
|
||||
/*
|
||||
* - Userland interface -
|
||||
*/
|
||||
|
|
|
|||
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