drm/nouveau: simplify fake gpu objects
Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
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a8eaebc6c5
Коммит
43efc9ce25
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@ -135,20 +135,19 @@ enum nouveau_flags {
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#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
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#define NVOBJ_FLAG_ZERO_FREE (1 << 2)
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#define NVOBJ_FLAG_FAKE (1 << 3)
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struct nouveau_gpuobj {
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struct drm_device *dev;
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struct list_head list;
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struct drm_mm_node *im_pramin;
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struct nouveau_bo *im_backing;
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uint32_t im_backing_start;
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uint32_t *im_backing_suspend;
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int im_bound;
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uint32_t flags;
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int refcount;
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u32 size;
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u32 pinst;
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u32 cinst;
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u64 vinst;
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@ -753,9 +752,8 @@ extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
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struct nouveau_gpuobj **);
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extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
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struct nouveau_gpuobj **);
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extern int nouveau_gpuobj_new_fake(struct drm_device *,
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uint32_t p_offset, uint32_t b_offset,
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uint32_t size, uint32_t flags,
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extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
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u32 size, u32 flags,
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struct nouveau_gpuobj **);
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extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
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uint64_t offset, uint64_t size, int access,
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@ -91,6 +91,7 @@ nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan,
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gpuobj->dev = dev;
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gpuobj->flags = flags;
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gpuobj->refcount = 1;
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gpuobj->size = size;
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list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
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@ -133,25 +134,23 @@ nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan,
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/* calculate the various different addresses for the object */
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if (chan) {
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gpuobj->pinst = gpuobj->im_pramin->start +
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chan->ramin->im_pramin->start;
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gpuobj->pinst = gpuobj->im_pramin->start + chan->ramin->pinst;
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if (dev_priv->card_type < NV_50) {
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gpuobj->cinst = gpuobj->pinst;
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} else {
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gpuobj->cinst = gpuobj->im_pramin->start;
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gpuobj->vinst = gpuobj->im_pramin->start +
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chan->ramin->im_backing_start;
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chan->ramin->vinst;
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}
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} else {
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gpuobj->pinst = gpuobj->im_pramin->start;
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gpuobj->cinst = 0xdeadbeef;
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gpuobj->vinst = gpuobj->im_backing_start;
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}
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if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) {
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int i;
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for (i = 0; i < gpuobj->im_pramin->size; i += 4)
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for (i = 0; i < gpuobj->size; i += 4)
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nv_wo32(gpuobj, i, 0);
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engine->instmem.flush(dev);
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}
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@ -237,7 +236,7 @@ nouveau_gpuobj_del(struct nouveau_gpuobj *gpuobj)
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NV_DEBUG(dev, "gpuobj %p\n", gpuobj);
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if (gpuobj->im_pramin && (gpuobj->flags & NVOBJ_FLAG_ZERO_FREE)) {
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for (i = 0; i < gpuobj->im_pramin->size; i += 4)
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for (i = 0; i < gpuobj->size; i += 4)
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nv_wo32(gpuobj, i, 0);
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engine->instmem.flush(dev);
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}
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@ -245,15 +244,11 @@ nouveau_gpuobj_del(struct nouveau_gpuobj *gpuobj)
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if (gpuobj->dtor)
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gpuobj->dtor(dev, gpuobj);
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if (gpuobj->im_backing && !(gpuobj->flags & NVOBJ_FLAG_FAKE))
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if (gpuobj->im_backing)
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engine->instmem.clear(dev, gpuobj);
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if (gpuobj->im_pramin) {
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if (gpuobj->flags & NVOBJ_FLAG_FAKE)
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kfree(gpuobj->im_pramin);
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else
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drm_mm_put_block(gpuobj->im_pramin);
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}
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if (gpuobj->im_pramin)
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drm_mm_put_block(gpuobj->im_pramin);
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list_del(&gpuobj->list);
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@ -274,56 +269,37 @@ nouveau_gpuobj_ref(struct nouveau_gpuobj *ref, struct nouveau_gpuobj **ptr)
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}
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int
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nouveau_gpuobj_new_fake(struct drm_device *dev, uint32_t p_offset,
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uint32_t b_offset, uint32_t size,
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uint32_t flags, struct nouveau_gpuobj **pgpuobj)
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nouveau_gpuobj_new_fake(struct drm_device *dev, u32 pinst, u64 vinst,
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u32 size, u32 flags, struct nouveau_gpuobj **pgpuobj)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *gpuobj = NULL;
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int i;
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NV_DEBUG(dev,
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"p_offset=0x%08x b_offset=0x%08x size=0x%08x flags=0x%08x\n",
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p_offset, b_offset, size, flags);
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"pinst=0x%08x vinst=0x%010llx size=0x%08x flags=0x%08x\n",
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pinst, vinst, size, flags);
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gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL);
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if (!gpuobj)
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return -ENOMEM;
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NV_DEBUG(dev, "gpuobj %p\n", gpuobj);
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gpuobj->dev = dev;
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gpuobj->flags = flags | NVOBJ_FLAG_FAKE;
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gpuobj->flags = flags;
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gpuobj->refcount = 1;
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list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
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if (p_offset != ~0) {
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gpuobj->im_pramin = kzalloc(sizeof(struct drm_mm_node),
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GFP_KERNEL);
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if (!gpuobj->im_pramin) {
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nouveau_gpuobj_ref(NULL, &gpuobj);
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return -ENOMEM;
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}
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gpuobj->im_pramin->start = p_offset;
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gpuobj->im_pramin->size = size;
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}
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if (b_offset != ~0) {
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gpuobj->im_backing = (struct nouveau_bo *)-1;
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gpuobj->im_backing_start = b_offset;
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}
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gpuobj->pinst = gpuobj->im_pramin->start;
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gpuobj->size = size;
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gpuobj->pinst = pinst;
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gpuobj->cinst = 0xdeadbeef;
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gpuobj->vinst = gpuobj->im_backing_start;
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gpuobj->vinst = vinst;
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if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) {
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for (i = 0; i < gpuobj->im_pramin->size; i += 4)
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for (i = 0; i < gpuobj->size; i += 4)
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nv_wo32(gpuobj, i, 0);
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dev_priv->engine.instmem.flush(dev);
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}
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if (pgpuobj)
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*pgpuobj = gpuobj;
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list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
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*pgpuobj = gpuobj;
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return 0;
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}
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@ -830,16 +806,16 @@ nouveau_gpuobj_suspend(struct drm_device *dev)
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}
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list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) {
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if (!gpuobj->im_backing || (gpuobj->flags & NVOBJ_FLAG_FAKE))
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if (!gpuobj->im_backing)
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continue;
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gpuobj->im_backing_suspend = vmalloc(gpuobj->im_pramin->size);
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gpuobj->im_backing_suspend = vmalloc(gpuobj->size);
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if (!gpuobj->im_backing_suspend) {
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nouveau_gpuobj_resume(dev);
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return -ENOMEM;
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}
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for (i = 0; i < gpuobj->im_pramin->size; i += 4)
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for (i = 0; i < gpuobj->size; i += 4)
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gpuobj->im_backing_suspend[i/4] = nv_ro32(gpuobj, i);
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}
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@ -885,7 +861,7 @@ nouveau_gpuobj_resume(struct drm_device *dev)
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if (!gpuobj->im_backing_suspend)
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continue;
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for (i = 0; i < gpuobj->im_pramin->size; i += 4)
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for (i = 0; i < gpuobj->size; i += 4)
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nv_wo32(gpuobj, i, gpuobj->im_backing_suspend[i/4]);
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dev_priv->engine.instmem.flush(dev);
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}
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@ -143,43 +143,26 @@ nv04_instmem_takedown(struct drm_device *dev)
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}
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int
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nv04_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj, uint32_t *sz)
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nv04_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj,
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uint32_t *sz)
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{
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if (gpuobj->im_backing)
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return -EINVAL;
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return 0;
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}
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void
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nv04_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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if (gpuobj && gpuobj->im_backing) {
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if (gpuobj->im_bound)
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dev_priv->engine.instmem.unbind(dev, gpuobj);
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gpuobj->im_backing = NULL;
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}
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}
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int
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nv04_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
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{
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if (!gpuobj->im_pramin || gpuobj->im_bound)
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return -EINVAL;
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gpuobj->im_bound = 1;
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return 0;
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}
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int
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nv04_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
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{
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if (gpuobj->im_bound == 0)
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return -EINVAL;
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gpuobj->im_bound = 0;
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return 0;
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}
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@ -205,8 +205,7 @@ nv50_instmem_init(struct drm_device *dev)
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/*XXX: double-check this is ok */
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dev_priv->vm_vram_pt[i] = chan->vm_vram_pt[i];
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for (v = 0; v < dev_priv->vm_vram_pt[i]->im_pramin->size;
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v += 4)
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for (v = 0; v < dev_priv->vm_vram_pt[i]->size; v += 4)
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BAR0_WI32(dev_priv->vm_vram_pt[i], v, 0);
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BAR0_WI32(chan->vm_pd, 0x10 + (i*8),
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@ -322,11 +321,11 @@ nv50_instmem_suspend(struct drm_device *dev)
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struct nouveau_gpuobj *ramin = chan->ramin;
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int i;
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ramin->im_backing_suspend = vmalloc(ramin->im_pramin->size);
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ramin->im_backing_suspend = vmalloc(ramin->size);
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if (!ramin->im_backing_suspend)
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return -ENOMEM;
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for (i = 0; i < ramin->im_pramin->size; i += 4)
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for (i = 0; i < ramin->size; i += 4)
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ramin->im_backing_suspend[i/4] = nv_ri32(dev, i);
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return 0;
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}
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@ -340,8 +339,8 @@ nv50_instmem_resume(struct drm_device *dev)
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struct nouveau_gpuobj *ramin = chan->ramin;
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int i;
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nv_wr32(dev, NV50_PUNK_BAR0_PRAMIN, (ramin->im_backing_start >> 16));
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for (i = 0; i < ramin->im_pramin->size; i += 4)
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nv_wr32(dev, NV50_PUNK_BAR0_PRAMIN, (ramin->vinst >> 16));
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for (i = 0; i < ramin->size; i += 4)
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BAR0_WI32(ramin, i, ramin->im_backing_suspend[i/4]);
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vfree(ramin->im_backing_suspend);
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ramin->im_backing_suspend = NULL;
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@ -387,9 +386,7 @@ nv50_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj,
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return ret;
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}
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gpuobj->im_backing_start = gpuobj->im_backing->bo.mem.mm_node->start;
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gpuobj->im_backing_start <<= PAGE_SHIFT;
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gpuobj->vinst = gpuobj->im_backing->bo.mem.mm_node->start << PAGE_SHIFT;
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return 0;
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}
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@ -424,11 +421,11 @@ nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
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pte = (gpuobj->im_pramin->start >> 12) << 1;
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pte_end = ((gpuobj->im_pramin->size >> 12) << 1) + pte;
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vram = gpuobj->im_backing_start;
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vram = gpuobj->vinst;
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NV_DEBUG(dev, "pramin=0x%lx, pte=%d, pte_end=%d\n",
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gpuobj->im_pramin->start, pte, pte_end);
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NV_DEBUG(dev, "first vram page: 0x%08x\n", gpuobj->im_backing_start);
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NV_DEBUG(dev, "first vram page: 0x%010llx\n", gpuobj->vinst);
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vram |= 1;
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if (dev_priv->vram_sys_base) {
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@ -50,8 +50,7 @@ nvc0_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj,
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return ret;
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}
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gpuobj->im_backing_start = gpuobj->im_backing->bo.mem.mm_node->start;
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gpuobj->im_backing_start <<= PAGE_SHIFT;
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gpuobj->vinst = gpuobj->im_backing->bo.mem.mm_node->start << PAGE_SHIFT;
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return 0;
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}
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@ -84,11 +83,11 @@ nvc0_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
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pte = gpuobj->im_pramin->start >> 12;
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pte_end = (gpuobj->im_pramin->size >> 12) + pte;
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vram = gpuobj->im_backing_start;
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vram = gpuobj->vinst;
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NV_DEBUG(dev, "pramin=0x%lx, pte=%d, pte_end=%d\n",
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gpuobj->im_pramin->start, pte, pte_end);
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NV_DEBUG(dev, "first vram page: 0x%08x\n", gpuobj->im_backing_start);
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NV_DEBUG(dev, "first vram page: 0x%010llx\n", gpuobj->vinst);
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while (pte < pte_end) {
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nv_wr32(dev, 0x702000 + (pte * 8), (vram >> 8) | 1);
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