Merge branch 'late/clksrc' into late/cleanup
There is no reason to keep the clksrc cleanups separate from the other cleanups, and this resolves some merge conflicts. Conflicts: arch/arm/mach-spear/spear13xx.c drivers/irqchip/Makefile
This commit is contained in:
Arnd Bergmann
Коммит
442a33ebce
|
|
@ -0,0 +1,56 @@
|
|||
Frequently asked questions about the sunxi clock system
|
||||
=======================================================
|
||||
|
||||
This document contains useful bits of information that people tend to ask
|
||||
about the sunxi clock system, as well as accompanying ASCII art when adequate.
|
||||
|
||||
Q: Why is the main 24MHz oscillator gatable? Wouldn't that break the
|
||||
system?
|
||||
|
||||
A: The 24MHz oscillator allows gating to save power. Indeed, if gated
|
||||
carelessly the system would stop functioning, but with the right
|
||||
steps, one can gate it and keep the system running. Consider this
|
||||
simplified suspend example:
|
||||
|
||||
While the system is operational, you would see something like
|
||||
|
||||
24MHz 32kHz
|
||||
|
|
||||
PLL1
|
||||
\
|
||||
\_ CPU Mux
|
||||
|
|
||||
[CPU]
|
||||
|
||||
When you are about to suspend, you switch the CPU Mux to the 32kHz
|
||||
oscillator:
|
||||
|
||||
24Mhz 32kHz
|
||||
| |
|
||||
PLL1 |
|
||||
/
|
||||
CPU Mux _/
|
||||
|
|
||||
[CPU]
|
||||
|
||||
Finally you can gate the main oscillator
|
||||
|
||||
32kHz
|
||||
|
|
||||
|
|
||||
/
|
||||
CPU Mux _/
|
||||
|
|
||||
[CPU]
|
||||
|
||||
Q: Were can I learn more about the sunxi clocks?
|
||||
|
||||
A: The linux-sunxi wiki contains a page documenting the clock registers,
|
||||
you can find it at
|
||||
|
||||
http://linux-sunxi.org/A10/CCM
|
||||
|
||||
The authoritative source for information at this time is the ccmu driver
|
||||
released by Allwinner, you can find it at
|
||||
|
||||
https://github.com/linux-sunxi/linux-sunxi/tree/sunxi-3.0/arch/arm/mach-sun4i/clock/ccmu
|
||||
|
|
@ -174,9 +174,9 @@ int clk_foo_enable(struct clk_hw *hw)
|
|||
};
|
||||
|
||||
Below is a matrix detailing which clk_ops are mandatory based upon the
|
||||
hardware capbilities of that clock. A cell marked as "y" means
|
||||
hardware capabilities of that clock. A cell marked as "y" means
|
||||
mandatory, a cell marked as "n" implies that either including that
|
||||
callback is invalid or otherwise uneccesary. Empty cells are either
|
||||
callback is invalid or otherwise unnecessary. Empty cells are either
|
||||
optional or must be evaluated on a case-by-case basis.
|
||||
|
||||
clock hardware characteristics
|
||||
|
|
|
|||
|
|
@ -1,19 +1,84 @@
|
|||
NVIDIA Tegra Power Management Controller (PMC)
|
||||
|
||||
Properties:
|
||||
The PMC block interacts with an external Power Management Unit. The PMC
|
||||
mostly controls the entry and exit of the system from different sleep
|
||||
modes. It provides power-gating controllers for SoC and CPU power-islands.
|
||||
|
||||
Required properties:
|
||||
- name : Should be pmc
|
||||
- compatible : Should contain "nvidia,tegra<chip>-pmc".
|
||||
- reg : Offset and length of the register set for the device
|
||||
- clocks : Must contain an entry for each entry in clock-names.
|
||||
- clock-names : Must include the following entries:
|
||||
"pclk" (The Tegra clock of that name),
|
||||
"clk32k_in" (The 32KHz clock input to Tegra).
|
||||
|
||||
Optional properties:
|
||||
- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
|
||||
The PMU is an external Power Management Unit, whose interrupt output
|
||||
signal is fed into the PMC. This signal is optionally inverted, and then
|
||||
fed into the ARM GIC. The PMC is not involved in the detection or
|
||||
handling of this interrupt signal, merely its inversion.
|
||||
- nvidia,suspend-mode : The suspend mode that the platform should use.
|
||||
Valid values are 0, 1 and 2:
|
||||
0 (LP0): CPU + Core voltage off and DRAM in self-refresh
|
||||
1 (LP1): CPU voltage off and DRAM in self-refresh
|
||||
2 (LP2): CPU voltage off
|
||||
- nvidia,core-power-req-active-high : Boolean, core power request active-high
|
||||
- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high
|
||||
- nvidia,combined-power-req : Boolean, combined power request for CPU & Core
|
||||
- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC)
|
||||
is enabled.
|
||||
|
||||
Required properties when nvidia,suspend-mode is specified:
|
||||
- nvidia,cpu-pwr-good-time : CPU power good time in uS.
|
||||
- nvidia,cpu-pwr-off-time : CPU power off time in uS.
|
||||
- nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time>
|
||||
Core power good time in uS.
|
||||
- nvidia,core-pwr-off-time : Core power off time in uS.
|
||||
|
||||
Required properties when nvidia,suspend-mode=<0>:
|
||||
- nvidia,lp0-vec : <start length> Starting address and length of LP0 vector
|
||||
The LP0 vector contains the warm boot code that is executed by AVP when
|
||||
resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7
|
||||
processor and always being the first boot processor when chip is power on
|
||||
or resume from deep sleep mode. When the system is resumed from the deep
|
||||
sleep mode, the warm boot code will restore some PLLs, clocks and then
|
||||
bring up CPU0 for resuming the system.
|
||||
|
||||
Example:
|
||||
|
||||
/ SoC dts including file
|
||||
pmc@7000f400 {
|
||||
compatible = "nvidia,tegra20-pmc";
|
||||
reg = <0x7000e400 0x400>;
|
||||
clocks = <&tegra_car 110>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
nvidia,invert-interrupt;
|
||||
nvidia,suspend-mode = <1>;
|
||||
nvidia,cpu-pwr-good-time = <2000>;
|
||||
nvidia,cpu-pwr-off-time = <100>;
|
||||
nvidia,core-pwr-good-time = <3845 3845>;
|
||||
nvidia,core-pwr-off-time = <458>;
|
||||
nvidia,core-power-req-active-high;
|
||||
nvidia,sys-clock-req-active-high;
|
||||
nvidia,lp0-vec = <0xbdffd000 0x2000>;
|
||||
};
|
||||
|
||||
/ Tegra board dts file
|
||||
{
|
||||
...
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
...
|
||||
};
|
||||
|
|
|
|||
|
|
@ -35,36 +35,83 @@ Required properties:
|
|||
|
||||
Timing properties for child nodes. All are optional and default to 0.
|
||||
|
||||
- gpmc,sync-clk: Minimum clock period for synchronous mode, in picoseconds
|
||||
- gpmc,sync-clk-ps: Minimum clock period for synchronous mode, in picoseconds
|
||||
|
||||
Chip-select signal timings corresponding to GPMC_CONFIG2:
|
||||
- gpmc,cs-on: Assertion time
|
||||
- gpmc,cs-rd-off: Read deassertion time
|
||||
- gpmc,cs-wr-off: Write deassertion time
|
||||
Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2:
|
||||
- gpmc,cs-on-ns: Assertion time
|
||||
- gpmc,cs-rd-off-ns: Read deassertion time
|
||||
- gpmc,cs-wr-off-ns: Write deassertion time
|
||||
|
||||
ADV signal timings corresponding to GPMC_CONFIG3:
|
||||
- gpmc,adv-on: Assertion time
|
||||
- gpmc,adv-rd-off: Read deassertion time
|
||||
- gpmc,adv-wr-off: Write deassertion time
|
||||
ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3:
|
||||
- gpmc,adv-on-ns: Assertion time
|
||||
- gpmc,adv-rd-off-ns: Read deassertion time
|
||||
- gpmc,adv-wr-off-ns: Write deassertion time
|
||||
|
||||
WE signals timings corresponding to GPMC_CONFIG4:
|
||||
- gpmc,we-on: Assertion time
|
||||
- gpmc,we-off: Deassertion time
|
||||
WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
|
||||
- gpmc,we-on-ns Assertion time
|
||||
- gpmc,we-off-ns: Deassertion time
|
||||
|
||||
OE signals timings corresponding to GPMC_CONFIG4:
|
||||
- gpmc,oe-on: Assertion time
|
||||
- gpmc,oe-off: Deassertion time
|
||||
OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
|
||||
- gpmc,oe-on-ns: Assertion time
|
||||
- gpmc,oe-off-ns: Deassertion time
|
||||
|
||||
Access time and cycle time timings corresponding to GPMC_CONFIG5:
|
||||
- gpmc,page-burst-access: Multiple access word delay
|
||||
- gpmc,access: Start-cycle to first data valid delay
|
||||
- gpmc,rd-cycle: Total read cycle time
|
||||
- gpmc,wr-cycle: Total write cycle time
|
||||
Access time and cycle time timings (in nanoseconds) corresponding to
|
||||
GPMC_CONFIG5:
|
||||
- gpmc,page-burst-access-ns: Multiple access word delay
|
||||
- gpmc,access-ns: Start-cycle to first data valid delay
|
||||
- gpmc,rd-cycle-ns: Total read cycle time
|
||||
- gpmc,wr-cycle-ns: Total write cycle time
|
||||
- gpmc,bus-turnaround-ns: Turn-around time between successive accesses
|
||||
- gpmc,cycle2cycle-delay-ns: Delay between chip-select pulses
|
||||
- gpmc,clk-activation-ns: GPMC clock activation time
|
||||
- gpmc,wait-monitoring-ns: Start of wait monitoring with regard to valid
|
||||
data
|
||||
|
||||
Boolean timing parameters. If property is present parameter enabled and
|
||||
disabled if omitted:
|
||||
- gpmc,adv-extra-delay: ADV signal is delayed by half GPMC clock
|
||||
- gpmc,cs-extra-delay: CS signal is delayed by half GPMC clock
|
||||
- gpmc,cycle2cycle-diffcsen: Add "cycle2cycle-delay" between successive
|
||||
accesses to a different CS
|
||||
- gpmc,cycle2cycle-samecsen: Add "cycle2cycle-delay" between successive
|
||||
accesses to the same CS
|
||||
- gpmc,oe-extra-delay: OE signal is delayed by half GPMC clock
|
||||
- gpmc,we-extra-delay: WE signal is delayed by half GPMC clock
|
||||
- gpmc,time-para-granularity: Multiply all access times by 2
|
||||
|
||||
The following are only applicable to OMAP3+ and AM335x:
|
||||
- gpmc,wr-access
|
||||
- gpmc,wr-data-mux-bus
|
||||
- gpmc,wr-access-ns: In synchronous write mode, for single or
|
||||
burst accesses, defines the number of
|
||||
GPMC_FCLK cycles from start access time
|
||||
to the GPMC_CLK rising edge used by the
|
||||
memory device for the first data capture.
|
||||
- gpmc,wr-data-mux-bus-ns: In address-data multiplex mode, specifies
|
||||
the time when the first data is driven on
|
||||
the address-data bus.
|
||||
|
||||
GPMC chip-select settings properties for child nodes. All are optional.
|
||||
|
||||
- gpmc,burst-length Page/burst length. Must be 4, 8 or 16.
|
||||
- gpmc,burst-wrap Enables wrap bursting
|
||||
- gpmc,burst-read Enables read page/burst mode
|
||||
- gpmc,burst-write Enables write page/burst mode
|
||||
- gpmc,device-nand Device is NAND
|
||||
- gpmc,device-width Total width of device(s) connected to a GPMC
|
||||
chip-select in bytes. The GPMC supports 8-bit
|
||||
and 16-bit devices and so this property must be
|
||||
1 or 2.
|
||||
- gpmc,mux-add-data Address and data multiplexing configuration.
|
||||
Valid values are 1 for address-address-data
|
||||
multiplexing mode and 2 for address-data
|
||||
multiplexing mode.
|
||||
- gpmc,sync-read Enables synchronous read. Defaults to asynchronous
|
||||
is this is not set.
|
||||
- gpmc,sync-write Enables synchronous writes. Defaults to asynchronous
|
||||
is this is not set.
|
||||
- gpmc,wait-pin Wait-pin used by client. Must be less than
|
||||
"gpmc,num-waitpins".
|
||||
- gpmc,wait-on-read Enables wait monitoring on reads.
|
||||
- gpmc,wait-on-write Enables wait monitoring on writes.
|
||||
|
||||
Example for an AM33xx board:
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,22 @@
|
|||
Binding for the axi-clkgen clock generator
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "adi,axi-clkgen".
|
||||
- #clock-cells : from common clock binding; Should always be set to 0.
|
||||
- reg : Address and length of the axi-clkgen register set.
|
||||
- clocks : Phandle and clock specifier for the parent clock.
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : From common clock binding.
|
||||
|
||||
Example:
|
||||
clock@0xff000000 {
|
||||
compatible = "adi,axi-clkgen";
|
||||
#clock-cells = <0>;
|
||||
reg = <0xff000000 0x1000>;
|
||||
clocks = <&osc 1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,303 @@
|
|||
NVIDIA Tegra114 Clock And Reset Controller
|
||||
|
||||
This binding uses the common clock binding:
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
|
||||
for muxing and gating Tegra's clocks, and setting their rates.
|
||||
|
||||
Required properties :
|
||||
- compatible : Should be "nvidia,tegra114-car"
|
||||
- reg : Should contain CAR registers location and length
|
||||
- clocks : Should contain phandle and clock specifiers for two clocks:
|
||||
the 32 KHz "32k_in", and the board-specific oscillator "osc".
|
||||
- #clock-cells : Should be 1.
|
||||
In clock consumers, this cell represents the clock ID exposed by the CAR.
|
||||
|
||||
The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
|
||||
registers. These IDs often match those in the CAR's RST_DEVICES registers,
|
||||
but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
|
||||
this case, those clocks are assigned IDs above 160 in order to highlight
|
||||
this issue. Implementations that interpret these clock IDs as bit values
|
||||
within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
|
||||
explicitly handle these special cases.
|
||||
|
||||
The balance of the clocks controlled by the CAR are assigned IDs of 160 and
|
||||
above.
|
||||
|
||||
0 unassigned
|
||||
1 unassigned
|
||||
2 unassigned
|
||||
3 unassigned
|
||||
4 rtc
|
||||
5 timer
|
||||
6 uarta
|
||||
7 unassigned (register bit affects uartb and vfir)
|
||||
8 unassigned
|
||||
9 sdmmc2
|
||||
10 unassigned (register bit affects spdif_in and spdif_out)
|
||||
11 i2s1
|
||||
12 i2c1
|
||||
13 ndflash
|
||||
14 sdmmc1
|
||||
15 sdmmc4
|
||||
16 unassigned
|
||||
17 pwm
|
||||
18 i2s2
|
||||
19 epp
|
||||
20 unassigned (register bit affects vi and vi_sensor)
|
||||
21 2d
|
||||
22 usbd
|
||||
23 isp
|
||||
24 3d
|
||||
25 unassigned
|
||||
26 disp2
|
||||
27 disp1
|
||||
28 host1x
|
||||
29 vcp
|
||||
30 i2s0
|
||||
31 unassigned
|
||||
|
||||
32 unassigned
|
||||
33 unassigned
|
||||
34 apbdma
|
||||
35 unassigned
|
||||
36 kbc
|
||||
37 unassigned
|
||||
38 unassigned
|
||||
39 unassigned (register bit affects fuse and fuse_burn)
|
||||
40 kfuse
|
||||
41 sbc1
|
||||
42 nor
|
||||
43 unassigned
|
||||
44 sbc2
|
||||
45 unassigned
|
||||
46 sbc3
|
||||
47 i2c5
|
||||
48 dsia
|
||||
49 unassigned
|
||||
50 mipi
|
||||
51 hdmi
|
||||
52 csi
|
||||
53 unassigned
|
||||
54 i2c2
|
||||
55 uartc
|
||||
56 mipi-cal
|
||||
57 emc
|
||||
58 usb2
|
||||
59 usb3
|
||||
60 msenc
|
||||
61 vde
|
||||
62 bsea
|
||||
63 bsev
|
||||
|
||||
64 unassigned
|
||||
65 uartd
|
||||
66 unassigned
|
||||
67 i2c3
|
||||
68 sbc4
|
||||
69 sdmmc3
|
||||
70 unassigned
|
||||
71 owr
|
||||
72 afi
|
||||
73 csite
|
||||
74 unassigned
|
||||
75 unassigned
|
||||
76 la
|
||||
77 trace
|
||||
78 soc_therm
|
||||
79 dtv
|
||||
80 ndspeed
|
||||
81 i2cslow
|
||||
82 dsib
|
||||
83 tsec
|
||||
84 unassigned
|
||||
85 unassigned
|
||||
86 unassigned
|
||||
87 unassigned
|
||||
88 unassigned
|
||||
89 xusb_host
|
||||
90 unassigned
|
||||
91 msenc
|
||||
92 csus
|
||||
93 unassigned
|
||||
94 unassigned
|
||||
95 unassigned (bit affects xusb_dev and xusb_dev_src)
|
||||
|
||||
96 unassigned
|
||||
97 unassigned
|
||||
98 unassigned
|
||||
99 mselect
|
||||
100 tsensor
|
||||
101 i2s3
|
||||
102 i2s4
|
||||
103 i2c4
|
||||
104 sbc5
|
||||
105 sbc6
|
||||
106 d_audio
|
||||
107 apbif
|
||||
108 dam0
|
||||
109 dam1
|
||||
110 dam2
|
||||
111 hda2codec_2x
|
||||
112 unassigned
|
||||
113 audio0_2x
|
||||
114 audio1_2x
|
||||
115 audio2_2x
|
||||
116 audio3_2x
|
||||
117 audio4_2x
|
||||
118 spdif_2x
|
||||
119 actmon
|
||||
120 extern1
|
||||
121 extern2
|
||||
122 extern3
|
||||
123 unassigned
|
||||
124 unassigned
|
||||
125 hda
|
||||
126 unassigned
|
||||
127 se
|
||||
|
||||
128 hda2hdmi
|
||||
129 unassigned
|
||||
130 unassigned
|
||||
131 unassigned
|
||||
132 unassigned
|
||||
133 unassigned
|
||||
134 unassigned
|
||||
135 unassigned
|
||||
136 unassigned
|
||||
137 unassigned
|
||||
138 unassigned
|
||||
139 unassigned
|
||||
140 unassigned
|
||||
141 unassigned
|
||||
142 unassigned
|
||||
143 unassigned (bit affects xusb_falcon_src, xusb_fs_src,
|
||||
xusb_host_src and xusb_ss_src)
|
||||
144 cilab
|
||||
145 cilcd
|
||||
146 cile
|
||||
147 dsialp
|
||||
148 dsiblp
|
||||
149 unassigned
|
||||
150 dds
|
||||
151 unassigned
|
||||
152 dp2
|
||||
153 amx
|
||||
154 adx
|
||||
155 unassigned (bit affects dfll_ref and dfll_soc)
|
||||
156 xusb_ss
|
||||
|
||||
192 uartb
|
||||
193 vfir
|
||||
194 spdif_in
|
||||
195 spdif_out
|
||||
196 vi
|
||||
197 vi_sensor
|
||||
198 fuse
|
||||
199 fuse_burn
|
||||
200 clk_32k
|
||||
201 clk_m
|
||||
202 clk_m_div2
|
||||
203 clk_m_div4
|
||||
204 pll_ref
|
||||
205 pll_c
|
||||
206 pll_c_out1
|
||||
207 pll_c2
|
||||
208 pll_c3
|
||||
209 pll_m
|
||||
210 pll_m_out1
|
||||
211 pll_p
|
||||
212 pll_p_out1
|
||||
213 pll_p_out2
|
||||
214 pll_p_out3
|
||||
215 pll_p_out4
|
||||
216 pll_a
|
||||
217 pll_a_out0
|
||||
218 pll_d
|
||||
219 pll_d_out0
|
||||
220 pll_d2
|
||||
221 pll_d2_out0
|
||||
222 pll_u
|
||||
223 pll_u_480M
|
||||
224 pll_u_60M
|
||||
225 pll_u_48M
|
||||
226 pll_u_12M
|
||||
227 pll_x
|
||||
228 pll_x_out0
|
||||
229 pll_re_vco
|
||||
230 pll_re_out
|
||||
231 pll_e_out0
|
||||
232 spdif_in_sync
|
||||
233 i2s0_sync
|
||||
234 i2s1_sync
|
||||
235 i2s2_sync
|
||||
236 i2s3_sync
|
||||
237 i2s4_sync
|
||||
238 vimclk_sync
|
||||
239 audio0
|
||||
240 audio1
|
||||
241 audio2
|
||||
242 audio3
|
||||
243 audio4
|
||||
244 spdif
|
||||
245 clk_out_1
|
||||
246 clk_out_2
|
||||
247 clk_out_3
|
||||
248 blink
|
||||
252 xusb_host_src
|
||||
253 xusb_falcon_src
|
||||
254 xusb_fs_src
|
||||
255 xusb_ss_src
|
||||
256 xusb_dev_src
|
||||
257 xusb_dev
|
||||
258 xusb_hs_src
|
||||
259 sclk
|
||||
260 hclk
|
||||
261 pclk
|
||||
262 cclk_g
|
||||
263 cclk_lp
|
||||
264 dfll_ref
|
||||
265 dfll_soc
|
||||
|
||||
Example SoC include file:
|
||||
|
||||
/ {
|
||||
tegra_car: clock {
|
||||
compatible = "nvidia,tegra114-car";
|
||||
reg = <0x60006000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
usb@c5004000 {
|
||||
clocks = <&tegra_car 58>; /* usb2 */
|
||||
};
|
||||
};
|
||||
|
||||
Example board file:
|
||||
|
||||
/ {
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
osc: clock@0 {
|
||||
compatible = "fixed-clock";
|
||||
reg = <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
clk_32k: clock@1 {
|
||||
compatible = "fixed-clock";
|
||||
reg = <1>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
&tegra_car {
|
||||
clocks = <&clk_32k> <&osc>;
|
||||
};
|
||||
};
|
||||
|
|
@ -120,8 +120,8 @@ Required properties :
|
|||
90 clk_d
|
||||
91 unassigned
|
||||
92 sus
|
||||
93 cdev1
|
||||
94 cdev2
|
||||
93 cdev2
|
||||
94 cdev1
|
||||
95 unassigned
|
||||
|
||||
96 uart2
|
||||
|
|
|
|||
|
|
@ -0,0 +1,44 @@
|
|||
Device Tree Clock bindings for arch-sunxi
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be one of the following:
|
||||
"allwinner,sun4i-osc-clk" - for a gatable oscillator
|
||||
"allwinner,sun4i-pll1-clk" - for the main PLL clock
|
||||
"allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
|
||||
"allwinner,sun4i-axi-clk" - for the AXI clock
|
||||
"allwinner,sun4i-ahb-clk" - for the AHB clock
|
||||
"allwinner,sun4i-apb0-clk" - for the APB0 clock
|
||||
"allwinner,sun4i-apb1-clk" - for the APB1 clock
|
||||
"allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
|
||||
|
||||
Required properties for all clocks:
|
||||
- reg : shall be the control register address for the clock.
|
||||
- clocks : shall be the input parent clock(s) phandle for the clock
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
|
||||
For example:
|
||||
|
||||
osc24M: osc24M@01c20050 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-osc-clk";
|
||||
reg = <0x01c20050 0x4>;
|
||||
clocks = <&osc24M_fixed>;
|
||||
};
|
||||
|
||||
pll1: pll1@01c20000 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-pll1-clk";
|
||||
reg = <0x01c20000 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
};
|
||||
|
||||
cpu: cpu@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-cpu-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&osc32k>, <&osc24M>, <&pll1>;
|
||||
};
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
VIA/Wondermedia VT8500 GPIO Controller
|
||||
-----------------------------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible : "via,vt8500-gpio", "wm,wm8505-gpio"
|
||||
or "wm,wm8650-gpio" depending on your SoC
|
||||
- reg : Should contain 1 register range (address and length)
|
||||
- #gpio-cells : should be <3>.
|
||||
1) bank
|
||||
2) pin number
|
||||
3) flags - should be 0
|
||||
|
||||
Example:
|
||||
|
||||
gpio: gpio-controller@d8110000 {
|
||||
compatible = "via,vt8500-gpio";
|
||||
gpio-controller;
|
||||
reg = <0xd8110000 0x10000>;
|
||||
#gpio-cells = <3>;
|
||||
};
|
||||
|
||||
vibrate {
|
||||
gpios = <&gpio 0 1 0>; /* Bank 0, Pin 1, No flags */
|
||||
};
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
Samsung S3C24XX Interrupt Controllers
|
||||
|
||||
The S3C24XX SoCs contain a custom set of interrupt controllers providing a
|
||||
varying number of interrupt sources. The set consists of a main- and sub-
|
||||
controller and on newer SoCs even a second main controller.
|
||||
|
||||
Required properties:
|
||||
- compatible: Compatible property value should be "samsung,s3c2410-irq"
|
||||
for machines before s3c2416 and "samsung,s3c2416-irq" for s3c2416 and later.
|
||||
|
||||
- reg: Physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
interrupt source. The value shall be 4 and interrupt descriptor shall
|
||||
have the following format:
|
||||
<ctrl_num parent_irq ctrl_irq type>
|
||||
|
||||
ctrl_num contains the controller to use:
|
||||
- 0 ... main controller
|
||||
- 1 ... sub controller
|
||||
- 2 ... second main controller on s3c2416 and s3c2450
|
||||
parent_irq contains the parent bit in the main controller and will be
|
||||
ignored in main controllers
|
||||
ctrl_irq contains the interrupt bit of the controller
|
||||
type contains the trigger type to use
|
||||
|
||||
Example:
|
||||
|
||||
interrupt-controller@4a000000 {
|
||||
compatible = "samsung,s3c2410-irq";
|
||||
reg = <0x4a000000 0x100>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells=<4>;
|
||||
};
|
||||
|
||||
[...]
|
||||
|
||||
serial@50000000 {
|
||||
compatible = "samsung,s3c2410-uart";
|
||||
reg = <0x50000000 0x4000>;
|
||||
interrupt-parent = <&subintc>;
|
||||
interrupts = <1 28 0 4>, <1 28 1 4>;
|
||||
};
|
||||
|
||||
rtc@57000000 {
|
||||
compatible = "samsung,s3c2410-rtc";
|
||||
reg = <0x57000000 0x100>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 30 0 3>, <0 8 0 3>;
|
||||
};
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
Device tree bindings for NOR flash connect to TI GPMC
|
||||
|
||||
NOR flash connected to the TI GPMC (found on OMAP boards) are represented as
|
||||
child nodes of the GPMC controller with a name of "nor".
|
||||
|
||||
All timing relevant properties as well as generic GPMC child properties are
|
||||
explained in a separate documents. Please refer to
|
||||
Documentation/devicetree/bindings/bus/ti-gpmc.txt
|
||||
|
||||
Required properties:
|
||||
- bank-width: Width of NOR flash in bytes. GPMC supports 8-bit and
|
||||
16-bit devices and so must be either 1 or 2 bytes.
|
||||
- compatible: Documentation/devicetree/bindings/mtd/mtd-physmap.txt
|
||||
- gpmc,cs-on-ns: Chip-select assertion time
|
||||
- gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads
|
||||
- gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes
|
||||
- gpmc,oe-on-ns: Output-enable assertion time
|
||||
- gpmc,oe-off-ns: Output-enable de-assertion time
|
||||
- gpmc,we-on-ns Write-enable assertion time
|
||||
- gpmc,we-off-ns: Write-enable de-assertion time
|
||||
- gpmc,access-ns: Start cycle to first data capture (read access)
|
||||
- gpmc,rd-cycle-ns: Total read cycle time
|
||||
- gpmc,wr-cycle-ns: Total write cycle time
|
||||
- linux,mtd-name: Documentation/devicetree/bindings/mtd/mtd-physmap.txt
|
||||
- reg: Chip-select, base address (relative to chip-select)
|
||||
and size of NOR flash. Note that base address will be
|
||||
typically 0 as this is the start of the chip-select.
|
||||
|
||||
Optional properties:
|
||||
- gpmc,XXX Additional GPMC timings and settings parameters. See
|
||||
Documentation/devicetree/bindings/bus/ti-gpmc.txt
|
||||
|
||||
Optional properties for partiton table parsing:
|
||||
- #address-cells: should be set to 1
|
||||
- #size-cells: should be set to 1
|
||||
|
||||
Example:
|
||||
|
||||
gpmc: gpmc@6e000000 {
|
||||
compatible = "ti,omap3430-gpmc", "simple-bus";
|
||||
ti,hwmods = "gpmc";
|
||||
reg = <0x6e000000 0x1000>;
|
||||
interrupts = <20>;
|
||||
gpmc,num-cs = <8>;
|
||||
gpmc,num-waitpins = <4>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
ranges = <0 0 0x10000000 0x08000000>;
|
||||
|
||||
nor@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
linux,mtd-name= "intel,pf48f6000m0y1be";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0 0 0x08000000>;
|
||||
bank-width = <2>;
|
||||
|
||||
gpmc,mux-add-data;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <186>;
|
||||
gpmc,cs-wr-off-ns = <186>;
|
||||
gpmc,adv-on-ns = <12>;
|
||||
gpmc,adv-rd-off-ns = <48>;
|
||||
gpmc,adv-wr-off-ns = <48>;
|
||||
gpmc,oe-on-ns = <54>;
|
||||
gpmc,oe-off-ns = <168>;
|
||||
gpmc,we-on-ns = <54>;
|
||||
gpmc,we-off-ns = <168>;
|
||||
gpmc,rd-cycle-ns = <186>;
|
||||
gpmc,wr-cycle-ns = <186>;
|
||||
gpmc,access-ns = <114>;
|
||||
gpmc,page-burst-access-ns = <6>;
|
||||
gpmc,bus-turnaround-ns = <12>;
|
||||
gpmc,cycle2cycle-delay-ns = <18>;
|
||||
gpmc,wr-data-mux-bus-ns = <90>;
|
||||
gpmc,wr-access-ns = <186>;
|
||||
gpmc,cycle2cycle-samecsen;
|
||||
gpmc,cycle2cycle-diffcsen;
|
||||
|
||||
partition@0 {
|
||||
label = "bootloader-nor";
|
||||
reg = <0 0x40000>;
|
||||
};
|
||||
partition@0x40000 {
|
||||
label = "params-nor";
|
||||
reg = <0x40000 0x40000>;
|
||||
};
|
||||
partition@0x80000 {
|
||||
label = "kernel-nor";
|
||||
reg = <0x80000 0x200000>;
|
||||
};
|
||||
partition@0x280000 {
|
||||
label = "filesystem-nor";
|
||||
reg = <0x240000 0x7d80000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -10,6 +10,8 @@ Documentation/devicetree/bindings/bus/ti-gpmc.txt
|
|||
Required properties:
|
||||
|
||||
- reg: The CS line the peripheral is connected to
|
||||
- gpmc,device-width Width of the ONENAND device connected to the GPMC
|
||||
in bytes. Must be 1 or 2.
|
||||
|
||||
Optional properties:
|
||||
|
||||
|
|
@ -34,6 +36,7 @@ Example for an OMAP3430 board:
|
|||
|
||||
onenand@0 {
|
||||
reg = <0 0 0>; /* CS0, offset 0 */
|
||||
gpmc,device-width = <2>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,97 @@
|
|||
Device tree bindings for Ethernet chip connected to TI GPMC
|
||||
|
||||
Besides being used to interface with external memory devices, the
|
||||
General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
|
||||
such as ethernet controllers to processors using the TI GPMC as a data bus.
|
||||
|
||||
Ethernet controllers connected to TI GPMC are represented as child nodes of
|
||||
the GPMC controller with an "ethernet" name.
|
||||
|
||||
All timing relevant properties as well as generic GPMC child properties are
|
||||
explained in a separate documents. Please refer to
|
||||
Documentation/devicetree/bindings/bus/ti-gpmc.txt
|
||||
|
||||
For the properties relevant to the ethernet controller connected to the GPMC
|
||||
refer to the binding documentation of the device. For example, the documentation
|
||||
for the SMSC 911x is Documentation/devicetree/bindings/net/smsc911x.txt
|
||||
|
||||
Child nodes need to specify the GPMC bus address width using the "bank-width"
|
||||
property but is possible that an ethernet controller also has a property to
|
||||
specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
|
||||
address width, it supports devices with 32-bit word registers.
|
||||
For example with an SMSC LAN911x/912x controller connected to the TI GPMC on an
|
||||
OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
|
||||
|
||||
Required properties:
|
||||
- bank-width: Address width of the device in bytes. GPMC supports 8-bit
|
||||
and 16-bit devices and so must be either 1 or 2 bytes.
|
||||
- compatible: Compatible string property for the ethernet child device.
|
||||
- gpmc,cs-on: Chip-select assertion time
|
||||
- gpmc,cs-rd-off: Chip-select de-assertion time for reads
|
||||
- gpmc,cs-wr-off: Chip-select de-assertion time for writes
|
||||
- gpmc,oe-on: Output-enable assertion time
|
||||
- gpmc,oe-off Output-enable de-assertion time
|
||||
- gpmc,we-on: Write-enable assertion time
|
||||
- gpmc,we-off: Write-enable de-assertion time
|
||||
- gpmc,access: Start cycle to first data capture (read access)
|
||||
- gpmc,rd-cycle: Total read cycle time
|
||||
- gpmc,wr-cycle: Total write cycle time
|
||||
- reg: Chip-select, base address (relative to chip-select)
|
||||
and size of the memory mapped for the device.
|
||||
Note that base address will be typically 0 as this
|
||||
is the start of the chip-select.
|
||||
|
||||
Optional properties:
|
||||
- gpmc,XXX Additional GPMC timings and settings parameters. See
|
||||
Documentation/devicetree/bindings/bus/ti-gpmc.txt
|
||||
|
||||
Example:
|
||||
|
||||
gpmc: gpmc@6e000000 {
|
||||
compatible = "ti,omap3430-gpmc";
|
||||
ti,hwmods = "gpmc";
|
||||
reg = <0x6e000000 0x1000>;
|
||||
interrupts = <20>;
|
||||
gpmc,num-cs = <8>;
|
||||
gpmc,num-waitpins = <4>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
ranges = <5 0 0x2c000000 0x1000000>;
|
||||
|
||||
ethernet@5,0 {
|
||||
compatible = "smsc,lan9221", "smsc,lan9115";
|
||||
reg = <5 0 0xff>;
|
||||
bank-width = <2>;
|
||||
|
||||
gpmc,mux-add-data;
|
||||
gpmc,cs-on = <0>;
|
||||
gpmc,cs-rd-off = <186>;
|
||||
gpmc,cs-wr-off = <186>;
|
||||
gpmc,adv-on = <12>;
|
||||
gpmc,adv-rd-off = <48>;
|
||||
gpmc,adv-wr-off = <48>;
|
||||
gpmc,oe-on = <54>;
|
||||
gpmc,oe-off = <168>;
|
||||
gpmc,we-on = <54>;
|
||||
gpmc,we-off = <168>;
|
||||
gpmc,rd-cycle = <186>;
|
||||
gpmc,wr-cycle = <186>;
|
||||
gpmc,access = <114>;
|
||||
gpmc,page-burst-access = <6>;
|
||||
gpmc,bus-turnaround = <12>;
|
||||
gpmc,cycle2cycle-delay = <18>;
|
||||
gpmc,wr-data-mux-bus = <90>;
|
||||
gpmc,wr-access = <186>;
|
||||
gpmc,cycle2cycle-samecsen;
|
||||
gpmc,cycle2cycle-diffcsen;
|
||||
|
||||
interrupt-parent = <&gpio6>;
|
||||
interrupts = <16>;
|
||||
vmmc-supply = <&vddvario>;
|
||||
vmmc_aux-supply = <&vdd33a>;
|
||||
reg-io-width = <4>;
|
||||
|
||||
smsc,save-mac-address;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
VIA VT8500 and Wondermedia WM8xxx-series pinmux/gpio controller
|
||||
|
||||
These SoCs contain a combined Pinmux/GPIO module. Each pin may operate as
|
||||
either a GPIO in, GPIO out or as an alternate function (I2C, SPI etc).
|
||||
|
||||
Required properties:
|
||||
- compatible: "via,vt8500-pinctrl", "wm,wm8505-pinctrl", "wm,wm8650-pinctrl",
|
||||
"wm8750-pinctrl" or "wm,wm8850-pinctrl"
|
||||
- reg: Should contain the physical address of the module's registers.
|
||||
- interrupt-controller: Marks the device node as an interrupt controller.
|
||||
- #interrupt-cells: Should be two.
|
||||
- gpio-controller: Marks the device node as a GPIO controller.
|
||||
- #gpio-cells : Should be two. The first cell is the pin number and the
|
||||
second cell is used to specify optional parameters.
|
||||
bit 0 - active low
|
||||
|
||||
Please refer to ../gpio/gpio.txt for a general description of GPIO bindings.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
Each pin configuration node lists the pin(s) to which it applies, and one or
|
||||
more of the mux functions to select on those pin(s), and pull-up/down
|
||||
configuration. Each subnode only affects those parameters that are explicitly
|
||||
listed. In other words, a subnode that lists only a mux function implies no
|
||||
information about any pull configuration. Similarly, a subnode that lists only
|
||||
a pull parameter implies no information about the mux function.
|
||||
|
||||
Required subnode-properties:
|
||||
- wm,pins: An array of cells. Each cell contains the ID of a pin.
|
||||
|
||||
Optional subnode-properties:
|
||||
- wm,function: Integer, containing the function to mux to the pin(s):
|
||||
0: GPIO in
|
||||
1: GPIO out
|
||||
2: alternate
|
||||
|
||||
- wm,pull: Integer, representing the pull-down/up to apply to the pin(s):
|
||||
0: none
|
||||
1: down
|
||||
2: up
|
||||
|
||||
Each of wm,function and wm,pull may contain either a single value which
|
||||
will be applied to all pins in wm,pins, or one value for each entry in
|
||||
wm,pins.
|
||||
|
||||
Example:
|
||||
|
||||
pinctrl: pinctrl {
|
||||
compatible = "wm,wm8505-pinctrl";
|
||||
reg = <0xD8110000 0x10000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
ARM sp804 Dual Timers
|
||||
---------------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "arm,sp804" & "arm,primecell"
|
||||
- interrupts: Should contain the list of Dual Timer interrupts. This is the
|
||||
interrupt for timer 1 and timer 2. In the case of a single entry, it is
|
||||
the combined interrupt or if "arm,sp804-has-irq" is present that
|
||||
specifies which timer interrupt is connected.
|
||||
- reg: Should contain location and length for dual timer register.
|
||||
- clocks: clocks driving the dual timer hardware. This list should be 1 or 3
|
||||
clocks. With 3 clocks, the order is timer0 clock, timer1 clock,
|
||||
apb_pclk. A single clock can also be specified if the same clock is
|
||||
used for all clock inputs.
|
||||
|
||||
Optional properties:
|
||||
- arm,sp804-has-irq = <#>: In the case of only 1 timer irq line connected, this
|
||||
specifies if the irq connection is for timer 1 or timer 2. A value of 1
|
||||
or 2 should be used.
|
||||
|
||||
Example:
|
||||
|
||||
timer0: timer@fc800000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0xfc800000 0x1000>;
|
||||
interrupts = <0 0 4>, <0 1 4>;
|
||||
clocks = <&timclk1 &timclk2 &pclk>;
|
||||
clock-names = "timer1", "timer2", "apb_pclk";
|
||||
};
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
Cadence TTC - Triple Timer Counter
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "cdns,ttc".
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
- interrupts : A list of 3 interrupts; one per timer channel.
|
||||
- clocks: phandle to the source clock
|
||||
|
||||
Example:
|
||||
|
||||
ttc0: ttc0@f8001000 {
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = < 0 10 4 0 11 4 0 12 4 >;
|
||||
compatible = "cdns,ttc";
|
||||
reg = <0xF8001000 0x1000>;
|
||||
clocks = <&cpu_clk 3>;
|
||||
};
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
Samsung's Multi Core Timer (MCT)
|
||||
|
||||
The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
|
||||
global timer and CPU local timers. The global timer is a 64-bit free running
|
||||
up-counter and can generate 4 interrupts when the counter reaches one of the
|
||||
four preset counter values. The CPU local timers are 32-bit free running
|
||||
down-counters and generate an interrupt when the counter expires. There is
|
||||
one CPU local timer instantiated in MCT for every CPU in the system.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: should be "samsung,exynos4210-mct".
|
||||
(a) "samsung,exynos4210-mct", for mct compatible with Exynos4210 mct.
|
||||
(b) "samsung,exynos4412-mct", for mct compatible with Exynos4412 mct.
|
||||
|
||||
- reg: base address of the mct controller and length of the address space
|
||||
it occupies.
|
||||
|
||||
- interrupts: the list of interrupts generated by the controller. The following
|
||||
should be the order of the interrupts specified. The local timer interrupts
|
||||
should be specified after the four global timer interrupts have been
|
||||
specified.
|
||||
|
||||
0: Global Timer Interrupt 0
|
||||
1: Global Timer Interrupt 1
|
||||
2: Global Timer Interrupt 2
|
||||
3: Global Timer Interrupt 3
|
||||
4: Local Timer Interrupt 0
|
||||
5: Local Timer Interrupt 1
|
||||
6: ..
|
||||
7: ..
|
||||
i: Local Timer Interrupt n
|
||||
|
||||
Example 1: In this example, the system uses only the first global timer
|
||||
interrupt generated by MCT and the remaining three global timer
|
||||
interrupts are unused. Two local timer interrupts have been
|
||||
specified.
|
||||
|
||||
mct@10050000 {
|
||||
compatible = "samsung,exynos4210-mct";
|
||||
reg = <0x10050000 0x800>;
|
||||
interrupts = <0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>,
|
||||
<0 42 0>, <0 48 0>;
|
||||
};
|
||||
|
||||
Example 2: In this example, the MCT global and local timer interrupts are
|
||||
connected to two seperate interrupt controllers. Hence, an
|
||||
interrupt-map is created to map the interrupts to the respective
|
||||
interrupt controllers.
|
||||
|
||||
mct@101C0000 {
|
||||
compatible = "samsung,exynos4210-mct";
|
||||
reg = <0x101C0000 0x800>;
|
||||
interrupt-controller;
|
||||
#interrups-cells = <2>;
|
||||
interrupt-parent = <&mct_map>;
|
||||
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
|
||||
<4 0>, <5 0>;
|
||||
|
||||
mct_map: mct-map {
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <0x0 0 &combiner 23 3>,
|
||||
<0x4 0 &gic 0 120 0>,
|
||||
<0x5 0 &gic 0 121 0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -673,6 +673,7 @@ config ARCH_TEGRA
|
|||
select HAVE_CLK
|
||||
select HAVE_SMP
|
||||
select MIGHT_HAVE_CACHE_L2X0
|
||||
select SOC_BUS
|
||||
select SPARSE_IRQ
|
||||
select USE_OF
|
||||
help
|
||||
|
|
@ -769,12 +770,15 @@ config ARCH_SA1100
|
|||
config ARCH_S3C24XX
|
||||
bool "Samsung S3C24XX SoCs"
|
||||
select ARCH_HAS_CPUFREQ
|
||||
select ARCH_USES_GETTIMEOFFSET
|
||||
select CLKDEV_LOOKUP
|
||||
select CLKSRC_MMIO
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select GENERIC_GPIO
|
||||
select HAVE_CLK
|
||||
select HAVE_S3C2410_I2C if I2C
|
||||
select HAVE_S3C2410_WATCHDOG if WATCHDOG
|
||||
select HAVE_S3C_RTC if RTC_CLASS
|
||||
select MULTI_IRQ_HANDLER
|
||||
select NEED_MACH_GPIO_H
|
||||
select NEED_MACH_IO_H
|
||||
help
|
||||
|
|
@ -787,10 +791,11 @@ config ARCH_S3C64XX
|
|||
bool "Samsung S3C64XX"
|
||||
select ARCH_HAS_CPUFREQ
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARCH_USES_GETTIMEOFFSET
|
||||
select ARM_VIC
|
||||
select CLKDEV_LOOKUP
|
||||
select CLKSRC_MMIO
|
||||
select CPU_V6
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_CLK
|
||||
select HAVE_S3C2410_I2C if I2C
|
||||
select HAVE_S3C2410_WATCHDOG if WATCHDOG
|
||||
|
|
@ -824,9 +829,11 @@ config ARCH_S5P64X0
|
|||
|
||||
config ARCH_S5PC100
|
||||
bool "Samsung S5PC100"
|
||||
select ARCH_USES_GETTIMEOFFSET
|
||||
select CLKDEV_LOOKUP
|
||||
select CLKSRC_MMIO
|
||||
select CPU_V7
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select GENERIC_GPIO
|
||||
select HAVE_CLK
|
||||
select HAVE_S3C2410_I2C if I2C
|
||||
select HAVE_S3C2410_WATCHDOG if WATCHDOG
|
||||
|
|
@ -1165,6 +1172,7 @@ config PLAT_VERSATILE
|
|||
config ARM_TIMER_SP804
|
||||
bool
|
||||
select CLKSRC_MMIO
|
||||
select CLKSRC_OF if OF
|
||||
select HAVE_SCHED_CLOCK
|
||||
|
||||
source arch/arm/mm/Kconfig
|
||||
|
|
@ -1595,6 +1603,7 @@ config HAVE_ARM_ARCH_TIMER
|
|||
config HAVE_ARM_TWD
|
||||
bool
|
||||
depends on SMP
|
||||
select CLKSRC_OF if OF
|
||||
help
|
||||
This options enables support for the ARM timer and watchdog unit
|
||||
|
||||
|
|
@ -1648,7 +1657,7 @@ config LOCAL_TIMERS
|
|||
bool "Use local timer interrupts"
|
||||
depends on SMP
|
||||
default y
|
||||
select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
|
||||
select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !CLKSRC_EXYNOS_MCT)
|
||||
help
|
||||
Enable support for local timers on SMP platforms, rather then the
|
||||
legacy IPI broadcast method. Local timers allows the system
|
||||
|
|
@ -1663,7 +1672,8 @@ config ARCH_NR_GPIO
|
|||
default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
|
||||
default 512 if SOC_OMAP5
|
||||
default 355 if ARCH_U8500
|
||||
default 288 if ARCH_VT8500 || ARCH_SUNXI
|
||||
default 352 if ARCH_VT8500
|
||||
default 288 if ARCH_SUNXI
|
||||
default 264 if MACH_H4700
|
||||
default 0
|
||||
help
|
||||
|
|
|
|||
|
|
@ -170,6 +170,8 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
|
|||
tegra30-cardhu-a04.dtb \
|
||||
tegra114-dalmore.dtb \
|
||||
tegra114-pluto.dtb
|
||||
dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \
|
||||
versatile-pb.dtb
|
||||
dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
|
||||
vexpress-v2p-ca9.dtb \
|
||||
vexpress-v2p-ca15-tc1.dtb \
|
||||
|
|
|
|||
|
|
@ -47,6 +47,28 @@
|
|||
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
|
||||
};
|
||||
|
||||
mct@10050000 {
|
||||
compatible = "samsung,exynos4210-mct";
|
||||
reg = <0x10050000 0x800>;
|
||||
interrupt-controller;
|
||||
#interrups-cells = <2>;
|
||||
interrupt-parent = <&mct_map>;
|
||||
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
|
||||
<4 0>, <5 0>;
|
||||
|
||||
mct_map: mct-map {
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <0x0 0 &gic 0 57 0>,
|
||||
<0x1 0 &gic 0 69 0>,
|
||||
<0x2 0 &combiner 12 6>,
|
||||
<0x3 0 &combiner 12 7>,
|
||||
<0x4 0 &gic 0 42 0>,
|
||||
<0x5 0 &gic 0 48 0>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_0: pinctrl@11400000 {
|
||||
compatible = "samsung,exynos4210-pinctrl";
|
||||
reg = <0x11400000 0x1000>;
|
||||
|
|
|
|||
|
|
@ -25,4 +25,26 @@
|
|||
gic:interrupt-controller@10490000 {
|
||||
cpu-offset = <0x8000>;
|
||||
};
|
||||
|
||||
mct@10050000 {
|
||||
compatible = "samsung,exynos4412-mct";
|
||||
reg = <0x10050000 0x800>;
|
||||
interrupt-controller;
|
||||
#interrups-cells = <2>;
|
||||
interrupt-parent = <&mct_map>;
|
||||
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
|
||||
<4 0>, <5 0>;
|
||||
|
||||
mct_map: mct-map {
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <0x0 0 &gic 0 57 0>,
|
||||
<0x1 0 &combiner 12 5>,
|
||||
<0x2 0 &combiner 12 6>,
|
||||
<0x3 0 &combiner 12 7>,
|
||||
<0x4 0 &gic 1 12 0>,
|
||||
<0x5 0 &gic 1 12 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -25,4 +25,28 @@
|
|||
gic:interrupt-controller@10490000 {
|
||||
cpu-offset = <0x4000>;
|
||||
};
|
||||
|
||||
mct@10050000 {
|
||||
compatible = "samsung,exynos4412-mct";
|
||||
reg = <0x10050000 0x800>;
|
||||
interrupt-controller;
|
||||
#interrups-cells = <2>;
|
||||
interrupt-parent = <&mct_map>;
|
||||
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
|
||||
<4 0>, <5 0>, <6 0>, <7 0>;
|
||||
|
||||
mct_map: mct-map {
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <0x0 0 &gic 0 57 0>,
|
||||
<0x1 0 &combiner 12 5>,
|
||||
<0x2 0 &combiner 12 6>,
|
||||
<0x3 0 &combiner 12 7>,
|
||||
<0x4 0 &gic 1 12 0>,
|
||||
<0x5 0 &gic 1 12 0>,
|
||||
<0x6 0 &gic 1 12 0>,
|
||||
<0x7 0 &gic 1 12 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -69,6 +69,28 @@
|
|||
<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
|
||||
};
|
||||
|
||||
mct@101C0000 {
|
||||
compatible = "samsung,exynos4210-mct";
|
||||
reg = <0x101C0000 0x800>;
|
||||
interrupt-controller;
|
||||
#interrups-cells = <2>;
|
||||
interrupt-parent = <&mct_map>;
|
||||
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
|
||||
<4 0>, <5 0>;
|
||||
|
||||
mct_map: mct-map {
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <0x0 0 &combiner 23 3>,
|
||||
<0x1 0 &combiner 23 4>,
|
||||
<0x2 0 &combiner 25 2>,
|
||||
<0x3 0 &combiner 25 3>,
|
||||
<0x4 0 &gic 0 120 0>,
|
||||
<0x5 0 &gic 0 121 0>;
|
||||
};
|
||||
};
|
||||
|
||||
watchdog {
|
||||
compatible = "samsung,s3c2410-wdt";
|
||||
reg = <0x101D0000 0x100>;
|
||||
|
|
|
|||
|
|
@ -24,15 +24,15 @@
|
|||
};
|
||||
|
||||
timer0: timer@13000000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
compatible = "arm,integrator-cp-timer";
|
||||
};
|
||||
|
||||
timer1: timer@13000100 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
compatible = "arm,integrator-cp-timer";
|
||||
};
|
||||
|
||||
timer2: timer@13000200 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
compatible = "arm,integrator-cp-timer";
|
||||
};
|
||||
|
||||
pic: pic@14000000 {
|
||||
|
|
|
|||
|
|
@ -38,6 +38,57 @@
|
|||
};
|
||||
};
|
||||
|
||||
/* HS USB Port 2 RESET */
|
||||
hsusb2_reset: hsusb2_reset_reg {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "hsusb2_reset";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio5 19 0>; /* gpio_147 */
|
||||
startup-delay-us = <70000>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
/* HS USB Port 2 Power */
|
||||
hsusb2_power: hsusb2_power_reg {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "hsusb2_vbus";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&twl_gpio 18 0>; /* GPIO LEDA */
|
||||
startup-delay-us = <70000>;
|
||||
};
|
||||
|
||||
/* HS USB Host PHY on PORT 2 */
|
||||
hsusb2_phy: hsusb2_phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
reset-supply = <&hsusb2_reset>;
|
||||
vcc-supply = <&hsusb2_power>;
|
||||
};
|
||||
};
|
||||
|
||||
&omap3_pmx_core {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <
|
||||
&hsusbb2_pins
|
||||
>;
|
||||
|
||||
hsusbb2_pins: pinmux_hsusbb2_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x5c0 0x3 /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk OUTPUT */
|
||||
0x5c2 0x3 /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_stp OUTPUT */
|
||||
0x5c4 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dir INPUT | PULLDOWN */
|
||||
0x5c6 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_nxt INPUT | PULLDOWN */
|
||||
0x5c8 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat0 INPUT | PULLDOWN */
|
||||
0x5cA 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat1 INPUT | PULLDOWN */
|
||||
0x1a4 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat2 INPUT | PULLDOWN */
|
||||
0x1a6 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat3 INPUT | PULLDOWN */
|
||||
0x1a8 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat4 INPUT | PULLDOWN */
|
||||
0x1aa 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat5 INPUT | PULLDOWN */
|
||||
0x1ac 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat6 INPUT | PULLDOWN */
|
||||
0x1ae 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 INPUT | PULLDOWN */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
|
|
@ -65,3 +116,23 @@
|
|||
&mmc3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usbhshost {
|
||||
port2-mode = "ehci-phy";
|
||||
};
|
||||
|
||||
&usbhsehci {
|
||||
phys = <0 &hsusb2_phy>;
|
||||
};
|
||||
|
||||
&twl_gpio {
|
||||
ti,use-leds;
|
||||
/* pullups: BIT(1) */
|
||||
ti,pullups = <0x000002>;
|
||||
/*
|
||||
* pulldowns:
|
||||
* BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
|
||||
* BIT(15), BIT(16), BIT(17)
|
||||
*/
|
||||
ti,pulldowns = <0x03a1c4>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -397,5 +397,36 @@
|
|||
ti,timer-alwon;
|
||||
ti,timer-secure;
|
||||
};
|
||||
|
||||
usbhstll: usbhstll@48062000 {
|
||||
compatible = "ti,usbhs-tll";
|
||||
reg = <0x48062000 0x1000>;
|
||||
interrupts = <78>;
|
||||
ti,hwmods = "usb_tll_hs";
|
||||
};
|
||||
|
||||
usbhshost: usbhshost@48064000 {
|
||||
compatible = "ti,usbhs-host";
|
||||
reg = <0x48064000 0x400>;
|
||||
ti,hwmods = "usb_host_hs";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
usbhsohci: ohci@48064400 {
|
||||
compatible = "ti,ohci-omap3", "usb-ohci";
|
||||
reg = <0x48064400 0x400>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <76>;
|
||||
};
|
||||
|
||||
usbhsehci: ehci@48064800 {
|
||||
compatible = "ti,ehci-omap", "usb-ehci";
|
||||
reg = <0x48064800 0x400>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <77>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -529,5 +529,35 @@
|
|||
ti,hwmods = "timer11";
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
usbhstll: usbhstll@4a062000 {
|
||||
compatible = "ti,usbhs-tll";
|
||||
reg = <0x4a062000 0x1000>;
|
||||
interrupts = <0 78 0x4>;
|
||||
ti,hwmods = "usb_tll_hs";
|
||||
};
|
||||
|
||||
usbhshost: usbhshost@4a064000 {
|
||||
compatible = "ti,usbhs-host";
|
||||
reg = <0x4a064000 0x800>;
|
||||
ti,hwmods = "usb_host_hs";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
usbhsohci: ohci@4a064800 {
|
||||
compatible = "ti,ohci-omap3", "usb-ohci";
|
||||
reg = <0x4a064800 0x400>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 76 0x4>;
|
||||
};
|
||||
|
||||
usbhsehci: ehci@4a064c00 {
|
||||
compatible = "ti,ehci-omap", "usb-ehci";
|
||||
reg = <0x4a064c00 0x400>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 77 0x4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,98 @@
|
|||
/*
|
||||
* Device Tree Source for Renesas r8a7779
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
* Copyright (C) 2013 Simon Horman
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a7779";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
};
|
||||
cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <2>;
|
||||
};
|
||||
cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f0001000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0xf0001000 0x1000>,
|
||||
<0xf0000100 0x100>;
|
||||
};
|
||||
|
||||
i2c0: i2c@0xffc70000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,rmobile-iic";
|
||||
reg = <0xffc70000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 79 0x4>;
|
||||
};
|
||||
|
||||
i2c1: i2c@0xffc71000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,rmobile-iic";
|
||||
reg = <0xffc71000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 82 0x4>;
|
||||
};
|
||||
|
||||
i2c2: i2c@0xffc72000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,rmobile-iic";
|
||||
reg = <0xffc72000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 80 0x4>;
|
||||
};
|
||||
|
||||
i2c3: i2c@0xffc73000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,rmobile-iic";
|
||||
reg = <0xffc73000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 81 0x4>;
|
||||
};
|
||||
|
||||
thermal@ffc48000 {
|
||||
compatible = "renesas,rcar-thermal";
|
||||
reg = <0xffc48000 0x38>;
|
||||
};
|
||||
|
||||
sata: sata@fc600000 {
|
||||
compatible = "renesas,rcar-sata";
|
||||
reg = <0xfc600000 0x2000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 100 0x4>;
|
||||
};
|
||||
};
|
||||
|
|
@ -12,10 +12,22 @@
|
|||
|
||||
serial@70006300 {
|
||||
status = "okay";
|
||||
clock-frequency = <408000000>;
|
||||
};
|
||||
|
||||
pmc {
|
||||
nvidia,invert-interrupt;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -12,10 +12,22 @@
|
|||
|
||||
serial@70006300 {
|
||||
status = "okay";
|
||||
clock-frequency = <408000000>;
|
||||
};
|
||||
|
||||
pmc {
|
||||
nvidia,invert-interrupt;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -24,10 +24,11 @@
|
|||
0 42 0x04
|
||||
0 121 0x04
|
||||
0 122 0x04>;
|
||||
clocks = <&tegra_car 5>;
|
||||
};
|
||||
|
||||
tegra_car: clock {
|
||||
compatible = "nvidia,tegra114-car, nvidia,tegra30-car";
|
||||
compatible = "nvidia,tegra114-car";
|
||||
reg = <0x60006000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -66,6 +67,7 @@
|
|||
reg-shift = <2>;
|
||||
interrupts = <0 36 0x04>;
|
||||
status = "disabled";
|
||||
clocks = <&tegra_car 6>;
|
||||
};
|
||||
|
||||
serial@70006040 {
|
||||
|
|
@ -74,6 +76,7 @@
|
|||
reg-shift = <2>;
|
||||
interrupts = <0 37 0x04>;
|
||||
status = "disabled";
|
||||
clocks = <&tegra_car 192>;
|
||||
};
|
||||
|
||||
serial@70006200 {
|
||||
|
|
@ -82,6 +85,7 @@
|
|||
reg-shift = <2>;
|
||||
interrupts = <0 46 0x04>;
|
||||
status = "disabled";
|
||||
clocks = <&tegra_car 55>;
|
||||
};
|
||||
|
||||
serial@70006300 {
|
||||
|
|
@ -90,17 +94,21 @@
|
|||
reg-shift = <2>;
|
||||
interrupts = <0 90 0x04>;
|
||||
status = "disabled";
|
||||
clocks = <&tegra_car 65>;
|
||||
};
|
||||
|
||||
rtc {
|
||||
compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
|
||||
reg = <0x7000e000 0x100>;
|
||||
interrupts = <0 2 0x04>;
|
||||
clocks = <&tegra_car 4>;
|
||||
};
|
||||
|
||||
pmc {
|
||||
compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc";
|
||||
compatible = "nvidia,tegra114-pmc";
|
||||
reg = <0x7000e400 0x400>;
|
||||
clocks = <&tegra_car 261>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
};
|
||||
|
||||
iommu {
|
||||
|
|
|
|||
|
|
@ -444,7 +444,20 @@
|
|||
};
|
||||
|
||||
sdhci@c8000600 {
|
||||
cd-gpios = <&gpio 23 0>; /* gpio PC7 */
|
||||
cd-gpios = <&gpio 23 1>; /* gpio PC7 */
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
|
|
|
|||
|
|
@ -437,7 +437,7 @@
|
|||
|
||||
sdhci@c8000200 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
|
||||
power-gpios = <&gpio 155 0>; /* gpio PT3 */
|
||||
bus-width = <4>;
|
||||
|
|
@ -445,12 +445,25 @@
|
|||
|
||||
sdhci@c8000600 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 58 0>; /* gpio PH2 */
|
||||
cd-gpios = <&gpio 58 1>; /* gpio PH2 */
|
||||
wp-gpios = <&gpio 59 0>; /* gpio PH3 */
|
||||
power-gpios = <&gpio 70 0>; /* gpio PI6 */
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
kbc {
|
||||
status = "okay";
|
||||
nvidia,debounce-delay-ms = <2>;
|
||||
|
|
|
|||
|
|
@ -436,7 +436,7 @@
|
|||
|
||||
sdhci@c8000000 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 173 0>; /* gpio PV5 */
|
||||
cd-gpios = <&gpio 173 1>; /* gpio PV5 */
|
||||
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
|
||||
power-gpios = <&gpio 169 0>; /* gpio PV1 */
|
||||
bus-width = <4>;
|
||||
|
|
@ -447,6 +447,19 @@
|
|||
bus-width = <8>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
|
|
|
|||
|
|
@ -584,7 +584,7 @@
|
|||
|
||||
sdhci@c8000400 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
|
||||
power-gpios = <&gpio 70 0>; /* gpio PI6 */
|
||||
bus-width = <4>;
|
||||
|
|
@ -595,6 +595,19 @@
|
|||
bus-width = <8>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
|
|
|
|||
|
|
@ -465,12 +465,25 @@
|
|||
};
|
||||
|
||||
sdhci@c8000600 {
|
||||
cd-gpios = <&gpio 58 0>; /* gpio PH2 */
|
||||
cd-gpios = <&gpio 58 1>; /* gpio PH2 */
|
||||
wp-gpios = <&gpio 59 0>; /* gpio PH3 */
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
|
||||
|
|
|
|||
|
|
@ -325,11 +325,24 @@
|
|||
|
||||
sdhci@c8000600 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 121 0>; /* gpio PP1 */
|
||||
cd-gpios = <&gpio 121 1>; /* gpio PP1 */
|
||||
wp-gpios = <&gpio 122 0>; /* gpio PP2 */
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
poweroff {
|
||||
compatible = "gpio-poweroff";
|
||||
gpios = <&gpio 191 1>; /* gpio PX7, active low */
|
||||
|
|
|
|||
|
|
@ -520,7 +520,7 @@
|
|||
|
||||
sdhci@c8000400 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
|
||||
power-gpios = <&gpio 70 0>; /* gpio PI6 */
|
||||
bus-width = <4>;
|
||||
|
|
@ -531,6 +531,19 @@
|
|||
bus-width = <8>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -510,6 +510,7 @@
|
|||
|
||||
sdhci@c8000400 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 173 0>; /* gpio PV5 */
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
|
@ -519,6 +520,19 @@
|
|||
bus-width = <8>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
kbc {
|
||||
status = "okay";
|
||||
nvidia,debounce-delay-ms = <20>;
|
||||
|
|
|
|||
|
|
@ -145,6 +145,7 @@
|
|||
0 1 0x04
|
||||
0 41 0x04
|
||||
0 42 0x04>;
|
||||
clocks = <&tegra_car 5>;
|
||||
};
|
||||
|
||||
tegra_car: clock {
|
||||
|
|
@ -304,6 +305,7 @@
|
|||
compatible = "nvidia,tegra20-rtc";
|
||||
reg = <0x7000e000 0x100>;
|
||||
interrupts = <0 2 0x04>;
|
||||
clocks = <&tegra_car 4>;
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
|
|
@ -416,6 +418,8 @@
|
|||
pmc {
|
||||
compatible = "nvidia,tegra20-pmc";
|
||||
reg = <0x7000e400 0x400>;
|
||||
clocks = <&tegra_car 110>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
};
|
||||
|
||||
memory-controller@7000f000 {
|
||||
|
|
|
|||
|
|
@ -257,7 +257,7 @@
|
|||
|
||||
sdhci@78000000 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 155 0>; /* gpio PT3 */
|
||||
power-gpios = <&gpio 31 0>; /* gpio PD7 */
|
||||
bus-width = <4>;
|
||||
|
|
@ -268,6 +268,19 @@
|
|||
bus-width = <8>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -311,7 +311,7 @@
|
|||
|
||||
sdhci@78000000 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 155 0>; /* gpio PT3 */
|
||||
power-gpios = <&gpio 31 0>; /* gpio PD7 */
|
||||
bus-width = <4>;
|
||||
|
|
@ -322,6 +322,19 @@
|
|||
bus-width = <8>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -148,6 +148,7 @@
|
|||
0 42 0x04
|
||||
0 121 0x04
|
||||
0 122 0x04>;
|
||||
clocks = <&tegra_car 5>;
|
||||
};
|
||||
|
||||
tegra_car: clock {
|
||||
|
|
@ -291,6 +292,7 @@
|
|||
compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
|
||||
reg = <0x7000e000 0x100>;
|
||||
interrupts = <0 2 0x04>;
|
||||
clocks = <&tegra_car 4>;
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
|
|
@ -423,8 +425,10 @@
|
|||
};
|
||||
|
||||
pmc {
|
||||
compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
|
||||
compatible = "nvidia,tegra30-pmc";
|
||||
reg = <0x7000e400 0x400>;
|
||||
clocks = <&tegra_car 218>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
};
|
||||
|
||||
memory-controller {
|
||||
|
|
|
|||
|
|
@ -121,6 +121,18 @@
|
|||
interrupts = <0>;
|
||||
};
|
||||
|
||||
timer@101e2000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x101e2000 0x1000>;
|
||||
interrupts = <4>;
|
||||
};
|
||||
|
||||
timer@101e3000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x101e3000 0x1000>;
|
||||
interrupts = <5>;
|
||||
};
|
||||
|
||||
gpio0: gpio@101e4000 {
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
reg = <0x101e4000 0x1000>;
|
||||
|
|
|
|||
|
|
@ -98,6 +98,7 @@
|
|||
<0 49 4>;
|
||||
clocks = <&oscclk2>, <&oscclk2>;
|
||||
clock-names = "timclk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog@100e5000 {
|
||||
|
|
|
|||
|
|
@ -25,11 +25,13 @@
|
|||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio: gpio-controller@d8110000 {
|
||||
compatible = "via,vt8500-gpio";
|
||||
gpio-controller;
|
||||
pinctrl: pinctrl@d8110000 {
|
||||
compatible = "via,vt8500-pinctrl";
|
||||
reg = <0xd8110000 0x10000>;
|
||||
#gpio-cells = <3>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
pmc@d8130000 {
|
||||
|
|
|
|||
|
|
@ -40,11 +40,13 @@
|
|||
interrupts = <56 57 58 59 60 61 62 63>;
|
||||
};
|
||||
|
||||
gpio: gpio-controller@d8110000 {
|
||||
compatible = "wm,wm8505-gpio";
|
||||
gpio-controller;
|
||||
pinctrl: pinctrl@d8110000 {
|
||||
compatible = "wm,wm8505-pinctrl";
|
||||
reg = <0xd8110000 0x10000>;
|
||||
#gpio-cells = <3>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
pmc@d8130000 {
|
||||
|
|
|
|||
|
|
@ -34,11 +34,13 @@
|
|||
interrupts = <56 57 58 59 60 61 62 63>;
|
||||
};
|
||||
|
||||
gpio: gpio-controller@d8110000 {
|
||||
compatible = "wm,wm8650-gpio";
|
||||
gpio-controller;
|
||||
pinctrl: pinctrl@d8110000 {
|
||||
compatible = "wm,wm8650-pinctrl";
|
||||
reg = <0xd8110000 0x10000>;
|
||||
#gpio-cells = <3>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
pmc@d8130000 {
|
||||
|
|
|
|||
|
|
@ -41,11 +41,13 @@
|
|||
interrupts = <56 57 58 59 60 61 62 63>;
|
||||
};
|
||||
|
||||
gpio: gpio-controller@d8110000 {
|
||||
compatible = "wm,wm8650-gpio";
|
||||
gpio-controller;
|
||||
pinctrl: pinctrl@d8110000 {
|
||||
compatible = "wm,wm8850-pinctrl";
|
||||
reg = <0xd8110000 0x10000>;
|
||||
#gpio-cells = <3>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
pmc@d8130000 {
|
||||
|
|
|
|||
|
|
@ -111,56 +111,23 @@
|
|||
};
|
||||
|
||||
ttc0: ttc0@f8001000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "xlnx,ttc";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = < 0 10 4 0 11 4 0 12 4 >;
|
||||
compatible = "cdns,ttc";
|
||||
reg = <0xF8001000 0x1000>;
|
||||
clocks = <&cpu_clk 3>;
|
||||
clock-names = "cpu_1x";
|
||||
clock-ranges;
|
||||
|
||||
ttc0_0: ttc0.0 {
|
||||
status = "disabled";
|
||||
reg = <0>;
|
||||
interrupts = <0 10 4>;
|
||||
};
|
||||
ttc0_1: ttc0.1 {
|
||||
status = "disabled";
|
||||
reg = <1>;
|
||||
interrupts = <0 11 4>;
|
||||
};
|
||||
ttc0_2: ttc0.2 {
|
||||
status = "disabled";
|
||||
reg = <2>;
|
||||
interrupts = <0 12 4>;
|
||||
};
|
||||
};
|
||||
|
||||
ttc1: ttc1@f8002000 {
|
||||
#interrupt-parent = <&intc>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "xlnx,ttc";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = < 0 37 4 0 38 4 0 39 4 >;
|
||||
compatible = "cdns,ttc";
|
||||
reg = <0xF8002000 0x1000>;
|
||||
clocks = <&cpu_clk 3>;
|
||||
clock-names = "cpu_1x";
|
||||
clock-ranges;
|
||||
|
||||
ttc1_0: ttc1.0 {
|
||||
status = "disabled";
|
||||
reg = <0>;
|
||||
interrupts = <0 37 4>;
|
||||
};
|
||||
ttc1_1: ttc1.1 {
|
||||
status = "disabled";
|
||||
reg = <1>;
|
||||
interrupts = <0 38 4>;
|
||||
};
|
||||
ttc1_2: ttc1.2 {
|
||||
status = "disabled";
|
||||
reg = <2>;
|
||||
interrupts = <0 39 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -32,13 +32,3 @@
|
|||
&ps_clk {
|
||||
clock-frequency = <33333330>;
|
||||
};
|
||||
|
||||
&ttc0_0 {
|
||||
status = "ok";
|
||||
compatible = "xlnx,ttc-counter-clocksource";
|
||||
};
|
||||
|
||||
&ttc0_1 {
|
||||
status = "ok";
|
||||
compatible = "xlnx,ttc-counter-clockevent";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -25,33 +25,29 @@
|
|||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
|
||||
#include <asm/sched_clock.h>
|
||||
#include <asm/hardware/arm_timer.h>
|
||||
#include <asm/hardware/timer-sp.h>
|
||||
|
||||
static long __init sp804_get_clock_rate(const char *name)
|
||||
static long __init sp804_get_clock_rate(struct clk *clk)
|
||||
{
|
||||
struct clk *clk;
|
||||
long rate;
|
||||
int err;
|
||||
|
||||
clk = clk_get_sys("sp804", name);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("sp804: %s clock not found: %d\n", name,
|
||||
(int)PTR_ERR(clk));
|
||||
return PTR_ERR(clk);
|
||||
}
|
||||
|
||||
err = clk_prepare(clk);
|
||||
if (err) {
|
||||
pr_err("sp804: %s clock failed to prepare: %d\n", name, err);
|
||||
pr_err("sp804: clock failed to prepare: %d\n", err);
|
||||
clk_put(clk);
|
||||
return err;
|
||||
}
|
||||
|
||||
err = clk_enable(clk);
|
||||
if (err) {
|
||||
pr_err("sp804: %s clock failed to enable: %d\n", name, err);
|
||||
pr_err("sp804: clock failed to enable: %d\n", err);
|
||||
clk_unprepare(clk);
|
||||
clk_put(clk);
|
||||
return err;
|
||||
|
|
@ -59,7 +55,7 @@ static long __init sp804_get_clock_rate(const char *name)
|
|||
|
||||
rate = clk_get_rate(clk);
|
||||
if (rate < 0) {
|
||||
pr_err("sp804: %s clock failed to get rate: %ld\n", name, rate);
|
||||
pr_err("sp804: clock failed to get rate: %ld\n", rate);
|
||||
clk_disable(clk);
|
||||
clk_unprepare(clk);
|
||||
clk_put(clk);
|
||||
|
|
@ -77,9 +73,21 @@ static u32 sp804_read(void)
|
|||
|
||||
void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,
|
||||
const char *name,
|
||||
struct clk *clk,
|
||||
int use_sched_clock)
|
||||
{
|
||||
long rate = sp804_get_clock_rate(name);
|
||||
long rate;
|
||||
|
||||
if (!clk) {
|
||||
clk = clk_get_sys("sp804", name);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("sp804: clock not found: %d\n",
|
||||
(int)PTR_ERR(clk));
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
rate = sp804_get_clock_rate(clk);
|
||||
|
||||
if (rate < 0)
|
||||
return;
|
||||
|
|
@ -171,12 +179,20 @@ static struct irqaction sp804_timer_irq = {
|
|||
.dev_id = &sp804_clockevent,
|
||||
};
|
||||
|
||||
void __init sp804_clockevents_init(void __iomem *base, unsigned int irq,
|
||||
const char *name)
|
||||
void __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct clk *clk, const char *name)
|
||||
{
|
||||
struct clock_event_device *evt = &sp804_clockevent;
|
||||
long rate = sp804_get_clock_rate(name);
|
||||
long rate;
|
||||
|
||||
if (!clk)
|
||||
clk = clk_get_sys("sp804", name);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("sp804: %s clock not found: %d\n", name,
|
||||
(int)PTR_ERR(clk));
|
||||
return;
|
||||
}
|
||||
|
||||
rate = sp804_get_clock_rate(clk);
|
||||
if (rate < 0)
|
||||
return;
|
||||
|
||||
|
|
@ -186,6 +202,98 @@ void __init sp804_clockevents_init(void __iomem *base, unsigned int irq,
|
|||
evt->irq = irq;
|
||||
evt->cpumask = cpu_possible_mask;
|
||||
|
||||
writel(0, base + TIMER_CTRL);
|
||||
|
||||
setup_irq(irq, &sp804_timer_irq);
|
||||
clockevents_config_and_register(evt, rate, 0xf, 0xffffffff);
|
||||
}
|
||||
|
||||
static void __init sp804_of_init(struct device_node *np)
|
||||
{
|
||||
static bool initialized = false;
|
||||
void __iomem *base;
|
||||
int irq;
|
||||
u32 irq_num = 0;
|
||||
struct clk *clk1, *clk2;
|
||||
const char *name = of_get_property(np, "compatible", NULL);
|
||||
|
||||
base = of_iomap(np, 0);
|
||||
if (WARN_ON(!base))
|
||||
return;
|
||||
|
||||
/* Ensure timers are disabled */
|
||||
writel(0, base + TIMER_CTRL);
|
||||
writel(0, base + TIMER_2_BASE + TIMER_CTRL);
|
||||
|
||||
if (initialized || !of_device_is_available(np))
|
||||
goto err;
|
||||
|
||||
clk1 = of_clk_get(np, 0);
|
||||
if (IS_ERR(clk1))
|
||||
clk1 = NULL;
|
||||
|
||||
/* Get the 2nd clock if the timer has 2 timer clocks */
|
||||
if (of_count_phandle_with_args(np, "clocks", "#clock-cells") == 3) {
|
||||
clk2 = of_clk_get(np, 1);
|
||||
if (IS_ERR(clk2)) {
|
||||
pr_err("sp804: %s clock not found: %d\n", np->name,
|
||||
(int)PTR_ERR(clk2));
|
||||
goto err;
|
||||
}
|
||||
} else
|
||||
clk2 = clk1;
|
||||
|
||||
irq = irq_of_parse_and_map(np, 0);
|
||||
if (irq <= 0)
|
||||
goto err;
|
||||
|
||||
of_property_read_u32(np, "arm,sp804-has-irq", &irq_num);
|
||||
if (irq_num == 2) {
|
||||
__sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name);
|
||||
__sp804_clocksource_and_sched_clock_init(base, name, clk1, 1);
|
||||
} else {
|
||||
__sp804_clockevents_init(base, irq, clk1 , name);
|
||||
__sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE,
|
||||
name, clk2, 1);
|
||||
}
|
||||
initialized = true;
|
||||
|
||||
return;
|
||||
err:
|
||||
iounmap(base);
|
||||
}
|
||||
CLOCKSOURCE_OF_DECLARE(sp804, "arm,sp804", sp804_of_init);
|
||||
|
||||
static void __init integrator_cp_of_init(struct device_node *np)
|
||||
{
|
||||
static int init_count = 0;
|
||||
void __iomem *base;
|
||||
int irq;
|
||||
const char *name = of_get_property(np, "compatible", NULL);
|
||||
|
||||
base = of_iomap(np, 0);
|
||||
if (WARN_ON(!base))
|
||||
return;
|
||||
|
||||
/* Ensure timer is disabled */
|
||||
writel(0, base + TIMER_CTRL);
|
||||
|
||||
if (init_count == 2 || !of_device_is_available(np))
|
||||
goto err;
|
||||
|
||||
if (!init_count)
|
||||
sp804_clocksource_init(base, name);
|
||||
else {
|
||||
irq = irq_of_parse_and_map(np, 0);
|
||||
if (irq <= 0)
|
||||
goto err;
|
||||
|
||||
sp804_clockevents_init(base, irq, name);
|
||||
}
|
||||
|
||||
init_count++;
|
||||
return;
|
||||
err:
|
||||
iounmap(base);
|
||||
}
|
||||
CLOCKSOURCE_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init);
|
||||
|
|
|
|||
|
|
@ -10,8 +10,7 @@
|
|||
#include <clocksource/arm_arch_timer.h>
|
||||
|
||||
#ifdef CONFIG_ARM_ARCH_TIMER
|
||||
int arch_timer_of_register(void);
|
||||
int arch_timer_sched_clock_init(void);
|
||||
int arch_timer_arch_init(void);
|
||||
|
||||
/*
|
||||
* These register accessors are marked inline so the compiler can
|
||||
|
|
@ -110,16 +109,6 @@ static inline void __cpuinit arch_counter_set_user_access(void)
|
|||
|
||||
asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl));
|
||||
}
|
||||
#else
|
||||
static inline int arch_timer_of_register(void)
|
||||
{
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
static inline int arch_timer_sched_clock_init(void)
|
||||
{
|
||||
return -ENXIO;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,15 +1,23 @@
|
|||
struct clk;
|
||||
|
||||
void __sp804_clocksource_and_sched_clock_init(void __iomem *,
|
||||
const char *, int);
|
||||
const char *, struct clk *, int);
|
||||
void __sp804_clockevents_init(void __iomem *, unsigned int,
|
||||
struct clk *, const char *);
|
||||
|
||||
static inline void sp804_clocksource_init(void __iomem *base, const char *name)
|
||||
{
|
||||
__sp804_clocksource_and_sched_clock_init(base, name, 0);
|
||||
__sp804_clocksource_and_sched_clock_init(base, name, NULL, 0);
|
||||
}
|
||||
|
||||
static inline void sp804_clocksource_and_sched_clock_init(void __iomem *base,
|
||||
const char *name)
|
||||
{
|
||||
__sp804_clocksource_and_sched_clock_init(base, name, 1);
|
||||
__sp804_clocksource_and_sched_clock_init(base, name, NULL, 1);
|
||||
}
|
||||
|
||||
void sp804_clockevents_init(void __iomem *, unsigned int, const char *);
|
||||
static inline void sp804_clockevents_init(void __iomem *base, unsigned int irq, const char *name)
|
||||
{
|
||||
__sp804_clockevents_init(base, irq, NULL, name);
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -11,4 +11,6 @@
|
|||
extern void sched_clock_postinit(void);
|
||||
extern void setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate);
|
||||
|
||||
extern unsigned long long (*sched_clock_func)(void);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -34,12 +34,4 @@ struct twd_local_timer name __initdata = { \
|
|||
|
||||
int twd_local_timer_register(struct twd_local_timer *);
|
||||
|
||||
#ifdef CONFIG_HAVE_ARM_TWD
|
||||
void twd_local_timer_of_register(void);
|
||||
#else
|
||||
static inline void twd_local_timer_of_register(void)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -22,9 +22,11 @@ static unsigned long arch_timer_read_counter_long(void)
|
|||
return arch_timer_read_counter();
|
||||
}
|
||||
|
||||
static u32 arch_timer_read_counter_u32(void)
|
||||
static u32 sched_clock_mult __read_mostly;
|
||||
|
||||
static unsigned long long notrace arch_timer_sched_clock(void)
|
||||
{
|
||||
return arch_timer_read_counter();
|
||||
return arch_timer_read_counter() * sched_clock_mult;
|
||||
}
|
||||
|
||||
static struct delay_timer arch_delay_timer;
|
||||
|
|
@ -37,25 +39,20 @@ static void __init arch_timer_delay_timer_register(void)
|
|||
register_current_timer_delay(&arch_delay_timer);
|
||||
}
|
||||
|
||||
int __init arch_timer_of_register(void)
|
||||
int __init arch_timer_arch_init(void)
|
||||
{
|
||||
int ret;
|
||||
u32 arch_timer_rate = arch_timer_get_rate();
|
||||
|
||||
ret = arch_timer_init();
|
||||
if (ret)
|
||||
return ret;
|
||||
if (arch_timer_rate == 0)
|
||||
return -ENXIO;
|
||||
|
||||
arch_timer_delay_timer_register();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int __init arch_timer_sched_clock_init(void)
|
||||
{
|
||||
if (arch_timer_get_rate() == 0)
|
||||
return -ENXIO;
|
||||
|
||||
setup_sched_clock(arch_timer_read_counter_u32,
|
||||
32, arch_timer_get_rate());
|
||||
/* Cache the sched_clock multiplier to save a divide in the hot path. */
|
||||
sched_clock_mult = NSEC_PER_SEC / arch_timer_rate;
|
||||
sched_clock_func = arch_timer_sched_clock;
|
||||
pr_info("sched_clock: ARM arch timer >56 bits at %ukHz, resolution %uns\n",
|
||||
arch_timer_rate / 1000, sched_clock_mult);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -562,21 +562,21 @@ ENDPROC(__und_usr)
|
|||
@ Fall-through from Thumb-2 __und_usr
|
||||
@
|
||||
#ifdef CONFIG_NEON
|
||||
get_thread_info r10 @ get current thread
|
||||
adr r6, .LCneon_thumb_opcodes
|
||||
b 2f
|
||||
#endif
|
||||
call_fpe:
|
||||
get_thread_info r10 @ get current thread
|
||||
#ifdef CONFIG_NEON
|
||||
adr r6, .LCneon_arm_opcodes
|
||||
2:
|
||||
ldr r7, [r6], #4 @ mask value
|
||||
cmp r7, #0 @ end mask?
|
||||
beq 1f
|
||||
and r8, r0, r7
|
||||
2: ldr r5, [r6], #4 @ mask value
|
||||
ldr r7, [r6], #4 @ opcode bits matching in mask
|
||||
cmp r5, #0 @ end mask?
|
||||
beq 1f
|
||||
and r8, r0, r5
|
||||
cmp r8, r7 @ NEON instruction?
|
||||
bne 2b
|
||||
get_thread_info r10
|
||||
mov r7, #1
|
||||
strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
|
||||
strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
|
||||
|
|
@ -586,7 +586,6 @@ call_fpe:
|
|||
tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
|
||||
tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
|
||||
moveq pc, lr
|
||||
get_thread_info r10 @ get current thread
|
||||
and r8, r0, #0x00000f00 @ mask out CP number
|
||||
THUMB( lsr r8, r8, #8 )
|
||||
mov r7, #1
|
||||
|
|
|
|||
|
|
@ -459,15 +459,16 @@ unsigned long arch_randomize_brk(struct mm_struct *mm)
|
|||
* atomic helpers and the signal restart code. Insert it into the
|
||||
* gate_vma so that it is visible through ptrace and /proc/<pid>/mem.
|
||||
*/
|
||||
static struct vm_area_struct gate_vma;
|
||||
static struct vm_area_struct gate_vma = {
|
||||
.vm_start = 0xffff0000,
|
||||
.vm_end = 0xffff0000 + PAGE_SIZE,
|
||||
.vm_flags = VM_READ | VM_EXEC | VM_MAYREAD | VM_MAYEXEC,
|
||||
.vm_mm = &init_mm,
|
||||
};
|
||||
|
||||
static int __init gate_vma_init(void)
|
||||
{
|
||||
gate_vma.vm_start = 0xffff0000;
|
||||
gate_vma.vm_end = 0xffff0000 + PAGE_SIZE;
|
||||
gate_vma.vm_page_prot = PAGE_READONLY_EXEC;
|
||||
gate_vma.vm_flags = VM_READ | VM_EXEC |
|
||||
VM_MAYREAD | VM_MAYEXEC;
|
||||
gate_vma.vm_page_prot = PAGE_READONLY_EXEC;
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(gate_vma_init);
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@ struct clock_data {
|
|||
u64 epoch_ns;
|
||||
u32 epoch_cyc;
|
||||
u32 epoch_cyc_copy;
|
||||
unsigned long rate;
|
||||
u32 mult;
|
||||
u32 shift;
|
||||
bool suspended;
|
||||
|
|
@ -113,11 +114,14 @@ void __init setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate)
|
|||
u64 res, wrap;
|
||||
char r_unit;
|
||||
|
||||
if (cd.rate > rate)
|
||||
return;
|
||||
|
||||
BUG_ON(bits > 32);
|
||||
WARN_ON(!irqs_disabled());
|
||||
WARN_ON(read_sched_clock != jiffy_sched_clock_read);
|
||||
read_sched_clock = read;
|
||||
sched_clock_mask = (1 << bits) - 1;
|
||||
cd.rate = rate;
|
||||
|
||||
/* calculate the mult/shift to convert counter ticks to ns. */
|
||||
clocks_calc_mult_shift(&cd.mult, &cd.shift, rate, NSEC_PER_SEC, 0);
|
||||
|
|
@ -161,12 +165,19 @@ void __init setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate)
|
|||
pr_debug("Registered %pF as sched_clock source\n", read);
|
||||
}
|
||||
|
||||
unsigned long long notrace sched_clock(void)
|
||||
static unsigned long long notrace sched_clock_32(void)
|
||||
{
|
||||
u32 cyc = read_sched_clock();
|
||||
return cyc_to_sched_clock(cyc, sched_clock_mask);
|
||||
}
|
||||
|
||||
unsigned long long __read_mostly (*sched_clock_func)(void) = sched_clock_32;
|
||||
|
||||
unsigned long long notrace sched_clock(void)
|
||||
{
|
||||
return sched_clock_func();
|
||||
}
|
||||
|
||||
void __init sched_clock_postinit(void)
|
||||
{
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -362,25 +362,13 @@ int __init twd_local_timer_register(struct twd_local_timer *tlt)
|
|||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
const static struct of_device_id twd_of_match[] __initconst = {
|
||||
{ .compatible = "arm,cortex-a9-twd-timer", },
|
||||
{ .compatible = "arm,cortex-a5-twd-timer", },
|
||||
{ .compatible = "arm,arm11mp-twd-timer", },
|
||||
{ },
|
||||
};
|
||||
|
||||
void __init twd_local_timer_of_register(void)
|
||||
static void __init twd_local_timer_of_register(struct device_node *np)
|
||||
{
|
||||
struct device_node *np;
|
||||
int err;
|
||||
|
||||
if (!is_smp() || !setup_max_cpus)
|
||||
return;
|
||||
|
||||
np = of_find_matching_node(NULL, twd_of_match);
|
||||
if (!np)
|
||||
return;
|
||||
|
||||
twd_ppi = irq_of_parse_and_map(np, 0);
|
||||
if (!twd_ppi) {
|
||||
err = -EINVAL;
|
||||
|
|
@ -398,4 +386,7 @@ void __init twd_local_timer_of_register(void)
|
|||
out:
|
||||
WARN(err, "twd_local_timer_of_register failed (%d)\n", err);
|
||||
}
|
||||
CLOCKSOURCE_OF_DECLARE(arm_twd_a9, "arm,cortex-a9-twd-timer", twd_local_timer_of_register);
|
||||
CLOCKSOURCE_OF_DECLARE(arm_twd_a5, "arm,cortex-a5-twd-timer", twd_local_timer_of_register);
|
||||
CLOCKSOURCE_OF_DECLARE(arm_twd_11mp, "arm,arm11mp-twd-timer", twd_local_timer_of_register);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
#include <linux/errno.h>
|
||||
#include <linux/profile.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/irq.h>
|
||||
|
||||
#include <asm/thread_info.h>
|
||||
|
|
@ -115,6 +116,10 @@ int __init register_persistent_clock(clock_access_fn read_boot,
|
|||
|
||||
void __init time_init(void)
|
||||
{
|
||||
machine_desc->init_time();
|
||||
if (machine_desc->init_time)
|
||||
machine_desc->init_time();
|
||||
else
|
||||
clocksource_of_init();
|
||||
|
||||
sched_clock_postinit();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -169,6 +169,8 @@ static struct clk *periph_clocks[] __initdata = {
|
|||
};
|
||||
|
||||
static struct clk_lookup periph_clocks_lookups[] = {
|
||||
CLKDEV_CON_DEV_ID("hclk", "at91sam9261-lcdfb.0", &hck1),
|
||||
CLKDEV_CON_DEV_ID("hclk", "at91sam9g10-lcdfb.0", &hck1),
|
||||
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
|
||||
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
|
||||
CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
|
||||
|
|
|
|||
|
|
@ -488,7 +488,6 @@ static struct resource lcdc_resources[] = {
|
|||
};
|
||||
|
||||
static struct platform_device at91_lcdc_device = {
|
||||
.name = "atmel_lcdfb",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = &lcdc_dmamask,
|
||||
|
|
@ -505,6 +504,11 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
|
|||
return;
|
||||
}
|
||||
|
||||
if (cpu_is_at91sam9g10())
|
||||
at91_lcdc_device.name = "at91sam9g10-lcdfb";
|
||||
else
|
||||
at91_lcdc_device.name = "at91sam9261-lcdfb";
|
||||
|
||||
#if defined(CONFIG_FB_ATMEL_STN)
|
||||
at91_set_A_periph(AT91_PIN_PB0, 0); /* LCDVSYNC */
|
||||
at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
|
||||
|
|
|
|||
|
|
@ -190,6 +190,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
|
|||
CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
|
||||
CLKDEV_CON_DEV_ID("pclk", "fff98000.ssc", &ssc0_clk),
|
||||
CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc1_clk),
|
||||
CLKDEV_CON_DEV_ID("hclk", "at91sam9263-lcdfb.0", &lcdc_clk),
|
||||
CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
|
||||
CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
|
||||
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
|
||||
|
|
|
|||
|
|
@ -848,7 +848,7 @@ static struct resource lcdc_resources[] = {
|
|||
};
|
||||
|
||||
static struct platform_device at91_lcdc_device = {
|
||||
.name = "atmel_lcdfb",
|
||||
.name = "at91sam9263-lcdfb",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = &lcdc_dmamask,
|
||||
|
|
|
|||
|
|
@ -228,6 +228,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
|
|||
CLKDEV_CON_ID("hclk", &macb_clk),
|
||||
/* One additional fake clock for ohci */
|
||||
CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
|
||||
CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk),
|
||||
CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk),
|
||||
CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
|
||||
CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
|
||||
CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
|
||||
|
|
|
|||
|
|
@ -981,7 +981,6 @@ static struct resource lcdc_resources[] = {
|
|||
};
|
||||
|
||||
static struct platform_device at91_lcdc_device = {
|
||||
.name = "atmel_lcdfb",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = &lcdc_dmamask,
|
||||
|
|
@ -997,6 +996,11 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
|
|||
if (!data)
|
||||
return;
|
||||
|
||||
if (cpu_is_at91sam9g45es())
|
||||
at91_lcdc_device.name = "at91sam9g45es-lcdfb";
|
||||
else
|
||||
at91_lcdc_device.name = "at91sam9g45-lcdfb";
|
||||
|
||||
at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
|
||||
|
||||
at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
|
||||
|
|
|
|||
|
|
@ -179,6 +179,7 @@ static struct clk *periph_clocks[] __initdata = {
|
|||
};
|
||||
|
||||
static struct clk_lookup periph_clocks_lookups[] = {
|
||||
CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
|
||||
CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
|
||||
CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
|
||||
CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
|
||||
|
|
|
|||
|
|
@ -514,7 +514,7 @@ static struct resource lcdc_resources[] = {
|
|||
};
|
||||
|
||||
static struct platform_device at91_lcdc_device = {
|
||||
.name = "atmel_lcdfb",
|
||||
.name = "at91sam9rl-lcdfb",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = &lcdc_dmamask,
|
||||
|
|
|
|||
|
|
@ -79,12 +79,6 @@ config SOC_EXYNOS5440
|
|||
help
|
||||
Enable EXYNOS5440 SoC support
|
||||
|
||||
config EXYNOS4_MCT
|
||||
bool
|
||||
default y
|
||||
help
|
||||
Use MCT (Multi Core Timer) as kernel timers
|
||||
|
||||
config EXYNOS_DEV_DMA
|
||||
bool
|
||||
help
|
||||
|
|
@ -276,8 +270,8 @@ config MACH_UNIVERSAL_C210
|
|||
select S5P_DEV_ONENAND
|
||||
select S5P_DEV_TV
|
||||
select S5P_GPIO_INT
|
||||
select S5P_HRT
|
||||
select S5P_SETUP_MIPIPHY
|
||||
select SAMSUNG_HRT
|
||||
help
|
||||
Machine support for Samsung Mobile Universal S5PC210 Reference
|
||||
Board.
|
||||
|
|
@ -406,6 +400,7 @@ config MACH_EXYNOS4_DT
|
|||
bool "Samsung Exynos4 Machine using device tree"
|
||||
depends on ARCH_EXYNOS4
|
||||
select ARM_AMBA
|
||||
select CLKSRC_OF
|
||||
select CPU_EXYNOS4210
|
||||
select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
|
||||
select PINCTRL
|
||||
|
|
@ -422,6 +417,7 @@ config MACH_EXYNOS5_DT
|
|||
default y
|
||||
depends on ARCH_EXYNOS5
|
||||
select ARM_AMBA
|
||||
select CLKSRC_OF
|
||||
select USE_OF
|
||||
help
|
||||
Machine support for Samsung EXYNOS5 machine with device tree enabled.
|
||||
|
|
|
|||
|
|
@ -26,8 +26,6 @@ obj-$(CONFIG_ARCH_EXYNOS) += pmu.o
|
|||
|
||||
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
|
||||
|
||||
obj-$(CONFIG_EXYNOS4_MCT) += mct.o
|
||||
|
||||
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
|
||||
# machine support
|
||||
|
|
|
|||
|
|
@ -256,11 +256,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
|
|||
.pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_SYSTIMER,
|
||||
.pfn = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_SYSRAM,
|
||||
.pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
|
||||
|
|
@ -822,6 +817,7 @@ static int __init exynos_init_irq_eint(void)
|
|||
static const struct of_device_id exynos_pinctrl_ids[] = {
|
||||
{ .compatible = "samsung,exynos4210-pinctrl", },
|
||||
{ .compatible = "samsung,exynos4x12-pinctrl", },
|
||||
{ .compatible = "samsung,exynos5250-pinctrl", },
|
||||
};
|
||||
struct device_node *pctrl_np, *wkup_np;
|
||||
const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@
|
|||
#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
|
||||
#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
|
||||
|
||||
extern void exynos4_timer_init(void);
|
||||
extern void mct_init(void);
|
||||
|
||||
struct map_desc;
|
||||
void exynos_init_io(struct map_desc *mach_desc, int size);
|
||||
|
|
|
|||
|
|
@ -30,8 +30,6 @@
|
|||
|
||||
/* For EXYNOS4 and EXYNOS5 */
|
||||
|
||||
#define EXYNOS_IRQ_MCT_LOCALTIMER IRQ_PPI(12)
|
||||
|
||||
#define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32)
|
||||
|
||||
/* For EXYNOS4 SoCs */
|
||||
|
|
@ -323,8 +321,6 @@
|
|||
#define EXYNOS5_IRQ_CEC IRQ_SPI(114)
|
||||
#define EXYNOS5_IRQ_SATA IRQ_SPI(115)
|
||||
|
||||
#define EXYNOS5_IRQ_MCT_L0 IRQ_SPI(120)
|
||||
#define EXYNOS5_IRQ_MCT_L1 IRQ_SPI(121)
|
||||
#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123)
|
||||
#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124)
|
||||
#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125)
|
||||
|
|
@ -419,8 +415,6 @@
|
|||
#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0)
|
||||
#define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3)
|
||||
#define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0)
|
||||
#define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1)
|
||||
|
|
|
|||
|
|
@ -65,7 +65,6 @@
|
|||
#define EXYNOS5_PA_CMU 0x10010000
|
||||
|
||||
#define EXYNOS4_PA_SYSTIMER 0x10050000
|
||||
#define EXYNOS5_PA_SYSTIMER 0x101C0000
|
||||
|
||||
#define EXYNOS4_PA_WATCHDOG 0x10060000
|
||||
#define EXYNOS5_PA_WATCHDOG 0x101D0000
|
||||
|
|
|
|||
|
|
@ -1,53 +0,0 @@
|
|||
/* arch/arm/mach-exynos4/include/mach/regs-mct.h
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4 MCT configutation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_REGS_MCT_H
|
||||
#define __ASM_ARCH_REGS_MCT_H __FILE__
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
#define EXYNOS4_MCTREG(x) (S5P_VA_SYSTIMER + (x))
|
||||
|
||||
#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
|
||||
#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
|
||||
#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
|
||||
|
||||
#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
|
||||
#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
|
||||
#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
|
||||
|
||||
#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
|
||||
|
||||
#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
|
||||
#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
|
||||
#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
|
||||
|
||||
#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
|
||||
#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
|
||||
#define EXYNOS4_MCT_L_MASK (0xffffff00)
|
||||
|
||||
#define MCT_L_TCNTB_OFFSET (0x00)
|
||||
#define MCT_L_ICNTB_OFFSET (0x08)
|
||||
#define MCT_L_TCON_OFFSET (0x20)
|
||||
#define MCT_L_INT_CSTAT_OFFSET (0x30)
|
||||
#define MCT_L_INT_ENB_OFFSET (0x34)
|
||||
#define MCT_L_WSTAT_OFFSET (0x40)
|
||||
|
||||
#define MCT_G_TCON_START (1 << 8)
|
||||
#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
|
||||
#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
|
||||
|
||||
#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
|
||||
#define MCT_L_TCON_INT_START (1 << 1)
|
||||
#define MCT_L_TCON_TIMER_START (1 << 0)
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_MCT_H */
|
||||
|
|
@ -202,6 +202,6 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
|
|||
.map_io = armlex4210_map_io,
|
||||
.init_machine = armlex4210_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = mct_init,
|
||||
.restart = exynos4_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/clocksource.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <mach/map.h>
|
||||
|
|
@ -142,7 +143,7 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
|
|||
.map_io = exynos4_dt_map_io,
|
||||
.init_machine = exynos4_dt_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = clocksource_of_init,
|
||||
.dt_compat = exynos4_dt_compat,
|
||||
.restart = exynos4_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@
|
|||
#include <linux/serial_core.h>
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/clocksource.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <mach/map.h>
|
||||
|
|
@ -216,7 +217,6 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
|
|||
.map_io = exynos5_dt_map_io,
|
||||
.init_machine = exynos5_dt_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = exynos4_timer_init,
|
||||
.dt_compat = exynos5_dt_compat,
|
||||
.restart = exynos5_restart,
|
||||
.reserve = exynos5_reserve,
|
||||
|
|
|
|||
|
|
@ -1380,7 +1380,7 @@ MACHINE_START(NURI, "NURI")
|
|||
.map_io = nuri_map_io,
|
||||
.init_machine = nuri_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = mct_init,
|
||||
.reserve = &nuri_reserve,
|
||||
.restart = exynos4_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -815,7 +815,7 @@ MACHINE_START(ORIGEN, "ORIGEN")
|
|||
.map_io = origen_map_io,
|
||||
.init_machine = origen_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = mct_init,
|
||||
.reserve = &origen_reserve,
|
||||
.restart = exynos4_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -376,7 +376,7 @@ MACHINE_START(SMDK4212, "SMDK4212")
|
|||
.init_irq = exynos4_init_irq,
|
||||
.map_io = smdk4x12_map_io,
|
||||
.init_machine = smdk4x12_machine_init,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = mct_init,
|
||||
.restart = exynos4_restart,
|
||||
.reserve = &smdk4x12_reserve,
|
||||
MACHINE_END
|
||||
|
|
@ -390,7 +390,7 @@ MACHINE_START(SMDK4412, "SMDK4412")
|
|||
.map_io = smdk4x12_map_io,
|
||||
.init_machine = smdk4x12_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = mct_init,
|
||||
.restart = exynos4_restart,
|
||||
.reserve = &smdk4x12_reserve,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -423,7 +423,7 @@ MACHINE_START(SMDKV310, "SMDKV310")
|
|||
.init_irq = exynos4_init_irq,
|
||||
.map_io = smdkv310_map_io,
|
||||
.init_machine = smdkv310_machine_init,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = mct_init,
|
||||
.reserve = &smdkv310_reserve,
|
||||
.restart = exynos4_restart,
|
||||
MACHINE_END
|
||||
|
|
@ -436,7 +436,7 @@ MACHINE_START(SMDKC210, "SMDKC210")
|
|||
.map_io = smdkv310_map_io,
|
||||
.init_machine = smdkv310_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = mct_init,
|
||||
.reserve = &smdkv310_reserve,
|
||||
.restart = exynos4_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@
|
|||
#include <plat/mfc.h>
|
||||
#include <plat/sdhci.h>
|
||||
#include <plat/fimc-core.h>
|
||||
#include <plat/s5p-time.h>
|
||||
#include <plat/samsung-time.h>
|
||||
#include <plat/camport.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
|
|
@ -1094,7 +1094,7 @@ static void __init universal_map_io(void)
|
|||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(clk_xusbxti.rate);
|
||||
s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
|
||||
s5p_set_timer_source(S5P_PWM2, S5P_PWM4);
|
||||
samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4);
|
||||
}
|
||||
|
||||
static void s5p_tv_setup(void)
|
||||
|
|
@ -1152,7 +1152,7 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
|
|||
.map_io = universal_map_io,
|
||||
.init_machine = universal_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = s5p_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.reserve = &universal_reserve,
|
||||
.restart = exynos4_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@
|
|||
*/
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
|
|
@ -28,13 +29,9 @@
|
|||
#include <linux/amba/bus.h>
|
||||
#include <linux/clk-provider.h>
|
||||
|
||||
#include <asm/arch_timer.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/cputype.h>
|
||||
#include <asm/smp_plat.h>
|
||||
#include <asm/smp_twd.h>
|
||||
#include <asm/hardware/arm_timer.h>
|
||||
#include <asm/hardware/timer-sp.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
|
@ -91,38 +88,18 @@ static void __init highbank_init_irq(void)
|
|||
#endif
|
||||
}
|
||||
|
||||
static struct clk_lookup lookup = {
|
||||
.dev_id = "sp804",
|
||||
.con_id = NULL,
|
||||
};
|
||||
|
||||
static void __init highbank_timer_init(void)
|
||||
{
|
||||
int irq;
|
||||
struct device_node *np;
|
||||
void __iomem *timer_base;
|
||||
|
||||
/* Map system registers */
|
||||
np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
|
||||
sregs_base = of_iomap(np, 0);
|
||||
WARN_ON(!sregs_base);
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "arm,sp804");
|
||||
timer_base = of_iomap(np, 0);
|
||||
WARN_ON(!timer_base);
|
||||
irq = irq_of_parse_and_map(np, 0);
|
||||
|
||||
of_clk_init(NULL);
|
||||
lookup.clk = of_clk_get(np, 0);
|
||||
clkdev_add(&lookup);
|
||||
|
||||
sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1");
|
||||
sp804_clockevents_init(timer_base, irq, "timer0");
|
||||
|
||||
twd_local_timer_of_register();
|
||||
|
||||
arch_timer_of_register();
|
||||
arch_timer_sched_clock_init();
|
||||
clocksource_of_init();
|
||||
}
|
||||
|
||||
static void highbank_power_off(void)
|
||||
|
|
|
|||
|
|
@ -169,7 +169,7 @@ struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
|
|||
|
||||
busy->mux.reg = reg;
|
||||
busy->mux.shift = shift;
|
||||
busy->mux.width = width;
|
||||
busy->mux.mask = BIT(width) - 1;
|
||||
busy->mux.lock = &imx_ccm_lock;
|
||||
busy->mux_ops = &clk_mux_ops;
|
||||
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/cpu.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/export.h>
|
||||
|
|
@ -28,11 +29,9 @@
|
|||
#include <linux/regmap.h>
|
||||
#include <linux/micrel_phy.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <asm/smp_twd.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/system_misc.h>
|
||||
|
||||
#include "common.h"
|
||||
|
|
@ -292,7 +291,7 @@ static void __init imx6q_init_irq(void)
|
|||
static void __init imx6q_timer_init(void)
|
||||
{
|
||||
mx6q_clocks_init();
|
||||
twd_local_timer_of_register();
|
||||
clocksource_of_init();
|
||||
imx_print_silicon_rev("i.MX6Q", imx6q_revision());
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -536,16 +536,14 @@ static void __init ap_init_of(void)
|
|||
'A' + (ap_sc_id & 0x0f));
|
||||
|
||||
soc_dev = soc_device_register(soc_dev_attr);
|
||||
if (IS_ERR_OR_NULL(soc_dev)) {
|
||||
if (IS_ERR(soc_dev)) {
|
||||
kfree(soc_dev_attr->revision);
|
||||
kfree(soc_dev_attr);
|
||||
return;
|
||||
}
|
||||
|
||||
parent = soc_device_to_device(soc_dev);
|
||||
|
||||
if (!IS_ERR_OR_NULL(parent))
|
||||
integrator_init_sysfs(parent, ap_sc_id);
|
||||
integrator_init_sysfs(parent, ap_sc_id);
|
||||
|
||||
of_platform_populate(root, of_default_bus_match_table,
|
||||
ap_auxdata_lookup, parent);
|
||||
|
|
|
|||
|
|
@ -250,39 +250,6 @@ static void __init intcp_init_early(void)
|
|||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
|
||||
static void __init cp_of_timer_init(void)
|
||||
{
|
||||
struct device_node *node;
|
||||
const char *path;
|
||||
void __iomem *base;
|
||||
int err;
|
||||
int irq;
|
||||
|
||||
err = of_property_read_string(of_aliases,
|
||||
"arm,timer-primary", &path);
|
||||
if (WARN_ON(err))
|
||||
return;
|
||||
node = of_find_node_by_path(path);
|
||||
base = of_iomap(node, 0);
|
||||
if (WARN_ON(!base))
|
||||
return;
|
||||
writel(0, base + TIMER_CTRL);
|
||||
sp804_clocksource_init(base, node->name);
|
||||
|
||||
err = of_property_read_string(of_aliases,
|
||||
"arm,timer-secondary", &path);
|
||||
if (WARN_ON(err))
|
||||
return;
|
||||
node = of_find_node_by_path(path);
|
||||
base = of_iomap(node, 0);
|
||||
if (WARN_ON(!base))
|
||||
return;
|
||||
irq = irq_of_parse_and_map(node, 0);
|
||||
writel(0, base + TIMER_CTRL);
|
||||
sp804_clockevents_init(base, irq, node->name);
|
||||
}
|
||||
|
||||
static const struct of_device_id fpga_irq_of_match[] __initconst = {
|
||||
{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
|
||||
{ /* Sentinel */ }
|
||||
|
|
@ -360,17 +327,14 @@ static void __init intcp_init_of(void)
|
|||
'A' + (intcp_sc_id & 0x0f));
|
||||
|
||||
soc_dev = soc_device_register(soc_dev_attr);
|
||||
if (IS_ERR_OR_NULL(soc_dev)) {
|
||||
if (IS_ERR(soc_dev)) {
|
||||
kfree(soc_dev_attr->revision);
|
||||
kfree(soc_dev_attr);
|
||||
return;
|
||||
}
|
||||
|
||||
parent = soc_device_to_device(soc_dev);
|
||||
|
||||
if (!IS_ERR_OR_NULL(parent))
|
||||
integrator_init_sysfs(parent, intcp_sc_id);
|
||||
|
||||
integrator_init_sysfs(parent, intcp_sc_id);
|
||||
of_platform_populate(root, of_default_bus_match_table,
|
||||
intcp_auxdata_lookup, parent);
|
||||
}
|
||||
|
|
@ -386,7 +350,6 @@ DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
|
|||
.init_early = intcp_init_early,
|
||||
.init_irq = intcp_init_irq_of,
|
||||
.handle_irq = fpga_handle_irq,
|
||||
.init_time = cp_of_timer_init,
|
||||
.init_machine = intcp_init_of,
|
||||
.restart = integrator_restart,
|
||||
.dt_compat = intcp_dt_board_compat,
|
||||
|
|
|
|||
|
|
@ -428,16 +428,23 @@ static void enable_board_wakeup_source(void)
|
|||
OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
|
||||
}
|
||||
|
||||
static struct usbhs_phy_data phy_data[] __initdata = {
|
||||
{
|
||||
.port = 1,
|
||||
.reset_gpio = 57,
|
||||
.vcc_gpio = -EINVAL,
|
||||
},
|
||||
{
|
||||
.port = 2,
|
||||
.reset_gpio = 61,
|
||||
.vcc_gpio = -EINVAL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||
|
||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
|
||||
.phy_reset = true,
|
||||
.reset_gpio_port[0] = 57,
|
||||
.reset_gpio_port[1] = 61,
|
||||
.reset_gpio_port[2] = -EINVAL
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
|
|
@ -589,6 +596,8 @@ static void __init omap_3430sdp_init(void)
|
|||
board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
|
||||
sdp3430_display_init();
|
||||
enable_board_wakeup_source();
|
||||
|
||||
usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
|
||||
usbhs_init(&usbhs_bdata);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -53,16 +53,23 @@ static void enable_board_wakeup_source(void)
|
|||
OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
|
||||
}
|
||||
|
||||
static struct usbhs_phy_data phy_data[] __initdata = {
|
||||
{
|
||||
.port = 1,
|
||||
.reset_gpio = 126,
|
||||
.vcc_gpio = -EINVAL,
|
||||
},
|
||||
{
|
||||
.port = 2,
|
||||
.reset_gpio = 61,
|
||||
.vcc_gpio = -EINVAL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||
|
||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
|
||||
.phy_reset = true,
|
||||
.reset_gpio_port[0] = 126,
|
||||
.reset_gpio_port[1] = 61,
|
||||
.reset_gpio_port[2] = -EINVAL
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
|
|
@ -199,6 +206,8 @@ static void __init omap_sdp_init(void)
|
|||
board_smc91x_init();
|
||||
board_flash_init(sdp_flash_partitions, chip_sel_sdp, NAND_BUSWIDTH_16);
|
||||
enable_board_wakeup_source();
|
||||
|
||||
usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
|
||||
usbhs_init(&usbhs_bdata);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -47,15 +47,17 @@ static struct omap_board_mux board_mux[] __initdata = {
|
|||
};
|
||||
#endif
|
||||
|
||||
static struct usbhs_phy_data phy_data[] __initdata = {
|
||||
{
|
||||
.port = 1,
|
||||
.reset_gpio = GPIO_USB_NRESET,
|
||||
.vcc_gpio = GPIO_USB_POWER,
|
||||
.vcc_polarity = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
|
||||
.phy_reset = true,
|
||||
.reset_gpio_port[0] = GPIO_USB_NRESET,
|
||||
.reset_gpio_port[1] = -EINVAL,
|
||||
.reset_gpio_port[2] = -EINVAL
|
||||
};
|
||||
|
||||
static struct mtd_partition crane_nand_partitions[] = {
|
||||
|
|
@ -131,13 +133,7 @@ static void __init am3517_crane_init(void)
|
|||
return;
|
||||
}
|
||||
|
||||
ret = gpio_request_one(GPIO_USB_POWER, GPIOF_OUT_INIT_HIGH,
|
||||
"usb_ehci_enable");
|
||||
if (ret < 0) {
|
||||
pr_err("Can not request GPIO %d\n", GPIO_USB_POWER);
|
||||
return;
|
||||
}
|
||||
|
||||
usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
|
||||
usbhs_init(&usbhs_bdata);
|
||||
am35xx_emac_init(AM35XX_DEFAULT_MDIO_FREQUENCY, 1);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -213,6 +213,14 @@ static __init void am3517_evm_mcbsp1_init(void)
|
|||
omap_ctrl_writel(devconf0, OMAP2_CONTROL_DEVCONF0);
|
||||
}
|
||||
|
||||
static struct usbhs_phy_data phy_data[] __initdata = {
|
||||
{
|
||||
.port = 1,
|
||||
.reset_gpio = 57,
|
||||
.vcc_gpio = -EINVAL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
#if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \
|
||||
|
|
@ -221,12 +229,6 @@ static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
|||
#else
|
||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
#endif
|
||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
|
||||
.phy_reset = true,
|
||||
.reset_gpio_port[0] = 57,
|
||||
.reset_gpio_port[1] = -EINVAL,
|
||||
.reset_gpio_port[2] = -EINVAL
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
|
|
@ -288,7 +290,6 @@ static struct omap2_hsmmc_info mmc[] = {
|
|||
{} /* Terminator */
|
||||
};
|
||||
|
||||
|
||||
static void __init am3517_evm_init(void)
|
||||
{
|
||||
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
|
||||
|
|
@ -300,6 +301,8 @@ static void __init am3517_evm_init(void)
|
|||
|
||||
/* Configure GPIO for EHCI port */
|
||||
omap_mux_init_gpio(57, OMAP_PIN_OUTPUT);
|
||||
|
||||
usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
|
||||
usbhs_init(&usbhs_bdata);
|
||||
am3517_evm_hecc_init(&am3517_evm_hecc_pdata);
|
||||
|
||||
|
|
|
|||
|
|
@ -376,15 +376,22 @@ static struct omap2_hsmmc_info mmc[] = {
|
|||
{} /* Terminator */
|
||||
};
|
||||
|
||||
static struct usbhs_phy_data phy_data[] __initdata = {
|
||||
{
|
||||
.port = 1,
|
||||
.reset_gpio = OMAP_MAX_GPIO_LINES + 6,
|
||||
.vcc_gpio = -EINVAL,
|
||||
},
|
||||
{
|
||||
.port = 2,
|
||||
.reset_gpio = OMAP_MAX_GPIO_LINES + 7,
|
||||
.vcc_gpio = -EINVAL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
|
||||
.phy_reset = true,
|
||||
.reset_gpio_port[0] = OMAP_MAX_GPIO_LINES + 6,
|
||||
.reset_gpio_port[1] = OMAP_MAX_GPIO_LINES + 7,
|
||||
.reset_gpio_port[2] = -EINVAL
|
||||
};
|
||||
|
||||
static void __init cm_t35_init_usbh(void)
|
||||
|
|
@ -401,6 +408,7 @@ static void __init cm_t35_init_usbh(void)
|
|||
msleep(1);
|
||||
}
|
||||
|
||||
usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
|
||||
usbhs_init(&usbhs_bdata);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -188,15 +188,22 @@ static inline void cm_t3517_init_rtc(void) {}
|
|||
#define HSUSB2_RESET_GPIO (147)
|
||||
#define USB_HUB_RESET_GPIO (152)
|
||||
|
||||
static struct usbhs_phy_data phy_data[] __initdata = {
|
||||
{
|
||||
.port = 1,
|
||||
.reset_gpio = HSUSB1_RESET_GPIO,
|
||||
.vcc_gpio = -EINVAL,
|
||||
},
|
||||
{
|
||||
.port = 2,
|
||||
.reset_gpio = HSUSB2_RESET_GPIO,
|
||||
.vcc_gpio = -EINVAL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct usbhs_omap_platform_data cm_t3517_ehci_pdata __initdata = {
|
||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
|
||||
.phy_reset = true,
|
||||
.reset_gpio_port[0] = HSUSB1_RESET_GPIO,
|
||||
.reset_gpio_port[1] = HSUSB2_RESET_GPIO,
|
||||
.reset_gpio_port[2] = -EINVAL,
|
||||
};
|
||||
|
||||
static int __init cm_t3517_init_usbh(void)
|
||||
|
|
@ -213,6 +220,7 @@ static int __init cm_t3517_init_usbh(void)
|
|||
msleep(1);
|
||||
}
|
||||
|
||||
usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
|
||||
usbhs_init(&cm_t3517_ehci_pdata);
|
||||
|
||||
return 0;
|
||||
|
|
@ -324,6 +332,6 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
|
|||
.handle_irq = omap3_intc_handle_irq,
|
||||
.init_machine = cm_t3517_init,
|
||||
.init_late = am35xx_init_late,
|
||||
.init_time = omap3_gp_gptimer_timer_init,
|
||||
.init_time = omap3_gptimer_timer_init,
|
||||
.restart = omap3xxx_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -415,15 +415,7 @@ static struct platform_device *devkit8000_devices[] __initdata = {
|
|||
};
|
||||
|
||||
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||
|
||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
|
||||
.phy_reset = true,
|
||||
.reset_gpio_port[0] = -EINVAL,
|
||||
.reset_gpio_port[1] = -EINVAL,
|
||||
.reset_gpio_port[2] = -EINVAL
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
|
|
|
|||
|
|
@ -140,7 +140,7 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
|
|||
.init_irq = omap_intc_of_init,
|
||||
.handle_irq = omap3_intc_handle_irq,
|
||||
.init_machine = omap_generic_init,
|
||||
.init_time = omap3_am33xx_gptimer_timer_init,
|
||||
.init_time = omap3_gptimer_timer_init,
|
||||
.dt_compat = am33xx_boards_compat,
|
||||
.restart = am33xx_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -527,26 +527,28 @@ static void __init igep_i2c_init(void)
|
|||
omap3_pmic_init("twl4030", &igep_twldata);
|
||||
}
|
||||
|
||||
static struct usbhs_phy_data igep2_phy_data[] __initdata = {
|
||||
{
|
||||
.port = 1,
|
||||
.reset_gpio = IGEP2_GPIO_USBH_NRESET,
|
||||
.vcc_gpio = -EINVAL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct usbhs_phy_data igep3_phy_data[] __initdata = {
|
||||
{
|
||||
.port = 2,
|
||||
.reset_gpio = IGEP3_GPIO_USBH_NRESET,
|
||||
.vcc_gpio = -EINVAL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct usbhs_omap_platform_data igep2_usbhs_bdata __initdata = {
|
||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
|
||||
.phy_reset = true,
|
||||
.reset_gpio_port[0] = IGEP2_GPIO_USBH_NRESET,
|
||||
.reset_gpio_port[1] = -EINVAL,
|
||||
.reset_gpio_port[2] = -EINVAL,
|
||||
};
|
||||
|
||||
static struct usbhs_omap_platform_data igep3_usbhs_bdata __initdata = {
|
||||
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
|
||||
.phy_reset = true,
|
||||
.reset_gpio_port[0] = -EINVAL,
|
||||
.reset_gpio_port[1] = IGEP3_GPIO_USBH_NRESET,
|
||||
.reset_gpio_port[2] = -EINVAL,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
|
|
@ -642,8 +644,10 @@ static void __init igep_init(void)
|
|||
if (machine_is_igep0020()) {
|
||||
omap_display_init(&igep2_dss_data);
|
||||
igep2_init_smsc911x();
|
||||
usbhs_init_phys(igep2_phy_data, ARRAY_SIZE(igep2_phy_data));
|
||||
usbhs_init(&igep2_usbhs_bdata);
|
||||
} else {
|
||||
usbhs_init_phys(igep3_phy_data, ARRAY_SIZE(igep3_phy_data));
|
||||
usbhs_init(&igep3_usbhs_bdata);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@
|
|||
#include <linux/mtd/nand.h>
|
||||
#include <linux/mmc/host.h>
|
||||
#include <linux/usb/phy.h>
|
||||
#include <linux/usb/nop-usb-xceiv.h>
|
||||
|
||||
#include <linux/regulator/machine.h>
|
||||
#include <linux/i2c/twl.h>
|
||||
|
|
@ -277,6 +278,21 @@ static struct regulator_consumer_supply beagle_vsim_supply[] = {
|
|||
|
||||
static struct gpio_led gpio_leds[];
|
||||
|
||||
/* PHY's VCC regulator might be added later, so flag that we need it */
|
||||
static struct nop_usb_xceiv_platform_data hsusb2_phy_data = {
|
||||
.needs_vcc = true,
|
||||
};
|
||||
|
||||
static struct usbhs_phy_data phy_data[] = {
|
||||
{
|
||||
.port = 2,
|
||||
.reset_gpio = 147,
|
||||
.vcc_gpio = -1, /* updated in beagle_twl_gpio_setup */
|
||||
.vcc_polarity = 1, /* updated in beagle_twl_gpio_setup */
|
||||
.platform_data = &hsusb2_phy_data,
|
||||
},
|
||||
};
|
||||
|
||||
static int beagle_twl_gpio_setup(struct device *dev,
|
||||
unsigned gpio, unsigned ngpio)
|
||||
{
|
||||
|
|
@ -318,9 +334,11 @@ static int beagle_twl_gpio_setup(struct device *dev,
|
|||
}
|
||||
dvi_panel.power_down_gpio = beagle_config.dvi_pd_gpio;
|
||||
|
||||
gpio_request_one(gpio + TWL4030_GPIO_MAX, beagle_config.usb_pwr_level,
|
||||
"nEN_USB_PWR");
|
||||
/* TWL4030_GPIO_MAX i.e. LED_GPO controls HS USB Port 2 power */
|
||||
phy_data[0].vcc_gpio = gpio + TWL4030_GPIO_MAX;
|
||||
phy_data[0].vcc_polarity = beagle_config.usb_pwr_level;
|
||||
|
||||
usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -453,15 +471,7 @@ static struct platform_device *omap3_beagle_devices[] __initdata = {
|
|||
};
|
||||
|
||||
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||
|
||||
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
|
||||
.phy_reset = true,
|
||||
.reset_gpio_port[0] = -EINVAL,
|
||||
.reset_gpio_port[1] = 147,
|
||||
.reset_gpio_port[2] = -EINVAL
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
|
|
@ -479,7 +489,7 @@ static int __init beagle_opp_init(void)
|
|||
|
||||
/* Initialize the omap3 opp table if not already created. */
|
||||
r = omap3_opp_init();
|
||||
if (IS_ERR_VALUE(r) && (r != -EEXIST)) {
|
||||
if (r < 0 && (r != -EEXIST)) {
|
||||
pr_err("%s: opp default init failed\n", __func__);
|
||||
return r;
|
||||
}
|
||||
|
|
@ -543,7 +553,9 @@ static void __init omap3_beagle_init(void)
|
|||
|
||||
usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
|
||||
usb_musb_init(NULL);
|
||||
|
||||
usbhs_init(&usbhs_bdata);
|
||||
|
||||
board_nand_init(omap3beagle_nand_partitions,
|
||||
ARRAY_SIZE(omap3beagle_nand_partitions), NAND_CS,
|
||||
NAND_BUSWIDTH_16, NULL);
|
||||
|
|
|
|||
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