x86, irq: Move PCI MSI related code from io_apic.c into msi.c
Create arch/x86/kernel/apic/msi.c to host MSI related code, preparing for enabling hierarchy irqdomain. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Joerg Roedel <joro@8bytes.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Prarit Bhargava <prarit@redhat.com> Link: http://lkml.kernel.org/r/1414397531-28254-12-git-send-email-jiang.liu@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Jiang Liu
Thomas Gleixner
Родитель
849d3569bb
Коммит
443809828c
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@ -148,9 +148,6 @@ extern int native_setup_ioapic_entry(int, struct IO_APIC_route_entry *,
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struct io_apic_irq_attr *);
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extern void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg);
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extern void native_compose_msi_msg(struct pci_dev *pdev,
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unsigned int irq, unsigned int dest,
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struct msi_msg *msg, u8 hpet_id);
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extern void native_eoi_ioapic_pin(int apic, int pin, int vector);
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extern int save_ioapic_entries(void);
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@ -261,7 +258,6 @@ static inline void disable_ioapic_support(void) { }
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#define native_io_apic_print_entries NULL
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#define native_ioapic_set_affinity NULL
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#define native_setup_ioapic_entry NULL
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#define native_compose_msi_msg NULL
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#define native_eoi_ioapic_pin NULL
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#endif
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@ -96,12 +96,15 @@ extern void pci_iommu_alloc(void);
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#ifdef CONFIG_PCI_MSI
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/* implemented in arch/x86/kernel/apic/io_apic. */
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struct msi_desc;
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void native_compose_msi_msg(struct pci_dev *pdev, unsigned int irq,
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unsigned int dest, struct msi_msg *msg, u8 hpet_id);
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int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
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void native_teardown_msi_irq(unsigned int irq);
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void native_restore_msi_irqs(struct pci_dev *dev);
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int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc,
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unsigned int irq_base, unsigned int irq_offset);
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#else
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#define native_compose_msi_msg NULL
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#define native_setup_msi_irqs NULL
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#define native_teardown_msi_irq NULL
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#endif
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@ -6,6 +6,7 @@ obj-$(CONFIG_X86_LOCAL_APIC) += apic.o apic_noop.o ipi.o vector.o
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obj-y += hw_nmi.o
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obj-$(CONFIG_X86_IO_APIC) += io_apic.o
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obj-$(CONFIG_PCI_MSI) += msi.o
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obj-$(CONFIG_SMP) += ipi.o
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ifeq ($(CONFIG_X86_64),y)
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@ -32,15 +32,12 @@
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#include <linux/module.h>
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#include <linux/syscore_ops.h>
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#include <linux/irqdomain.h>
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#include <linux/msi.h>
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#include <linux/htirq.h>
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#include <linux/freezer.h>
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#include <linux/kthread.h>
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#include <linux/jiffies.h> /* time_after() */
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#include <linux/slab.h>
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#include <linux/bootmem.h>
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#include <linux/dmar.h>
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#include <linux/hpet.h>
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#include <asm/idle.h>
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#include <asm/io.h>
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@ -52,11 +49,9 @@
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#include <asm/dma.h>
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#include <asm/timer.h>
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#include <asm/i8259.h>
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#include <asm/msidef.h>
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#include <asm/hypertransport.h>
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#include <asm/setup.h>
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#include <asm/irq_remapping.h>
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#include <asm/hpet.h>
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#include <asm/hw_irq.h>
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#include <asm/apic.h>
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@ -2455,273 +2450,6 @@ static int __init ioapic_init_ops(void)
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device_initcall(ioapic_init_ops);
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/*
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* MSI message composition
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*/
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void native_compose_msi_msg(struct pci_dev *pdev,
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unsigned int irq, unsigned int dest,
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struct msi_msg *msg, u8 hpet_id)
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{
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struct irq_cfg *cfg = irq_cfg(irq);
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msg->address_hi = MSI_ADDR_BASE_HI;
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if (x2apic_enabled())
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msg->address_hi |= MSI_ADDR_EXT_DEST_ID(dest);
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msg->address_lo =
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MSI_ADDR_BASE_LO |
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((apic->irq_dest_mode == 0) ?
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MSI_ADDR_DEST_MODE_PHYSICAL:
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MSI_ADDR_DEST_MODE_LOGICAL) |
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((apic->irq_delivery_mode != dest_LowestPrio) ?
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MSI_ADDR_REDIRECTION_CPU:
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MSI_ADDR_REDIRECTION_LOWPRI) |
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MSI_ADDR_DEST_ID(dest);
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msg->data =
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MSI_DATA_TRIGGER_EDGE |
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MSI_DATA_LEVEL_ASSERT |
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((apic->irq_delivery_mode != dest_LowestPrio) ?
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MSI_DATA_DELIVERY_FIXED:
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MSI_DATA_DELIVERY_LOWPRI) |
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MSI_DATA_VECTOR(cfg->vector);
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}
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#ifdef CONFIG_PCI_MSI
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static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
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struct msi_msg *msg, u8 hpet_id)
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{
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struct irq_cfg *cfg;
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int err;
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unsigned dest;
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if (disable_apic)
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return -ENXIO;
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cfg = irq_cfg(irq);
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err = assign_irq_vector(irq, cfg, apic->target_cpus());
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if (err)
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return err;
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err = apic->cpu_mask_to_apicid_and(cfg->domain,
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apic->target_cpus(), &dest);
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if (err)
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return err;
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x86_msi.compose_msi_msg(pdev, irq, dest, msg, hpet_id);
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return 0;
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}
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static int
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msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
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{
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struct irq_cfg *cfg = data->chip_data;
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struct msi_msg msg;
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unsigned int dest;
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int ret;
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ret = apic_set_affinity(data, mask, &dest);
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if (ret)
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return ret;
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__get_cached_msi_msg(data->msi_desc, &msg);
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msg.data &= ~MSI_DATA_VECTOR_MASK;
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msg.data |= MSI_DATA_VECTOR(cfg->vector);
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msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
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msg.address_lo |= MSI_ADDR_DEST_ID(dest);
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__pci_write_msi_msg(data->msi_desc, &msg);
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return IRQ_SET_MASK_OK_NOCOPY;
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}
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/*
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* IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
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* which implement the MSI or MSI-X Capability Structure.
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*/
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static struct irq_chip msi_chip = {
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.name = "PCI-MSI",
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.irq_unmask = pci_msi_unmask_irq,
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.irq_mask = pci_msi_mask_irq,
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.irq_ack = apic_ack_edge,
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.irq_set_affinity = msi_set_affinity,
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.irq_retrigger = apic_retrigger_irq,
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.flags = IRQCHIP_SKIP_SET_WAKE,
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};
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int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc,
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unsigned int irq_base, unsigned int irq_offset)
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{
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struct irq_chip *chip = &msi_chip;
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struct msi_msg msg;
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unsigned int irq = irq_base + irq_offset;
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int ret;
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ret = msi_compose_msg(dev, irq, &msg, -1);
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if (ret < 0)
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return ret;
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irq_set_msi_desc_off(irq_base, irq_offset, msidesc);
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/*
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* MSI-X message is written per-IRQ, the offset is always 0.
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* MSI message denotes a contiguous group of IRQs, written for 0th IRQ.
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*/
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if (!irq_offset)
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pci_write_msi_msg(irq, &msg);
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setup_remapped_irq(irq, irq_cfg(irq), chip);
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irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
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dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
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return 0;
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}
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int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
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{
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struct msi_desc *msidesc;
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unsigned int irq;
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int node, ret;
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/* Multiple MSI vectors only supported with interrupt remapping */
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if (type == PCI_CAP_ID_MSI && nvec > 1)
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return 1;
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node = dev_to_node(&dev->dev);
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list_for_each_entry(msidesc, &dev->msi_list, list) {
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irq = irq_alloc_hwirq(node);
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if (!irq)
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return -ENOSPC;
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ret = setup_msi_irq(dev, msidesc, irq, 0);
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if (ret < 0) {
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irq_free_hwirq(irq);
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return ret;
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}
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}
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return 0;
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}
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void native_teardown_msi_irq(unsigned int irq)
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{
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irq_free_hwirq(irq);
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}
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#ifdef CONFIG_DMAR_TABLE
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static int
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dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
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bool force)
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{
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struct irq_cfg *cfg = data->chip_data;
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unsigned int dest, irq = data->irq;
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struct msi_msg msg;
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int ret;
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ret = apic_set_affinity(data, mask, &dest);
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if (ret)
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return ret;
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dmar_msi_read(irq, &msg);
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msg.data &= ~MSI_DATA_VECTOR_MASK;
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msg.data |= MSI_DATA_VECTOR(cfg->vector);
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msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
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msg.address_lo |= MSI_ADDR_DEST_ID(dest);
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msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);
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dmar_msi_write(irq, &msg);
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return IRQ_SET_MASK_OK_NOCOPY;
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}
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static struct irq_chip dmar_msi_type = {
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.name = "DMAR_MSI",
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.irq_unmask = dmar_msi_unmask,
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.irq_mask = dmar_msi_mask,
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.irq_ack = apic_ack_edge,
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.irq_set_affinity = dmar_msi_set_affinity,
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.irq_retrigger = apic_retrigger_irq,
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.flags = IRQCHIP_SKIP_SET_WAKE,
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};
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int arch_setup_dmar_msi(unsigned int irq)
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{
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int ret;
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struct msi_msg msg;
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ret = msi_compose_msg(NULL, irq, &msg, -1);
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if (ret < 0)
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return ret;
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dmar_msi_write(irq, &msg);
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irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
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"edge");
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return 0;
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}
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#endif
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#ifdef CONFIG_HPET_TIMER
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static int hpet_msi_set_affinity(struct irq_data *data,
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const struct cpumask *mask, bool force)
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{
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struct irq_cfg *cfg = data->chip_data;
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struct msi_msg msg;
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unsigned int dest;
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int ret;
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ret = apic_set_affinity(data, mask, &dest);
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if (ret)
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return ret;
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hpet_msi_read(data->handler_data, &msg);
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msg.data &= ~MSI_DATA_VECTOR_MASK;
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msg.data |= MSI_DATA_VECTOR(cfg->vector);
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msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
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msg.address_lo |= MSI_ADDR_DEST_ID(dest);
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hpet_msi_write(data->handler_data, &msg);
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return IRQ_SET_MASK_OK_NOCOPY;
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}
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static struct irq_chip hpet_msi_type = {
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.name = "HPET_MSI",
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.irq_unmask = hpet_msi_unmask,
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.irq_mask = hpet_msi_mask,
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.irq_ack = apic_ack_edge,
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.irq_set_affinity = hpet_msi_set_affinity,
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.irq_retrigger = apic_retrigger_irq,
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.flags = IRQCHIP_SKIP_SET_WAKE,
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};
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int default_setup_hpet_msi(unsigned int irq, unsigned int id)
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{
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struct irq_chip *chip = &hpet_msi_type;
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struct msi_msg msg;
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int ret;
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ret = msi_compose_msg(NULL, irq, &msg, id);
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if (ret < 0)
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return ret;
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hpet_msi_write(irq_get_handler_data(irq), &msg);
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irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
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setup_remapped_irq(irq, irq_cfg(irq), chip);
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irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
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return 0;
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}
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#endif
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#endif /* CONFIG_PCI_MSI */
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/*
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* Hypertransport interrupt support
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*/
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@ -0,0 +1,286 @@
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/*
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* Support of MSI, HPET and DMAR interrupts.
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*
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* Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
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* Moved from arch/x86/kernel/apic/io_apic.c.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/dmar.h>
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#include <linux/hpet.h>
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#include <linux/msi.h>
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#include <asm/msidef.h>
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#include <asm/hpet.h>
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#include <asm/hw_irq.h>
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#include <asm/apic.h>
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#include <asm/irq_remapping.h>
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void native_compose_msi_msg(struct pci_dev *pdev,
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unsigned int irq, unsigned int dest,
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struct msi_msg *msg, u8 hpet_id)
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{
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struct irq_cfg *cfg = irq_cfg(irq);
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msg->address_hi = MSI_ADDR_BASE_HI;
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if (x2apic_enabled())
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msg->address_hi |= MSI_ADDR_EXT_DEST_ID(dest);
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msg->address_lo =
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MSI_ADDR_BASE_LO |
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((apic->irq_dest_mode == 0) ?
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MSI_ADDR_DEST_MODE_PHYSICAL :
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MSI_ADDR_DEST_MODE_LOGICAL) |
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((apic->irq_delivery_mode != dest_LowestPrio) ?
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MSI_ADDR_REDIRECTION_CPU :
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MSI_ADDR_REDIRECTION_LOWPRI) |
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MSI_ADDR_DEST_ID(dest);
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msg->data =
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MSI_DATA_TRIGGER_EDGE |
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MSI_DATA_LEVEL_ASSERT |
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((apic->irq_delivery_mode != dest_LowestPrio) ?
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MSI_DATA_DELIVERY_FIXED :
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MSI_DATA_DELIVERY_LOWPRI) |
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MSI_DATA_VECTOR(cfg->vector);
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}
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static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
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struct msi_msg *msg, u8 hpet_id)
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{
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struct irq_cfg *cfg;
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int err;
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unsigned dest;
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if (disable_apic)
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return -ENXIO;
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cfg = irq_cfg(irq);
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err = assign_irq_vector(irq, cfg, apic->target_cpus());
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if (err)
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return err;
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err = apic->cpu_mask_to_apicid_and(cfg->domain,
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apic->target_cpus(), &dest);
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if (err)
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return err;
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x86_msi.compose_msi_msg(pdev, irq, dest, msg, hpet_id);
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return 0;
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}
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static int
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msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
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{
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struct irq_cfg *cfg = data->chip_data;
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struct msi_msg msg;
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unsigned int dest;
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int ret;
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||||
|
||||
ret = apic_set_affinity(data, mask, &dest);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
__get_cached_msi_msg(data->msi_desc, &msg);
|
||||
|
||||
msg.data &= ~MSI_DATA_VECTOR_MASK;
|
||||
msg.data |= MSI_DATA_VECTOR(cfg->vector);
|
||||
msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
|
||||
msg.address_lo |= MSI_ADDR_DEST_ID(dest);
|
||||
|
||||
__pci_write_msi_msg(data->msi_desc, &msg);
|
||||
|
||||
return IRQ_SET_MASK_OK_NOCOPY;
|
||||
}
|
||||
|
||||
/*
|
||||
* IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
|
||||
* which implement the MSI or MSI-X Capability Structure.
|
||||
*/
|
||||
static struct irq_chip msi_chip = {
|
||||
.name = "PCI-MSI",
|
||||
.irq_unmask = pci_msi_unmask_irq,
|
||||
.irq_mask = pci_msi_mask_irq,
|
||||
.irq_ack = apic_ack_edge,
|
||||
.irq_set_affinity = msi_set_affinity,
|
||||
.irq_retrigger = apic_retrigger_irq,
|
||||
.flags = IRQCHIP_SKIP_SET_WAKE,
|
||||
};
|
||||
|
||||
int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc,
|
||||
unsigned int irq_base, unsigned int irq_offset)
|
||||
{
|
||||
struct irq_chip *chip = &msi_chip;
|
||||
struct msi_msg msg;
|
||||
unsigned int irq = irq_base + irq_offset;
|
||||
int ret;
|
||||
|
||||
ret = msi_compose_msg(dev, irq, &msg, -1);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
irq_set_msi_desc_off(irq_base, irq_offset, msidesc);
|
||||
|
||||
/*
|
||||
* MSI-X message is written per-IRQ, the offset is always 0.
|
||||
* MSI message denotes a contiguous group of IRQs, written for 0th IRQ.
|
||||
*/
|
||||
if (!irq_offset)
|
||||
pci_write_msi_msg(irq, &msg);
|
||||
|
||||
setup_remapped_irq(irq, irq_cfg(irq), chip);
|
||||
|
||||
irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
|
||||
|
||||
dev_dbg(&dev->dev, "irq %d for MSI/MSI-X\n", irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
|
||||
{
|
||||
struct msi_desc *msidesc;
|
||||
unsigned int irq;
|
||||
int node, ret;
|
||||
|
||||
/* Multiple MSI vectors only supported with interrupt remapping */
|
||||
if (type == PCI_CAP_ID_MSI && nvec > 1)
|
||||
return 1;
|
||||
|
||||
node = dev_to_node(&dev->dev);
|
||||
|
||||
list_for_each_entry(msidesc, &dev->msi_list, list) {
|
||||
irq = irq_alloc_hwirq(node);
|
||||
if (!irq)
|
||||
return -ENOSPC;
|
||||
|
||||
ret = setup_msi_irq(dev, msidesc, irq, 0);
|
||||
if (ret < 0) {
|
||||
irq_free_hwirq(irq);
|
||||
return ret;
|
||||
}
|
||||
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void native_teardown_msi_irq(unsigned int irq)
|
||||
{
|
||||
irq_free_hwirq(irq);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DMAR_TABLE
|
||||
static int
|
||||
dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
|
||||
bool force)
|
||||
{
|
||||
struct irq_cfg *cfg = data->chip_data;
|
||||
unsigned int dest, irq = data->irq;
|
||||
struct msi_msg msg;
|
||||
int ret;
|
||||
|
||||
ret = apic_set_affinity(data, mask, &dest);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
dmar_msi_read(irq, &msg);
|
||||
|
||||
msg.data &= ~MSI_DATA_VECTOR_MASK;
|
||||
msg.data |= MSI_DATA_VECTOR(cfg->vector);
|
||||
msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
|
||||
msg.address_lo |= MSI_ADDR_DEST_ID(dest);
|
||||
msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);
|
||||
|
||||
dmar_msi_write(irq, &msg);
|
||||
|
||||
return IRQ_SET_MASK_OK_NOCOPY;
|
||||
}
|
||||
|
||||
static struct irq_chip dmar_msi_type = {
|
||||
.name = "DMAR_MSI",
|
||||
.irq_unmask = dmar_msi_unmask,
|
||||
.irq_mask = dmar_msi_mask,
|
||||
.irq_ack = apic_ack_edge,
|
||||
.irq_set_affinity = dmar_msi_set_affinity,
|
||||
.irq_retrigger = apic_retrigger_irq,
|
||||
.flags = IRQCHIP_SKIP_SET_WAKE,
|
||||
};
|
||||
|
||||
int arch_setup_dmar_msi(unsigned int irq)
|
||||
{
|
||||
int ret;
|
||||
struct msi_msg msg;
|
||||
|
||||
ret = msi_compose_msg(NULL, irq, &msg, -1);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
dmar_msi_write(irq, &msg);
|
||||
irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
|
||||
"edge");
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* MSI message composition
|
||||
*/
|
||||
#ifdef CONFIG_HPET_TIMER
|
||||
|
||||
static int hpet_msi_set_affinity(struct irq_data *data,
|
||||
const struct cpumask *mask, bool force)
|
||||
{
|
||||
struct irq_cfg *cfg = data->chip_data;
|
||||
struct msi_msg msg;
|
||||
unsigned int dest;
|
||||
int ret;
|
||||
|
||||
ret = apic_set_affinity(data, mask, &dest);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
hpet_msi_read(data->handler_data, &msg);
|
||||
|
||||
msg.data &= ~MSI_DATA_VECTOR_MASK;
|
||||
msg.data |= MSI_DATA_VECTOR(cfg->vector);
|
||||
msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
|
||||
msg.address_lo |= MSI_ADDR_DEST_ID(dest);
|
||||
|
||||
hpet_msi_write(data->handler_data, &msg);
|
||||
|
||||
return IRQ_SET_MASK_OK_NOCOPY;
|
||||
}
|
||||
|
||||
static struct irq_chip hpet_msi_type = {
|
||||
.name = "HPET_MSI",
|
||||
.irq_unmask = hpet_msi_unmask,
|
||||
.irq_mask = hpet_msi_mask,
|
||||
.irq_ack = apic_ack_edge,
|
||||
.irq_set_affinity = hpet_msi_set_affinity,
|
||||
.irq_retrigger = apic_retrigger_irq,
|
||||
.flags = IRQCHIP_SKIP_SET_WAKE,
|
||||
};
|
||||
|
||||
int default_setup_hpet_msi(unsigned int irq, unsigned int id)
|
||||
{
|
||||
struct irq_chip *chip = &hpet_msi_type;
|
||||
struct msi_msg msg;
|
||||
int ret;
|
||||
|
||||
ret = msi_compose_msg(NULL, irq, &msg, id);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
hpet_msi_write(irq_get_handler_data(irq), &msg);
|
||||
irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
|
||||
setup_remapped_irq(irq, irq_cfg(irq), chip);
|
||||
|
||||
irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
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