[PATCH] ppc32: refactor FPU exception handling
Moved common FPU exception handling code out of head.S so it can be used by several of the sub-architectures that might of a full PowerPC FPU. Also, uses new CONFIG_PPC_FPU define to fix alignment exception handling for floating point load/store instructions to only occur if we have a hardware FPU. Signed-off-by: Jason McMullan <jason.mcmullan@timesys.com> Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Paul Mackerras
Linus Torvalds
Родитель
f1c55dea0b
Коммит
443a848cd3
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@ -53,6 +53,7 @@ choice
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config 6xx
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bool "6xx/7xx/74xx/52xx/82xx/83xx"
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select PPC_FPU
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help
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There are four types of PowerPC chips supported. The more common
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types (601, 603, 604, 740, 750, 7400), the Motorola embedded
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@ -86,6 +87,9 @@ config E500
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endchoice
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config PPC_FPU
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bool
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config BOOKE
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bool
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depends on E500
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@ -53,6 +53,7 @@ head-$(CONFIG_FSL_BOOKE) := arch/ppc/kernel/head_fsl_booke.o
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head-$(CONFIG_6xx) += arch/ppc/kernel/idle_6xx.o
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head-$(CONFIG_POWER4) += arch/ppc/kernel/idle_power4.o
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head-$(CONFIG_PPC_FPU) += arch/ppc/kernel/fpu.o
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core-y += arch/ppc/kernel/ arch/ppc/platforms/ \
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arch/ppc/mm/ arch/ppc/lib/ arch/ppc/syslib/
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@ -9,6 +9,7 @@ extra-$(CONFIG_FSL_BOOKE) := head_fsl_booke.o
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extra-$(CONFIG_8xx) := head_8xx.o
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extra-$(CONFIG_6xx) += idle_6xx.o
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extra-$(CONFIG_POWER4) += idle_power4.o
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extra-$(CONFIG_PPC_FPU) += fpu.o
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extra-y += vmlinux.lds
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obj-y := entry.o traps.o irq.o idle.o time.o misc.o \
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@ -368,16 +368,24 @@ fix_alignment(struct pt_regs *regs)
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/* Single-precision FP load and store require conversions... */
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case LD+F+S:
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#ifdef CONFIG_PPC_FPU
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preempt_disable();
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enable_kernel_fp();
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cvt_fd(&data.f, &data.d, ¤t->thread.fpscr);
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preempt_enable();
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#else
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return 0;
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#endif
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break;
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case ST+F+S:
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#ifdef CONFIG_PPC_FPU
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preempt_disable();
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enable_kernel_fp();
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cvt_df(&data.d, &data.f, ¤t->thread.fpscr);
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preempt_enable();
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#else
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return 0;
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#endif
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break;
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}
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@ -563,6 +563,65 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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addi r1,r1,INT_FRAME_SIZE
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blr
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.globl fast_exception_return
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fast_exception_return:
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#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
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andi. r10,r9,MSR_RI /* check for recoverable interrupt */
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beq 1f /* if not, we've got problems */
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#endif
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2: REST_4GPRS(3, r11)
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lwz r10,_CCR(r11)
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REST_GPR(1, r11)
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mtcr r10
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lwz r10,_LINK(r11)
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mtlr r10
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REST_GPR(10, r11)
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mtspr SPRN_SRR1,r9
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mtspr SPRN_SRR0,r12
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REST_GPR(9, r11)
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REST_GPR(12, r11)
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lwz r11,GPR11(r11)
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SYNC
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RFI
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#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
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/* check if the exception happened in a restartable section */
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1: lis r3,exc_exit_restart_end@ha
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addi r3,r3,exc_exit_restart_end@l
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cmplw r12,r3
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bge 3f
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lis r4,exc_exit_restart@ha
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addi r4,r4,exc_exit_restart@l
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cmplw r12,r4
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blt 3f
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lis r3,fee_restarts@ha
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tophys(r3,r3)
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lwz r5,fee_restarts@l(r3)
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addi r5,r5,1
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stw r5,fee_restarts@l(r3)
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mr r12,r4 /* restart at exc_exit_restart */
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b 2b
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.comm fee_restarts,4
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/* aargh, a nonrecoverable interrupt, panic */
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/* aargh, we don't know which trap this is */
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/* but the 601 doesn't implement the RI bit, so assume it's OK */
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3:
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BEGIN_FTR_SECTION
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b 2b
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END_FTR_SECTION_IFSET(CPU_FTR_601)
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li r10,-1
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stw r10,TRAP(r11)
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addi r3,r1,STACK_FRAME_OVERHEAD
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lis r10,MSR_KERNEL@h
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ori r10,r10,MSR_KERNEL@l
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bl transfer_to_handler_full
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.long nonrecoverable_exception
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.long ret_from_except
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#endif
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.globl sigreturn_exit
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sigreturn_exit:
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subi r1,r3,STACK_FRAME_OVERHEAD
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@ -0,0 +1,133 @@
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/*
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* FPU support code, moved here from head.S so that it can be used
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* by chips which use other head-whatever.S files.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/config.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm/pgtable.h>
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#include <asm/cputable.h>
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#include <asm/cache.h>
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/offsets.h>
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/*
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* This task wants to use the FPU now.
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* On UP, disable FP for the task which had the FPU previously,
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* and save its floating-point registers in its thread_struct.
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* Load up this task's FP registers from its thread_struct,
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* enable the FPU for the current task and return to the task.
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*/
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.globl load_up_fpu
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load_up_fpu:
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mfmsr r5
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ori r5,r5,MSR_FP
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#ifdef CONFIG_PPC64BRIDGE
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clrldi r5,r5,1 /* turn off 64-bit mode */
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#endif /* CONFIG_PPC64BRIDGE */
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SYNC
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MTMSRD(r5) /* enable use of fpu now */
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isync
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/*
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* For SMP, we don't do lazy FPU switching because it just gets too
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* horrendously complex, especially when a task switches from one CPU
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* to another. Instead we call giveup_fpu in switch_to.
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*/
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#ifndef CONFIG_SMP
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tophys(r6,0) /* get __pa constant */
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addis r3,r6,last_task_used_math@ha
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lwz r4,last_task_used_math@l(r3)
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cmpwi 0,r4,0
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beq 1f
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add r4,r4,r6
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addi r4,r4,THREAD /* want last_task_used_math->thread */
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SAVE_32FPRS(0, r4)
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mffs fr0
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stfd fr0,THREAD_FPSCR-4(r4)
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lwz r5,PT_REGS(r4)
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add r5,r5,r6
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lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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li r10,MSR_FP|MSR_FE0|MSR_FE1
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andc r4,r4,r10 /* disable FP for previous task */
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stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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1:
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#endif /* CONFIG_SMP */
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/* enable use of FP after return */
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mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
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lwz r4,THREAD_FPEXC_MODE(r5)
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ori r9,r9,MSR_FP /* enable FP for current */
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or r9,r9,r4
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lfd fr0,THREAD_FPSCR-4(r5)
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mtfsf 0xff,fr0
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REST_32FPRS(0, r5)
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#ifndef CONFIG_SMP
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subi r4,r5,THREAD
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sub r4,r4,r6
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stw r4,last_task_used_math@l(r3)
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#endif /* CONFIG_SMP */
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/* restore registers and return */
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/* we haven't used ctr or xer or lr */
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b fast_exception_return
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/*
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* FP unavailable trap from kernel - print a message, but let
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* the task use FP in the kernel until it returns to user mode.
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*/
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.globl KernelFP
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KernelFP:
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lwz r3,_MSR(r1)
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ori r3,r3,MSR_FP
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stw r3,_MSR(r1) /* enable use of FP after return */
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lis r3,86f@h
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ori r3,r3,86f@l
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mr r4,r2 /* current */
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lwz r5,_NIP(r1)
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bl printk
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b ret_from_except
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86: .string "floating point used in kernel (task=%p, pc=%x)\n"
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.align 4,0
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/*
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* giveup_fpu(tsk)
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* Disable FP for the task given as the argument,
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* and save the floating-point registers in its thread_struct.
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* Enables the FPU for use in the kernel on return.
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*/
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.globl giveup_fpu
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giveup_fpu:
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mfmsr r5
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ori r5,r5,MSR_FP
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SYNC_601
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ISYNC_601
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MTMSRD(r5) /* enable use of fpu now */
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SYNC_601
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isync
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cmpwi 0,r3,0
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beqlr- /* if no previous owner, done */
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addi r3,r3,THREAD /* want THREAD of task */
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lwz r5,PT_REGS(r3)
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cmpwi 0,r5,0
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SAVE_32FPRS(0, r3)
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mffs fr0
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stfd fr0,THREAD_FPSCR-4(r3)
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beq 1f
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lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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li r3,MSR_FP|MSR_FE0|MSR_FE1
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andc r4,r4,r3 /* disable FP for previous task */
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stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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1:
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#ifndef CONFIG_SMP
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li r5,0
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lis r4,last_task_used_math@ha
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stw r5,last_task_used_math@l(r4)
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#endif /* CONFIG_SMP */
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blr
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@ -775,133 +775,6 @@ InstructionSegment:
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EXC_XFER_STD(0x480, UnknownException)
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#endif /* CONFIG_PPC64BRIDGE */
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/*
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* This task wants to use the FPU now.
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* On UP, disable FP for the task which had the FPU previously,
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* and save its floating-point registers in its thread_struct.
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* Load up this task's FP registers from its thread_struct,
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* enable the FPU for the current task and return to the task.
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*/
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load_up_fpu:
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mfmsr r5
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ori r5,r5,MSR_FP
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#ifdef CONFIG_PPC64BRIDGE
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clrldi r5,r5,1 /* turn off 64-bit mode */
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#endif /* CONFIG_PPC64BRIDGE */
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SYNC
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MTMSRD(r5) /* enable use of fpu now */
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isync
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/*
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* For SMP, we don't do lazy FPU switching because it just gets too
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* horrendously complex, especially when a task switches from one CPU
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* to another. Instead we call giveup_fpu in switch_to.
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*/
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#ifndef CONFIG_SMP
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tophys(r6,0) /* get __pa constant */
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addis r3,r6,last_task_used_math@ha
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lwz r4,last_task_used_math@l(r3)
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cmpwi 0,r4,0
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beq 1f
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add r4,r4,r6
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addi r4,r4,THREAD /* want last_task_used_math->thread */
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SAVE_32FPRS(0, r4)
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mffs fr0
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stfd fr0,THREAD_FPSCR-4(r4)
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lwz r5,PT_REGS(r4)
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add r5,r5,r6
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lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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li r10,MSR_FP|MSR_FE0|MSR_FE1
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andc r4,r4,r10 /* disable FP for previous task */
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stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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1:
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#endif /* CONFIG_SMP */
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/* enable use of FP after return */
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mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
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lwz r4,THREAD_FPEXC_MODE(r5)
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ori r9,r9,MSR_FP /* enable FP for current */
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or r9,r9,r4
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lfd fr0,THREAD_FPSCR-4(r5)
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mtfsf 0xff,fr0
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REST_32FPRS(0, r5)
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#ifndef CONFIG_SMP
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subi r4,r5,THREAD
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sub r4,r4,r6
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stw r4,last_task_used_math@l(r3)
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#endif /* CONFIG_SMP */
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/* restore registers and return */
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/* we haven't used ctr or xer or lr */
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/* fall through to fast_exception_return */
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.globl fast_exception_return
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fast_exception_return:
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andi. r10,r9,MSR_RI /* check for recoverable interrupt */
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beq 1f /* if not, we've got problems */
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2: REST_4GPRS(3, r11)
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lwz r10,_CCR(r11)
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REST_GPR(1, r11)
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mtcr r10
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lwz r10,_LINK(r11)
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mtlr r10
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REST_GPR(10, r11)
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mtspr SPRN_SRR1,r9
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mtspr SPRN_SRR0,r12
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REST_GPR(9, r11)
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REST_GPR(12, r11)
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lwz r11,GPR11(r11)
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SYNC
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RFI
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/* check if the exception happened in a restartable section */
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1: lis r3,exc_exit_restart_end@ha
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addi r3,r3,exc_exit_restart_end@l
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cmplw r12,r3
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bge 3f
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lis r4,exc_exit_restart@ha
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addi r4,r4,exc_exit_restart@l
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cmplw r12,r4
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blt 3f
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lis r3,fee_restarts@ha
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tophys(r3,r3)
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lwz r5,fee_restarts@l(r3)
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addi r5,r5,1
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stw r5,fee_restarts@l(r3)
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mr r12,r4 /* restart at exc_exit_restart */
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b 2b
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.comm fee_restarts,4
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/* aargh, a nonrecoverable interrupt, panic */
|
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/* aargh, we don't know which trap this is */
|
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/* but the 601 doesn't implement the RI bit, so assume it's OK */
|
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3:
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BEGIN_FTR_SECTION
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b 2b
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END_FTR_SECTION_IFSET(CPU_FTR_601)
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li r10,-1
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stw r10,TRAP(r11)
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addi r3,r1,STACK_FRAME_OVERHEAD
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li r10,MSR_KERNEL
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bl transfer_to_handler_full
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.long nonrecoverable_exception
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.long ret_from_except
|
||||
|
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/*
|
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* FP unavailable trap from kernel - print a message, but let
|
||||
* the task use FP in the kernel until it returns to user mode.
|
||||
*/
|
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KernelFP:
|
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lwz r3,_MSR(r1)
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ori r3,r3,MSR_FP
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stw r3,_MSR(r1) /* enable use of FP after return */
|
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lis r3,86f@h
|
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ori r3,r3,86f@l
|
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mr r4,r2 /* current */
|
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lwz r5,_NIP(r1)
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bl printk
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b ret_from_except
|
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86: .string "floating point used in kernel (task=%p, pc=%x)\n"
|
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.align 4,0
|
||||
|
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#ifdef CONFIG_ALTIVEC
|
||||
/* Note that the AltiVec support is closely modeled after the FP
|
||||
* support. Changes to one are likely to be applicable to the
|
||||
|
|
@ -1015,42 +888,6 @@ giveup_altivec:
|
|||
blr
|
||||
#endif /* CONFIG_ALTIVEC */
|
||||
|
||||
/*
|
||||
* giveup_fpu(tsk)
|
||||
* Disable FP for the task given as the argument,
|
||||
* and save the floating-point registers in its thread_struct.
|
||||
* Enables the FPU for use in the kernel on return.
|
||||
*/
|
||||
.globl giveup_fpu
|
||||
giveup_fpu:
|
||||
mfmsr r5
|
||||
ori r5,r5,MSR_FP
|
||||
SYNC_601
|
||||
ISYNC_601
|
||||
MTMSRD(r5) /* enable use of fpu now */
|
||||
SYNC_601
|
||||
isync
|
||||
cmpwi 0,r3,0
|
||||
beqlr- /* if no previous owner, done */
|
||||
addi r3,r3,THREAD /* want THREAD of task */
|
||||
lwz r5,PT_REGS(r3)
|
||||
cmpwi 0,r5,0
|
||||
SAVE_32FPRS(0, r3)
|
||||
mffs fr0
|
||||
stfd fr0,THREAD_FPSCR-4(r3)
|
||||
beq 1f
|
||||
lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
|
||||
li r3,MSR_FP|MSR_FE0|MSR_FE1
|
||||
andc r4,r4,r3 /* disable FP for previous task */
|
||||
stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
|
||||
1:
|
||||
#ifndef CONFIG_SMP
|
||||
li r5,0
|
||||
lis r4,last_task_used_math@ha
|
||||
stw r5,last_task_used_math@l(r4)
|
||||
#endif /* CONFIG_SMP */
|
||||
blr
|
||||
|
||||
/*
|
||||
* This code is jumped to from the startup code to copy
|
||||
* the kernel image to physical address 0.
|
||||
|
|
|
|||
|
|
@ -426,7 +426,11 @@ interrupt_base:
|
|||
PROGRAM_EXCEPTION
|
||||
|
||||
/* Floating Point Unavailable Interrupt */
|
||||
#ifdef CONFIG_PPC_FPU
|
||||
FP_UNAVAILABLE_EXCEPTION
|
||||
#else
|
||||
EXCEPTION(0x2010, FloatingPointUnavailable, UnknownException, EXC_XFER_EE)
|
||||
#endif
|
||||
|
||||
/* System Call Interrupt */
|
||||
START_EXCEPTION(SystemCall)
|
||||
|
|
@ -686,8 +690,10 @@ _GLOBAL(giveup_altivec)
|
|||
*
|
||||
* The 44x core does not have an FPU.
|
||||
*/
|
||||
#ifndef CONFIG_PPC_FPU
|
||||
_GLOBAL(giveup_fpu)
|
||||
blr
|
||||
#endif
|
||||
|
||||
/*
|
||||
* extern void abort(void)
|
||||
|
|
|
|||
|
|
@ -337,4 +337,11 @@ label:
|
|||
addi r3,r1,STACK_FRAME_OVERHEAD; \
|
||||
EXC_XFER_LITE(0x0900, timer_interrupt)
|
||||
|
||||
#define FP_UNAVAILABLE_EXCEPTION \
|
||||
START_EXCEPTION(FloatingPointUnavailable) \
|
||||
NORMAL_EXCEPTION_PROLOG; \
|
||||
bne load_up_fpu; /* if from user, just load it up */ \
|
||||
addi r3,r1,STACK_FRAME_OVERHEAD; \
|
||||
EXC_XFER_EE_LITE(0x800, KernelFP)
|
||||
|
||||
#endif /* __HEAD_BOOKE_H__ */
|
||||
|
|
|
|||
|
|
@ -504,7 +504,11 @@ interrupt_base:
|
|||
PROGRAM_EXCEPTION
|
||||
|
||||
/* Floating Point Unavailable Interrupt */
|
||||
#ifdef CONFIG_PPC_FPU
|
||||
FP_UNAVAILABLE_EXCEPTION
|
||||
#else
|
||||
EXCEPTION(0x0800, FloatingPointUnavailable, UnknownException, EXC_XFER_EE)
|
||||
#endif
|
||||
|
||||
/* System Call Interrupt */
|
||||
START_EXCEPTION(SystemCall)
|
||||
|
|
@ -916,10 +920,12 @@ _GLOBAL(giveup_spe)
|
|||
/*
|
||||
* extern void giveup_fpu(struct task_struct *prev)
|
||||
*
|
||||
* The e500 core does not have an FPU.
|
||||
* Not all FSL Book-E cores have an FPU
|
||||
*/
|
||||
#ifndef CONFIG_PPC_FPU
|
||||
_GLOBAL(giveup_fpu)
|
||||
blr
|
||||
#endif
|
||||
|
||||
/*
|
||||
* extern void abort(void)
|
||||
|
|
|
|||
|
|
@ -1096,17 +1096,7 @@ _GLOBAL(_get_SP)
|
|||
* and exceptions as if the cpu had performed the load or store.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_4xx) || defined(CONFIG_E500)
|
||||
_GLOBAL(cvt_fd)
|
||||
lfs 0,0(r3)
|
||||
stfd 0,0(r4)
|
||||
blr
|
||||
|
||||
_GLOBAL(cvt_df)
|
||||
lfd 0,0(r3)
|
||||
stfs 0,0(r4)
|
||||
blr
|
||||
#else
|
||||
#ifdef CONFIG_PPC_FPU
|
||||
_GLOBAL(cvt_fd)
|
||||
lfd 0,-4(r5) /* load up fpscr value */
|
||||
mtfsf 0xff,0
|
||||
|
|
|
|||
|
|
@ -176,7 +176,7 @@ static inline int check_io_access(struct pt_regs *regs)
|
|||
#else
|
||||
#define get_mc_reason(regs) (mfspr(SPRN_MCSR))
|
||||
#endif
|
||||
#define REASON_FP 0
|
||||
#define REASON_FP ESR_FP
|
||||
#define REASON_ILLEGAL ESR_PIL
|
||||
#define REASON_PRIVILEGED ESR_PPR
|
||||
#define REASON_TRAP ESR_PTR
|
||||
|
|
|
|||
|
|
@ -305,6 +305,7 @@ do { \
|
|||
#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
|
||||
#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
|
||||
#define ESR_PTR 0x02000000 /* Program Exception - Trap */
|
||||
#define ESR_FP 0x01000000 /* Floating Point Operation */
|
||||
#define ESR_DST 0x00800000 /* Storage Exception - Data miss */
|
||||
#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
|
||||
#define ESR_ST 0x00800000 /* Store Operation */
|
||||
|
|
|
|||
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