Merge branch 'bnx2x'
Yuval Mintz says: ==================== bnx2x: Bug fixes patch series This patch series contains fixes for various flows - several SR-IOV issues are fixed, ethtool callbacks (coalescing and register dump) are corrected, null pointer dereference on error flows is prevented, etc. Changes from V1 --------------- - Patch 2 "bnx2x: Prevent an illegal pointer dereference during panic" is revised, with improved handling of edge cases. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Коммит
4440c6f7d5
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@ -1197,8 +1197,9 @@ union cdu_context {
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/* TM (timers) host DB constants */
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#define TM_ILT_PAGE_SZ_HW 0
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#define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
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/* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
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#define TM_CONN_NUM 1024
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#define TM_CONN_NUM (BNX2X_FIRST_VF_CID + \
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BNX2X_VF_CIDS + \
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CNIC_ISCSI_CID_MAX)
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#define TM_ILT_SZ (8 * TM_CONN_NUM)
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#define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
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@ -1527,7 +1528,6 @@ struct bnx2x {
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#define PCI_32BIT_FLAG (1 << 1)
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#define ONE_PORT_FLAG (1 << 2)
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#define NO_WOL_FLAG (1 << 3)
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#define USING_DAC_FLAG (1 << 4)
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#define USING_MSIX_FLAG (1 << 5)
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#define USING_MSI_FLAG (1 << 6)
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#define DISABLE_MSI_FLAG (1 << 7)
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@ -1621,7 +1621,7 @@ struct bnx2x {
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u16 rx_ticks_int;
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u16 rx_ticks;
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/* Maximal coalescing timeout in us */
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#define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
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#define BNX2X_MAX_COALESCE_TOUT (0xff*BNX2X_BTR)
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u32 lin_cnt;
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@ -2072,7 +2072,8 @@ u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
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void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
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u8 src_type, u8 dst_type);
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int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae);
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int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
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u32 *comp);
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/* FLR related routines */
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u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp);
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@ -2498,4 +2499,8 @@ enum bnx2x_pci_bus_speed {
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};
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void bnx2x_set_local_cmng(struct bnx2x *bp);
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#define MCPR_SCRATCH_BASE(bp) \
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(CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
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#endif /* bnx2x.h */
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@ -891,17 +891,8 @@ static void bnx2x_get_regs(struct net_device *dev,
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* will re-enable parity attentions right after the dump.
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*/
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/* Disable parity on path 0 */
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bnx2x_pretend_func(bp, 0);
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bnx2x_disable_blocks_parity(bp);
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/* Disable parity on path 1 */
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bnx2x_pretend_func(bp, 1);
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bnx2x_disable_blocks_parity(bp);
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/* Return to current function */
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bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
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dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
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dump_hdr.preset = DUMP_ALL_PRESETS;
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dump_hdr.version = BNX2X_DUMP_VERSION;
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@ -928,18 +919,9 @@ static void bnx2x_get_regs(struct net_device *dev,
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/* Actually read the registers */
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__bnx2x_get_regs(bp, p);
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/* Re-enable parity attentions on path 0 */
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bnx2x_pretend_func(bp, 0);
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/* Re-enable parity attentions */
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bnx2x_clear_blocks_parity(bp);
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bnx2x_enable_blocks_parity(bp);
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/* Re-enable parity attentions on path 1 */
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bnx2x_pretend_func(bp, 1);
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bnx2x_clear_blocks_parity(bp);
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bnx2x_enable_blocks_parity(bp);
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/* Return to current function */
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bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
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}
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static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
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@ -993,17 +975,8 @@ static int bnx2x_get_dump_data(struct net_device *dev,
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* will re-enable parity attentions right after the dump.
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*/
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/* Disable parity on path 0 */
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bnx2x_pretend_func(bp, 0);
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bnx2x_disable_blocks_parity(bp);
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/* Disable parity on path 1 */
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bnx2x_pretend_func(bp, 1);
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bnx2x_disable_blocks_parity(bp);
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/* Return to current function */
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bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
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dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
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dump_hdr.preset = bp->dump_preset_idx;
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dump_hdr.version = BNX2X_DUMP_VERSION;
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@ -1032,19 +1005,10 @@ static int bnx2x_get_dump_data(struct net_device *dev,
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/* Actually read the registers */
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__bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
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/* Re-enable parity attentions on path 0 */
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bnx2x_pretend_func(bp, 0);
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/* Re-enable parity attentions */
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bnx2x_clear_blocks_parity(bp);
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bnx2x_enable_blocks_parity(bp);
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/* Re-enable parity attentions on path 1 */
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bnx2x_pretend_func(bp, 1);
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bnx2x_clear_blocks_parity(bp);
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bnx2x_enable_blocks_parity(bp);
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/* Return to current function */
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bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
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return 0;
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}
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@ -640,23 +640,35 @@ static const struct {
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* [30] MCP Latched ump_tx_parity
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* [31] MCP Latched scpad_parity
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*/
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#define MISC_AEU_ENABLE_MCP_PRTY_BITS \
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#define MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS \
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(AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY)
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#define MISC_AEU_ENABLE_MCP_PRTY_BITS \
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(MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS | \
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
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/* Below registers control the MCP parity attention output. When
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* MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are
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* enabled, when cleared - disabled.
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*/
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static const u32 mcp_attn_ctl_regs[] = {
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MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
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MISC_REG_AEU_ENABLE4_NIG_0,
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MISC_REG_AEU_ENABLE4_PXP_0,
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MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
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MISC_REG_AEU_ENABLE4_NIG_1,
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MISC_REG_AEU_ENABLE4_PXP_1
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static const struct {
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u32 addr;
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u32 bits;
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} mcp_attn_ctl_regs[] = {
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{ MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
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MISC_AEU_ENABLE_MCP_PRTY_BITS },
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{ MISC_REG_AEU_ENABLE4_NIG_0,
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MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
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{ MISC_REG_AEU_ENABLE4_PXP_0,
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MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
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{ MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
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MISC_AEU_ENABLE_MCP_PRTY_BITS },
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{ MISC_REG_AEU_ENABLE4_NIG_1,
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MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
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{ MISC_REG_AEU_ENABLE4_PXP_1,
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MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS }
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};
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static inline void bnx2x_set_mcp_parity(struct bnx2x *bp, u8 enable)
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@ -665,14 +677,14 @@ static inline void bnx2x_set_mcp_parity(struct bnx2x *bp, u8 enable)
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u32 reg_val;
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for (i = 0; i < ARRAY_SIZE(mcp_attn_ctl_regs); i++) {
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reg_val = REG_RD(bp, mcp_attn_ctl_regs[i]);
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reg_val = REG_RD(bp, mcp_attn_ctl_regs[i].addr);
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if (enable)
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reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS;
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reg_val |= mcp_attn_ctl_regs[i].bits;
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else
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reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS;
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reg_val &= ~mcp_attn_ctl_regs[i].bits;
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REG_WR(bp, mcp_attn_ctl_regs[i], reg_val);
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REG_WR(bp, mcp_attn_ctl_regs[i].addr, reg_val);
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}
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}
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@ -503,9 +503,9 @@ void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
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}
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/* issue a dmae command over the init-channel and wait for completion */
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int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae)
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int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
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u32 *comp)
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{
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u32 *wb_comp = bnx2x_sp(bp, wb_comp);
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int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
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int rc = 0;
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@ -518,14 +518,14 @@ int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae)
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spin_lock_bh(&bp->dmae_lock);
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/* reset completion */
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*wb_comp = 0;
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*comp = 0;
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/* post the command on the channel used for initializations */
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bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
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/* wait for completion */
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udelay(5);
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while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
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while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
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if (!cnt ||
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(bp->recovery_state != BNX2X_RECOVERY_DONE &&
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@ -537,7 +537,7 @@ int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae)
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cnt--;
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udelay(50);
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}
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if (*wb_comp & DMAE_PCI_ERR_FLAG) {
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if (*comp & DMAE_PCI_ERR_FLAG) {
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BNX2X_ERR("DMAE PCI error!\n");
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rc = DMAE_PCI_ERROR;
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}
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@ -574,7 +574,7 @@ void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
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dmae.len = len32;
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/* issue the command and wait for completion */
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rc = bnx2x_issue_dmae_with_comp(bp, &dmae);
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rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
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if (rc) {
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BNX2X_ERR("DMAE returned failure %d\n", rc);
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bnx2x_panic();
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@ -611,7 +611,7 @@ void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
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dmae.len = len32;
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/* issue the command and wait for completion */
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rc = bnx2x_issue_dmae_with_comp(bp, &dmae);
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rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
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if (rc) {
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BNX2X_ERR("DMAE returned failure %d\n", rc);
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bnx2x_panic();
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@ -751,6 +751,10 @@ static int bnx2x_mc_assert(struct bnx2x *bp)
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return rc;
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}
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#define MCPR_TRACE_BUFFER_SIZE (0x800)
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#define SCRATCH_BUFFER_SIZE(bp) \
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(CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
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void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
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{
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u32 addr, val;
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@ -775,7 +779,17 @@ void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
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trace_shmem_base = bp->common.shmem_base;
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else
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trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
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addr = trace_shmem_base - 0x800;
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/* sanity */
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if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
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trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
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SCRATCH_BUFFER_SIZE(bp)) {
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BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
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trace_shmem_base);
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return;
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}
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addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
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/* validate TRCB signature */
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mark = REG_RD(bp, addr);
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@ -787,14 +801,17 @@ void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
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/* read cyclic buffer pointer */
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addr += 4;
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mark = REG_RD(bp, addr);
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mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
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+ ((mark + 0x3) & ~0x3) - 0x08000000;
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mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
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if (mark >= trace_shmem_base || mark < addr + 4) {
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BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
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return;
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}
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printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
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printk("%s", lvl);
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/* dump buffer after the mark */
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for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
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for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
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for (word = 0; word < 8; word++)
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data[word] = htonl(REG_RD(bp, offset + 4*word));
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data[8] = 0x0;
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@ -4280,65 +4297,60 @@ static void _print_next_block(int idx, const char *blk)
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pr_cont("%s%s", idx ? ", " : "", blk);
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}
|
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static int bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
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int par_num, bool print)
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static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
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int *par_num, bool print)
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{
|
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int i = 0;
|
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u32 cur_bit = 0;
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u32 cur_bit;
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bool res;
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int i;
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res = false;
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for (i = 0; sig; i++) {
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cur_bit = ((u32)0x1 << i);
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cur_bit = (0x1UL << i);
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if (sig & cur_bit) {
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switch (cur_bit) {
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case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
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if (print) {
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_print_next_block(par_num++, "BRB");
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res |= true; /* Each bit is real error! */
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if (print) {
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switch (cur_bit) {
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case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
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_print_next_block((*par_num)++, "BRB");
|
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_print_parity(bp,
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BRB1_REG_BRB1_PRTY_STS);
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}
|
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break;
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case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
|
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if (print) {
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_print_next_block(par_num++, "PARSER");
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break;
|
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case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
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_print_next_block((*par_num)++,
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"PARSER");
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_print_parity(bp, PRS_REG_PRS_PRTY_STS);
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}
|
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break;
|
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case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
|
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if (print) {
|
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_print_next_block(par_num++, "TSDM");
|
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break;
|
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case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
|
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_print_next_block((*par_num)++, "TSDM");
|
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_print_parity(bp,
|
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TSDM_REG_TSDM_PRTY_STS);
|
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}
|
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break;
|
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case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
|
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if (print) {
|
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_print_next_block(par_num++,
|
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break;
|
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case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
|
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_print_next_block((*par_num)++,
|
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"SEARCHER");
|
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_print_parity(bp, SRC_REG_SRC_PRTY_STS);
|
||||
}
|
||||
break;
|
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case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
|
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if (print) {
|
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_print_next_block(par_num++, "TCM");
|
||||
_print_parity(bp,
|
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TCM_REG_TCM_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
|
||||
if (print) {
|
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_print_next_block(par_num++, "TSEMI");
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++, "TCM");
|
||||
_print_parity(bp, TCM_REG_TCM_PRTY_STS);
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++,
|
||||
"TSEMI");
|
||||
_print_parity(bp,
|
||||
TSEM_REG_TSEM_PRTY_STS_0);
|
||||
_print_parity(bp,
|
||||
TSEM_REG_TSEM_PRTY_STS_1);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "XPB");
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++, "XPB");
|
||||
_print_parity(bp, GRCBASE_XPB +
|
||||
PB_REG_PB_PRTY_STS);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
/* Clear the bit */
|
||||
|
@ -4346,53 +4358,59 @@ static int bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
|
|||
}
|
||||
}
|
||||
|
||||
return par_num;
|
||||
return res;
|
||||
}
|
||||
|
||||
static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
|
||||
int par_num, bool *global,
|
||||
static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
|
||||
int *par_num, bool *global,
|
||||
bool print)
|
||||
{
|
||||
int i = 0;
|
||||
u32 cur_bit = 0;
|
||||
u32 cur_bit;
|
||||
bool res;
|
||||
int i;
|
||||
|
||||
res = false;
|
||||
|
||||
for (i = 0; sig; i++) {
|
||||
cur_bit = ((u32)0x1 << i);
|
||||
cur_bit = (0x1UL << i);
|
||||
if (sig & cur_bit) {
|
||||
res |= true; /* Each bit is real error! */
|
||||
switch (cur_bit) {
|
||||
case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "PBF");
|
||||
_print_next_block((*par_num)++, "PBF");
|
||||
_print_parity(bp, PBF_REG_PBF_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "QM");
|
||||
_print_next_block((*par_num)++, "QM");
|
||||
_print_parity(bp, QM_REG_QM_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "TM");
|
||||
_print_next_block((*par_num)++, "TM");
|
||||
_print_parity(bp, TM_REG_TM_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "XSDM");
|
||||
_print_next_block((*par_num)++, "XSDM");
|
||||
_print_parity(bp,
|
||||
XSDM_REG_XSDM_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "XCM");
|
||||
_print_next_block((*par_num)++, "XCM");
|
||||
_print_parity(bp, XCM_REG_XCM_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "XSEMI");
|
||||
_print_next_block((*par_num)++,
|
||||
"XSEMI");
|
||||
_print_parity(bp,
|
||||
XSEM_REG_XSEM_PRTY_STS_0);
|
||||
_print_parity(bp,
|
||||
|
@ -4401,7 +4419,7 @@ static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
|
|||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++,
|
||||
_print_next_block((*par_num)++,
|
||||
"DOORBELLQ");
|
||||
_print_parity(bp,
|
||||
DORQ_REG_DORQ_PRTY_STS);
|
||||
|
@ -4409,7 +4427,7 @@ static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
|
|||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "NIG");
|
||||
_print_next_block((*par_num)++, "NIG");
|
||||
if (CHIP_IS_E1x(bp)) {
|
||||
_print_parity(bp,
|
||||
NIG_REG_NIG_PRTY_STS);
|
||||
|
@ -4423,32 +4441,34 @@ static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
|
|||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
|
||||
if (print)
|
||||
_print_next_block(par_num++,
|
||||
_print_next_block((*par_num)++,
|
||||
"VAUX PCI CORE");
|
||||
*global = true;
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "DEBUG");
|
||||
_print_next_block((*par_num)++,
|
||||
"DEBUG");
|
||||
_print_parity(bp, DBG_REG_DBG_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "USDM");
|
||||
_print_next_block((*par_num)++, "USDM");
|
||||
_print_parity(bp,
|
||||
USDM_REG_USDM_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "UCM");
|
||||
_print_next_block((*par_num)++, "UCM");
|
||||
_print_parity(bp, UCM_REG_UCM_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "USEMI");
|
||||
_print_next_block((*par_num)++,
|
||||
"USEMI");
|
||||
_print_parity(bp,
|
||||
USEM_REG_USEM_PRTY_STS_0);
|
||||
_print_parity(bp,
|
||||
|
@ -4457,21 +4477,21 @@ static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
|
|||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "UPB");
|
||||
_print_next_block((*par_num)++, "UPB");
|
||||
_print_parity(bp, GRCBASE_UPB +
|
||||
PB_REG_PB_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "CSDM");
|
||||
_print_next_block((*par_num)++, "CSDM");
|
||||
_print_parity(bp,
|
||||
CSDM_REG_CSDM_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "CCM");
|
||||
_print_next_block((*par_num)++, "CCM");
|
||||
_print_parity(bp, CCM_REG_CCM_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
|
@ -4482,80 +4502,73 @@ static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
|
|||
}
|
||||
}
|
||||
|
||||
return par_num;
|
||||
return res;
|
||||
}
|
||||
|
||||
static int bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
|
||||
int par_num, bool print)
|
||||
static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
|
||||
int *par_num, bool print)
|
||||
{
|
||||
int i = 0;
|
||||
u32 cur_bit = 0;
|
||||
u32 cur_bit;
|
||||
bool res;
|
||||
int i;
|
||||
|
||||
res = false;
|
||||
|
||||
for (i = 0; sig; i++) {
|
||||
cur_bit = ((u32)0x1 << i);
|
||||
cur_bit = (0x1UL << i);
|
||||
if (sig & cur_bit) {
|
||||
switch (cur_bit) {
|
||||
case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "CSEMI");
|
||||
res |= true; /* Each bit is real error! */
|
||||
if (print) {
|
||||
switch (cur_bit) {
|
||||
case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++,
|
||||
"CSEMI");
|
||||
_print_parity(bp,
|
||||
CSEM_REG_CSEM_PRTY_STS_0);
|
||||
_print_parity(bp,
|
||||
CSEM_REG_CSEM_PRTY_STS_1);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "PXP");
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++, "PXP");
|
||||
_print_parity(bp, PXP_REG_PXP_PRTY_STS);
|
||||
_print_parity(bp,
|
||||
PXP2_REG_PXP2_PRTY_STS_0);
|
||||
_print_parity(bp,
|
||||
PXP2_REG_PXP2_PRTY_STS_1);
|
||||
}
|
||||
break;
|
||||
case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
|
||||
if (print)
|
||||
_print_next_block(par_num++,
|
||||
"PXPPCICLOCKCLIENT");
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "CFC");
|
||||
break;
|
||||
case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++,
|
||||
"PXPPCICLOCKCLIENT");
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++, "CFC");
|
||||
_print_parity(bp,
|
||||
CFC_REG_CFC_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "CDU");
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++, "CDU");
|
||||
_print_parity(bp, CDU_REG_CDU_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "DMAE");
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++, "DMAE");
|
||||
_print_parity(bp,
|
||||
DMAE_REG_DMAE_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "IGU");
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++, "IGU");
|
||||
if (CHIP_IS_E1x(bp))
|
||||
_print_parity(bp,
|
||||
HC_REG_HC_PRTY_STS);
|
||||
else
|
||||
_print_parity(bp,
|
||||
IGU_REG_IGU_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "MISC");
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++, "MISC");
|
||||
_print_parity(bp,
|
||||
MISC_REG_MISC_PRTY_STS);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
/* Clear the bit */
|
||||
|
@ -4563,40 +4576,49 @@ static int bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
|
|||
}
|
||||
}
|
||||
|
||||
return par_num;
|
||||
return res;
|
||||
}
|
||||
|
||||
static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
|
||||
bool *global, bool print)
|
||||
static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
|
||||
int *par_num, bool *global,
|
||||
bool print)
|
||||
{
|
||||
int i = 0;
|
||||
u32 cur_bit = 0;
|
||||
bool res = false;
|
||||
u32 cur_bit;
|
||||
int i;
|
||||
|
||||
for (i = 0; sig; i++) {
|
||||
cur_bit = ((u32)0x1 << i);
|
||||
cur_bit = (0x1UL << i);
|
||||
if (sig & cur_bit) {
|
||||
switch (cur_bit) {
|
||||
case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
|
||||
if (print)
|
||||
_print_next_block(par_num++, "MCP ROM");
|
||||
_print_next_block((*par_num)++,
|
||||
"MCP ROM");
|
||||
*global = true;
|
||||
res |= true;
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
|
||||
if (print)
|
||||
_print_next_block(par_num++,
|
||||
_print_next_block((*par_num)++,
|
||||
"MCP UMP RX");
|
||||
*global = true;
|
||||
res |= true;
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
|
||||
if (print)
|
||||
_print_next_block(par_num++,
|
||||
_print_next_block((*par_num)++,
|
||||
"MCP UMP TX");
|
||||
*global = true;
|
||||
res |= true;
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
|
||||
if (print)
|
||||
_print_next_block(par_num++,
|
||||
_print_next_block((*par_num)++,
|
||||
"MCP SCPAD");
|
||||
*global = true;
|
||||
/* clear latched SCPAD PATIRY from MCP */
|
||||
REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
|
||||
1UL << 10);
|
||||
break;
|
||||
}
|
||||
|
||||
|
@ -4605,45 +4627,50 @@ static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
|
|||
}
|
||||
}
|
||||
|
||||
return par_num;
|
||||
return res;
|
||||
}
|
||||
|
||||
static int bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
|
||||
int par_num, bool print)
|
||||
static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
|
||||
int *par_num, bool print)
|
||||
{
|
||||
int i = 0;
|
||||
u32 cur_bit = 0;
|
||||
u32 cur_bit;
|
||||
bool res;
|
||||
int i;
|
||||
|
||||
res = false;
|
||||
|
||||
for (i = 0; sig; i++) {
|
||||
cur_bit = ((u32)0x1 << i);
|
||||
cur_bit = (0x1UL << i);
|
||||
if (sig & cur_bit) {
|
||||
switch (cur_bit) {
|
||||
case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "PGLUE_B");
|
||||
res |= true; /* Each bit is real error! */
|
||||
if (print) {
|
||||
switch (cur_bit) {
|
||||
case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++,
|
||||
"PGLUE_B");
|
||||
_print_parity(bp,
|
||||
PGLUE_B_REG_PGLUE_B_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "ATC");
|
||||
PGLUE_B_REG_PGLUE_B_PRTY_STS);
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++, "ATC");
|
||||
_print_parity(bp,
|
||||
ATC_REG_ATC_PRTY_STS);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
/* Clear the bit */
|
||||
sig &= ~cur_bit;
|
||||
}
|
||||
}
|
||||
|
||||
return par_num;
|
||||
return res;
|
||||
}
|
||||
|
||||
static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
|
||||
u32 *sig)
|
||||
{
|
||||
bool res = false;
|
||||
|
||||
if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
|
||||
(sig[1] & HW_PRTY_ASSERT_SET_1) ||
|
||||
(sig[2] & HW_PRTY_ASSERT_SET_2) ||
|
||||
|
@ -4660,23 +4687,22 @@ static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
|
|||
if (print)
|
||||
netdev_err(bp->dev,
|
||||
"Parity errors detected in blocks: ");
|
||||
par_num = bnx2x_check_blocks_with_parity0(bp,
|
||||
sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
|
||||
par_num = bnx2x_check_blocks_with_parity1(bp,
|
||||
sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
|
||||
par_num = bnx2x_check_blocks_with_parity2(bp,
|
||||
sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
|
||||
par_num = bnx2x_check_blocks_with_parity3(
|
||||
sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
|
||||
par_num = bnx2x_check_blocks_with_parity4(bp,
|
||||
sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
|
||||
res |= bnx2x_check_blocks_with_parity0(bp,
|
||||
sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
|
||||
res |= bnx2x_check_blocks_with_parity1(bp,
|
||||
sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
|
||||
res |= bnx2x_check_blocks_with_parity2(bp,
|
||||
sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
|
||||
res |= bnx2x_check_blocks_with_parity3(bp,
|
||||
sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
|
||||
res |= bnx2x_check_blocks_with_parity4(bp,
|
||||
sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
|
||||
|
||||
if (print)
|
||||
pr_cont("\n");
|
||||
}
|
||||
|
||||
return true;
|
||||
} else
|
||||
return false;
|
||||
return res;
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -7126,7 +7152,7 @@ static int bnx2x_init_hw_port(struct bnx2x *bp)
|
|||
int port = BP_PORT(bp);
|
||||
int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
|
||||
u32 low, high;
|
||||
u32 val;
|
||||
u32 val, reg;
|
||||
|
||||
DP(NETIF_MSG_HW, "starting port init port %d\n", port);
|
||||
|
||||
|
@ -7271,6 +7297,17 @@ static int bnx2x_init_hw_port(struct bnx2x *bp)
|
|||
val |= CHIP_IS_E1(bp) ? 0 : 0x10;
|
||||
REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
|
||||
|
||||
/* SCPAD_PARITY should NOT trigger close the gates */
|
||||
reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
|
||||
REG_WR(bp, reg,
|
||||
REG_RD(bp, reg) &
|
||||
~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
|
||||
|
||||
reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
|
||||
REG_WR(bp, reg,
|
||||
REG_RD(bp, reg) &
|
||||
~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
|
||||
|
||||
bnx2x_init_block(bp, BLOCK_NIG, init_phase);
|
||||
|
||||
if (!CHIP_IS_E1x(bp)) {
|
||||
|
@ -11685,9 +11722,6 @@ static int bnx2x_init_bp(struct bnx2x *bp)
|
|||
static int bnx2x_open(struct net_device *dev)
|
||||
{
|
||||
struct bnx2x *bp = netdev_priv(dev);
|
||||
bool global = false;
|
||||
int other_engine = BP_PATH(bp) ? 0 : 1;
|
||||
bool other_load_status, load_status;
|
||||
int rc;
|
||||
|
||||
bp->stats_init = true;
|
||||
|
@ -11703,6 +11737,10 @@ static int bnx2x_open(struct net_device *dev)
|
|||
* Parity recovery is only relevant for PF driver.
|
||||
*/
|
||||
if (IS_PF(bp)) {
|
||||
int other_engine = BP_PATH(bp) ? 0 : 1;
|
||||
bool other_load_status, load_status;
|
||||
bool global = false;
|
||||
|
||||
other_load_status = bnx2x_get_load_status(bp, other_engine);
|
||||
load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
|
||||
if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
|
||||
|
@ -12080,7 +12118,6 @@ static int bnx2x_set_coherency_mask(struct bnx2x *bp)
|
|||
struct device *dev = &bp->pdev->dev;
|
||||
|
||||
if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
|
||||
bp->flags |= USING_DAC_FLAG;
|
||||
if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
|
||||
dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
|
||||
return -EIO;
|
||||
|
@ -12248,8 +12285,7 @@ static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
|
|||
NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
|
||||
|
||||
dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
|
||||
if (bp->flags & USING_DAC_FLAG)
|
||||
dev->features |= NETIF_F_HIGHDMA;
|
||||
dev->features |= NETIF_F_HIGHDMA;
|
||||
|
||||
/* Add Loopback capability to the device */
|
||||
dev->hw_features |= NETIF_F_LOOPBACK;
|
||||
|
@ -12612,24 +12648,24 @@ static int set_max_cos_est(int chip_id)
|
|||
return BNX2X_MULTI_TX_COS_E1X;
|
||||
case BCM57712:
|
||||
case BCM57712_MF:
|
||||
case BCM57712_VF:
|
||||
return BNX2X_MULTI_TX_COS_E2_E3A0;
|
||||
case BCM57800:
|
||||
case BCM57800_MF:
|
||||
case BCM57800_VF:
|
||||
case BCM57810:
|
||||
case BCM57810_MF:
|
||||
case BCM57840_4_10:
|
||||
case BCM57840_2_20:
|
||||
case BCM57840_O:
|
||||
case BCM57840_MFO:
|
||||
case BCM57810_VF:
|
||||
case BCM57840_MF:
|
||||
case BCM57840_VF:
|
||||
case BCM57811:
|
||||
case BCM57811_MF:
|
||||
case BCM57811_VF:
|
||||
return BNX2X_MULTI_TX_COS_E3B0;
|
||||
case BCM57712_VF:
|
||||
case BCM57800_VF:
|
||||
case BCM57810_VF:
|
||||
case BCM57840_VF:
|
||||
case BCM57811_VF:
|
||||
return 1;
|
||||
default:
|
||||
pr_err("Unknown board_type (%d), aborting\n", chip_id);
|
||||
|
|
|
@ -470,10 +470,10 @@ static int bnx2x_vfop_qdtor_cmd(struct bnx2x *bp,
|
|||
bnx2x_vfop_qdtor, cmd->done);
|
||||
return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_qdtor,
|
||||
cmd->block);
|
||||
} else {
|
||||
BNX2X_ERR("VF[%d] failed to add a vfop\n", vf->abs_vfid);
|
||||
return -ENOMEM;
|
||||
}
|
||||
DP(BNX2X_MSG_IOV, "VF[%d] failed to add a vfop. rc %d\n",
|
||||
vf->abs_vfid, vfop->rc);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
static void
|
||||
|
@ -3390,14 +3390,16 @@ int bnx2x_set_vf_mac(struct net_device *dev, int vfidx, u8 *mac)
|
|||
rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_ETH_MAC, true);
|
||||
if (rc) {
|
||||
BNX2X_ERR("failed to delete eth macs\n");
|
||||
return -EINVAL;
|
||||
rc = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* remove existing uc list macs */
|
||||
rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, true);
|
||||
if (rc) {
|
||||
BNX2X_ERR("failed to delete uc_list macs\n");
|
||||
return -EINVAL;
|
||||
rc = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* configure the new mac to device */
|
||||
|
@ -3405,6 +3407,7 @@ int bnx2x_set_vf_mac(struct net_device *dev, int vfidx, u8 *mac)
|
|||
bnx2x_set_mac_one(bp, (u8 *)&bulletin->mac, mac_obj, true,
|
||||
BNX2X_ETH_MAC, &ramrod_flags);
|
||||
|
||||
out:
|
||||
bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_MAC);
|
||||
}
|
||||
|
||||
|
@ -3467,7 +3470,8 @@ int bnx2x_set_vf_vlan(struct net_device *dev, int vfidx, u16 vlan, u8 qos)
|
|||
&ramrod_flags);
|
||||
if (rc) {
|
||||
BNX2X_ERR("failed to delete vlans\n");
|
||||
return -EINVAL;
|
||||
rc = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* send queue update ramrod to configure default vlan and silent
|
||||
|
@ -3501,7 +3505,8 @@ int bnx2x_set_vf_vlan(struct net_device *dev, int vfidx, u16 vlan, u8 qos)
|
|||
rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
|
||||
if (rc) {
|
||||
BNX2X_ERR("failed to configure vlan\n");
|
||||
return -EINVAL;
|
||||
rc = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* configure default vlan to vf queue and set silent
|
||||
|
@ -3519,18 +3524,18 @@ int bnx2x_set_vf_vlan(struct net_device *dev, int vfidx, u16 vlan, u8 qos)
|
|||
rc = bnx2x_queue_state_change(bp, &q_params);
|
||||
if (rc) {
|
||||
BNX2X_ERR("Failed to configure default VLAN\n");
|
||||
return rc;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* clear the flag indicating that this VF needs its vlan
|
||||
* (will only be set if the HV configured th Vlan before vf was
|
||||
* and we were called because the VF came up later
|
||||
* (will only be set if the HV configured the Vlan before vf was
|
||||
* up and we were called because the VF came up later
|
||||
*/
|
||||
out:
|
||||
vf->cfg_flags &= ~VF_CFG_VLAN;
|
||||
|
||||
bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_VLAN);
|
||||
}
|
||||
return 0;
|
||||
return rc;
|
||||
}
|
||||
|
||||
/* crc is the first field in the bulletin board. Compute the crc over the
|
||||
|
|
|
@ -196,7 +196,7 @@ static void bnx2x_hw_stats_post(struct bnx2x *bp)
|
|||
|
||||
} else if (bp->func_stx) {
|
||||
*stats_comp = 0;
|
||||
bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
|
||||
bnx2x_issue_dmae_with_comp(bp, dmae, stats_comp);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -980,7 +980,7 @@ static int bnx2x_copy32_vf_dmae(struct bnx2x *bp, u8 from_vf,
|
|||
dmae.len = len32;
|
||||
|
||||
/* issue the command and wait for completion */
|
||||
return bnx2x_issue_dmae_with_comp(bp, &dmae);
|
||||
return bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
|
||||
}
|
||||
|
||||
static void bnx2x_vf_mbx_resp(struct bnx2x *bp, struct bnx2x_virtf *vf)
|
||||
|
|
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