powerpc/fsl: add MSI support for the Freescale hypervisor
Add support for vmpic-msi nodes to the fsl_msi driver. The MSI is virtualized by the hypervisor, so the vmpic-msi does not contain a 'reg' property. Instead, the driver uses hcalls. Add support for the "msi-address-64" property to the fsl_pci driver. The Freescale hypervisor typically puts the virtualized MSIIR register in the page after the end of DDR, so we extend the DDR ATMU to cover it. Any other location for MSIIR is not supported, for now. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Timur Tabi
Kumar Gala
Родитель
c6ca52ad32
Коммит
446bc1ffe4
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@ -23,6 +23,8 @@
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#include <asm/hw_irq.h>
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#include <asm/ppc-pci.h>
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#include <asm/mpic.h>
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#include <asm/fsl_hcalls.h>
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#include "fsl_msi.h"
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#include "fsl_pci.h"
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@ -163,11 +165,13 @@ static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
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*/
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np = of_parse_phandle(hose->dn, "fsl,msi", 0);
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if (np) {
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if (of_device_is_compatible(np, "fsl,mpic-msi"))
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if (of_device_is_compatible(np, "fsl,mpic-msi") ||
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of_device_is_compatible(np, "fsl,vmpic-msi"))
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phandle = np->phandle;
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else {
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dev_err(&pdev->dev, "node %s has an invalid fsl,msi"
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" phandle\n", hose->dn->full_name);
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dev_err(&pdev->dev,
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"node %s has an invalid fsl,msi phandle %u\n",
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hose->dn->full_name, np->phandle);
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return -EINVAL;
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}
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}
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@ -196,16 +200,14 @@ static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
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if (hwirq < 0) {
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rc = hwirq;
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pr_debug("%s: fail allocating msi interrupt\n",
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__func__);
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dev_err(&pdev->dev, "could not allocate MSI interrupt\n");
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goto out_free;
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}
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virq = irq_create_mapping(msi_data->irqhost, hwirq);
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if (virq == NO_IRQ) {
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pr_debug("%s: fail mapping hwirq 0x%x\n",
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__func__, hwirq);
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dev_err(&pdev->dev, "fail mapping hwirq %i\n", hwirq);
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msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
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rc = -ENOSPC;
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goto out_free;
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@ -234,6 +236,7 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
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u32 intr_index;
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u32 have_shift = 0;
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struct fsl_msi_cascade_data *cascade_data;
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unsigned int ret;
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cascade_data = irq_get_handler_data(irq);
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msi_data = cascade_data->msi_data;
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@ -265,6 +268,14 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
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case FSL_PIC_IP_IPIC:
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msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
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break;
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case FSL_PIC_IP_VMPIC:
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ret = fh_vmpic_get_msir(virq_to_hw(irq), &msir_value);
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if (ret) {
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pr_err("fsl-msi: fh_vmpic_get_msir() failed for "
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"irq %u (ret=%u)\n", irq, ret);
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msir_value = 0;
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}
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break;
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}
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while (msir_value) {
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@ -282,6 +293,7 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
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switch (msi_data->feature & FSL_PIC_IP_MASK) {
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case FSL_PIC_IP_MPIC:
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case FSL_PIC_IP_VMPIC:
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chip->irq_eoi(idata);
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break;
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case FSL_PIC_IP_IPIC:
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@ -311,7 +323,8 @@ static int fsl_of_msi_remove(struct platform_device *ofdev)
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}
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if (msi->bitmap.bitmap)
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msi_bitmap_free(&msi->bitmap);
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iounmap(msi->msi_regs);
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if ((msi->feature & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC)
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iounmap(msi->msi_regs);
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kfree(msi);
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return 0;
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@ -383,26 +396,32 @@ static int __devinit fsl_of_msi_probe(struct platform_device *dev)
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goto error_out;
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}
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/* Get the MSI reg base */
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err = of_address_to_resource(dev->dev.of_node, 0, &res);
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if (err) {
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dev_err(&dev->dev, "%s resource error!\n",
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/*
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* Under the Freescale hypervisor, the msi nodes don't have a 'reg'
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* property. Instead, we use hypercalls to access the MSI.
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*/
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if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC) {
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err = of_address_to_resource(dev->dev.of_node, 0, &res);
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if (err) {
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dev_err(&dev->dev, "invalid resource for node %s\n",
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dev->dev.of_node->full_name);
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goto error_out;
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}
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goto error_out;
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}
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msi->msi_regs = ioremap(res.start, resource_size(&res));
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if (!msi->msi_regs) {
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dev_err(&dev->dev, "ioremap problem failed\n");
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goto error_out;
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msi->msi_regs = ioremap(res.start, resource_size(&res));
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if (!msi->msi_regs) {
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dev_err(&dev->dev, "could not map node %s\n",
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dev->dev.of_node->full_name);
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goto error_out;
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}
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msi->msiir_offset =
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features->msiir_offset + (res.start & 0xfffff);
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}
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msi->feature = features->fsl_pic_ip;
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msi->irqhost->host_data = msi;
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msi->msiir_offset = features->msiir_offset + (res.start & 0xfffff);
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/*
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* Remember the phandle, so that we can match with any PCI nodes
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* that have an "fsl,msi" property.
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@ -476,6 +495,11 @@ static const struct fsl_msi_feature ipic_msi_feature = {
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.msiir_offset = 0x38,
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};
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static const struct fsl_msi_feature vmpic_msi_feature = {
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.fsl_pic_ip = FSL_PIC_IP_VMPIC,
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.msiir_offset = 0,
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};
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static const struct of_device_id fsl_of_msi_ids[] = {
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{
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.compatible = "fsl,mpic-msi",
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@ -485,6 +509,10 @@ static const struct of_device_id fsl_of_msi_ids[] = {
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.compatible = "fsl,ipic-msi",
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.data = (void *)&ipic_msi_feature,
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},
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{
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.compatible = "fsl,vmpic-msi",
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.data = (void *)&vmpic_msi_feature,
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},
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{}
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};
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@ -20,9 +20,10 @@
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#define IRQS_PER_MSI_REG 32
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#define NR_MSI_IRQS (NR_MSI_REG * IRQS_PER_MSI_REG)
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#define FSL_PIC_IP_MASK 0x0000000F
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#define FSL_PIC_IP_MPIC 0x00000001
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#define FSL_PIC_IP_IPIC 0x00000002
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#define FSL_PIC_IP_MASK 0x0000000F
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#define FSL_PIC_IP_MPIC 0x00000001
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#define FSL_PIC_IP_IPIC 0x00000002
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#define FSL_PIC_IP_VMPIC 0x00000003
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struct fsl_msi {
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struct irq_host *irqhost;
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@ -137,6 +137,8 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
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u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
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PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
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char *name = hose->dn->full_name;
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const u64 *reg;
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int len;
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pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
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(u64)rsrc->start, (u64)resource_size(rsrc));
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@ -229,6 +231,33 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
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/* Setup inbound mem window */
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mem = memblock_end_of_DRAM();
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/*
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* The msi-address-64 property, if it exists, indicates the physical
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* address of the MSIIR register. Normally, this register is located
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* inside CCSR, so the ATMU that covers all of CCSR is used. But if
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* this property exists, then we normally need to create a new ATMU
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* for it. For now, however, we cheat. The only entity that creates
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* this property is the Freescale hypervisor, and the address is
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* specified in the partition configuration. Typically, the address
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* is located in the page immediately after the end of DDR. If so, we
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* can avoid allocating a new ATMU by extending the DDR ATMU by one
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* page.
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*/
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reg = of_get_property(hose->dn, "msi-address-64", &len);
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if (reg && (len == sizeof(u64))) {
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u64 address = be64_to_cpup(reg);
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if ((address >= mem) && (address < (mem + PAGE_SIZE))) {
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pr_info("%s: extending DDR ATMU to cover MSIIR", name);
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mem += PAGE_SIZE;
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} else {
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/* TODO: Create a new ATMU for MSIIR */
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pr_warn("%s: msi-address-64 address of %llx is "
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"unsupported\n", name, address);
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}
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}
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sz = min(mem, paddr_lo);
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mem_log = __ilog2_u64(sz);
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