drm/amdgpu: fix unused variable
SOC15_WAIT_ON_RREG's return value needn't always been handled by caller. new design is to fix this kind of unused variable. Signed-off-by: James Zhu <James.Zhu@amd.com> Reported-by: kernel test robot <lkp@intel.com> Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
James Zhu
Alex Deucher
Родитель
a20ace1b02
Коммит
450da2ef41
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@ -230,9 +230,9 @@ static int jpeg_v2_0_disable_power_gating(struct amdgpu_device *adev)
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data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
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WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
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SOC15_WAIT_ON_RREG(JPEG, 0,
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r = SOC15_WAIT_ON_RREG(JPEG, 0,
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mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
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UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
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UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
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if (r) {
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DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
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@ -261,9 +261,9 @@ static int jpeg_v2_0_enable_power_gating(struct amdgpu_device* adev)
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data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
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WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
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SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,
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r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,
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(2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),
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UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
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UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
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if (r) {
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DRM_ERROR("amdgpu: JPEG enable power gating failed\n");
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@ -677,10 +677,10 @@ static bool jpeg_v2_0_is_idle(void *handle)
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static int jpeg_v2_0_wait_for_idle(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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int ret = 0;
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int ret;
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SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
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UVD_JRBC_STATUS__RB_JOB_DONE_MASK, ret);
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ret = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
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UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
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return ret;
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}
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@ -449,15 +449,15 @@ static bool jpeg_v2_5_is_idle(void *handle)
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static int jpeg_v2_5_wait_for_idle(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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int i, ret = 0;
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int i, ret;
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for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
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if (adev->jpeg.harvest_config & (1 << i))
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continue;
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SOC15_WAIT_ON_RREG(JPEG, i, mmUVD_JRBC_STATUS,
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ret = SOC15_WAIT_ON_RREG(JPEG, i, mmUVD_JRBC_STATUS,
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UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
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UVD_JRBC_STATUS__RB_JOB_DONE_MASK, ret);
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UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
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if (ret)
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return ret;
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}
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@ -266,9 +266,9 @@ static int jpeg_v3_0_disable_static_power_gating(struct amdgpu_device *adev)
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data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
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WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
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SOC15_WAIT_ON_RREG(JPEG, 0,
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r = SOC15_WAIT_ON_RREG(JPEG, 0,
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mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
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UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
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UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
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if (r) {
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DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
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@ -301,9 +301,9 @@ static int jpeg_v3_0_enable_static_power_gating(struct amdgpu_device* adev)
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data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
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WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
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SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,
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r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,
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(2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),
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UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
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UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
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if (r) {
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DRM_ERROR("amdgpu: JPEG enable power gating failed\n");
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@ -461,11 +461,11 @@ static bool jpeg_v3_0_is_idle(void *handle)
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static int jpeg_v3_0_wait_for_idle(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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int ret = 0;
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int ret;
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SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS,
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ret = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS,
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UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
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UVD_JRBC_STATUS__RB_JOB_DONE_MASK, ret);
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UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
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if (ret)
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return ret;
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@ -50,18 +50,19 @@
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#define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
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WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value)
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#define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask, ret) \
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#define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \
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({ int ret = 0; \
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do { \
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uint32_t old_ = 0; \
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uint32_t old_ = 0; \
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uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
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uint32_t loop = adev->usec_timeout; \
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ret = 0; \
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while ((tmp_ & (mask)) != (expected_value)) { \
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if (old_ != tmp_) { \
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loop = adev->usec_timeout; \
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old_ = tmp_; \
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} else \
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udelay(1); \
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old_ = tmp_; \
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} else \
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udelay(1); \
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tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
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loop--; \
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if (!loop) { \
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@ -71,7 +72,9 @@
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break; \
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} \
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} \
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} while (0)
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} while (0); \
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ret; \
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})
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#define WREG32_RLC(reg, value) \
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do { \
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@ -683,7 +683,6 @@ static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t s
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static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev)
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{
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uint32_t data = 0;
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int ret;
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if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
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data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
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@ -699,7 +698,7 @@ static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev)
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| 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
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WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
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SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF, ret);
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SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF);
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} else {
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data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
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| 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
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@ -713,7 +712,7 @@ static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev)
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| 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
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| 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
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WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
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SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFFFFF, ret);
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SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFFFFF);
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}
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/* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */
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@ -729,7 +728,6 @@ static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev)
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static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev)
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{
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uint32_t data = 0;
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int ret;
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if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
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/* Before power off, this indicator has to be turned on */
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@ -764,7 +762,7 @@ static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev)
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| 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
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| 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
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| 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT);
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SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF, ret);
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SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF);
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}
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}
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@ -1113,15 +1111,15 @@ static int vcn_v1_0_start(struct amdgpu_device *adev)
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*/
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static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
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{
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int ret_code, tmp;
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int tmp;
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SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, ret_code);
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SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
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tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
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UVD_LMI_STATUS__READ_CLEAN_MASK |
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UVD_LMI_STATUS__WRITE_CLEAN_MASK |
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UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
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SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code);
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SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);
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/* put VCPU into reset */
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WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
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@ -1130,7 +1128,7 @@ static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
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tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
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UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
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SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code);
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SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);
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/* disable VCPU clock */
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WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
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@ -1154,30 +1152,29 @@ static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
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static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)
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{
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int ret_code = 0;
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uint32_t tmp;
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/* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */
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SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
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UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
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UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
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UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
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/* wait for read ptr to be equal to write ptr */
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tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
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SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
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SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
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tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
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SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code);
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SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
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tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
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SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
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SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF);
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tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
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SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
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SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
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SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
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UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
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UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
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UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
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/* disable dynamic power gating mode */
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WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
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@ -1220,9 +1217,9 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
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ret_code = 0;
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if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK))
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SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
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ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
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UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
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UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
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UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
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if (!ret_code) {
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/* pause DPG non-jpeg */
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@ -1230,7 +1227,7 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
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WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
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SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
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UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
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UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code);
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UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
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/* Restore */
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ring = &adev->vcn.inst->ring_enc[0];
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@ -1252,7 +1249,7 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
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RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
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SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
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UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
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UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
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UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
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}
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} else {
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/* unpause dpg non-jpeg, no need to wait */
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@ -1276,9 +1273,9 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
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ret_code = 0;
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if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK))
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SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
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ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
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UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
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UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
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UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
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if (!ret_code) {
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/* Make sure JPRG Snoop is disabled before sending the pause */
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@ -1291,7 +1288,7 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
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WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
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SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
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UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK,
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UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, ret_code);
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UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK);
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/* Restore */
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ring = &adev->jpeg.inst->ring_dec;
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@ -1313,7 +1310,7 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
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RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
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SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
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UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
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UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
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UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
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}
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} else {
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/* unpause dpg jpeg, no need to wait */
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@ -1336,10 +1333,10 @@ static bool vcn_v1_0_is_idle(void *handle)
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static int vcn_v1_0_wait_for_idle(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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int ret = 0;
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int ret;
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|
||||
SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
|
||||
UVD_STATUS__IDLE, ret);
|
||||
ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
|
||||
UVD_STATUS__IDLE);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -697,7 +697,6 @@ static void vcn_v2_0_enable_clock_gating(struct amdgpu_device *adev)
|
|||
static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev)
|
||||
{
|
||||
uint32_t data = 0;
|
||||
int ret;
|
||||
|
||||
if (amdgpu_sriov_vf(adev))
|
||||
return;
|
||||
|
|
@ -716,7 +715,7 @@ static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev)
|
|||
|
||||
WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
|
||||
SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS,
|
||||
UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0, 0xFFFFF, ret);
|
||||
UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0, 0xFFFFF);
|
||||
} else {
|
||||
data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
|
||||
| 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
|
||||
|
|
@ -729,7 +728,7 @@ static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev)
|
|||
| 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
|
||||
| 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
|
||||
WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
|
||||
SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF, ret);
|
||||
SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF);
|
||||
}
|
||||
|
||||
/* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS,
|
||||
|
|
@ -747,7 +746,6 @@ static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev)
|
|||
static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev)
|
||||
{
|
||||
uint32_t data = 0;
|
||||
int ret;
|
||||
|
||||
if (amdgpu_sriov_vf(adev))
|
||||
return;
|
||||
|
|
@ -783,7 +781,7 @@ static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev)
|
|||
| 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
|
||||
| 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
|
||||
| 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT);
|
||||
SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF, ret);
|
||||
SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1099,25 +1097,24 @@ static int vcn_v2_0_start(struct amdgpu_device *adev)
|
|||
|
||||
static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev)
|
||||
{
|
||||
int ret_code = 0;
|
||||
uint32_t tmp;
|
||||
|
||||
/* Wait for power status to be 1 */
|
||||
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
|
||||
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
|
||||
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
|
||||
|
||||
/* wait for read ptr to be equal to write ptr */
|
||||
tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
|
||||
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
|
||||
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
|
||||
|
||||
tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
|
||||
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code);
|
||||
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
|
||||
|
||||
tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
|
||||
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
|
||||
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
|
||||
|
||||
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
|
||||
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
|
||||
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
|
||||
|
||||
/* disable dynamic power gating mode */
|
||||
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
|
||||
|
|
@ -1139,7 +1136,7 @@ static int vcn_v2_0_stop(struct amdgpu_device *adev)
|
|||
}
|
||||
|
||||
/* wait for uvd idle */
|
||||
SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
|
||||
r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
|
|
@ -1147,7 +1144,7 @@ static int vcn_v2_0_stop(struct amdgpu_device *adev)
|
|||
UVD_LMI_STATUS__READ_CLEAN_MASK |
|
||||
UVD_LMI_STATUS__WRITE_CLEAN_MASK |
|
||||
UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
|
||||
SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r);
|
||||
r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
|
|
@ -1158,7 +1155,7 @@ static int vcn_v2_0_stop(struct amdgpu_device *adev)
|
|||
|
||||
tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
|
||||
UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
|
||||
SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r);
|
||||
r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
|
|
@ -1209,9 +1206,8 @@ static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
|
|||
(~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
|
||||
|
||||
if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
|
||||
ret_code = 0;
|
||||
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1,
|
||||
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
|
||||
ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1,
|
||||
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
|
||||
|
||||
if (!ret_code) {
|
||||
volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr;
|
||||
|
|
@ -1222,7 +1218,7 @@ static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
|
|||
/* wait for ACK */
|
||||
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
|
||||
UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
|
||||
UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code);
|
||||
UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
|
||||
|
||||
/* Stall DPG before WPTR/RPTR reset */
|
||||
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
|
||||
|
|
@ -1259,7 +1255,7 @@ static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
|
|||
|
||||
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
|
||||
UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
|
||||
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
|
||||
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
|
||||
}
|
||||
} else {
|
||||
/* unpause dpg, no need to wait */
|
||||
|
|
@ -1282,10 +1278,10 @@ static bool vcn_v2_0_is_idle(void *handle)
|
|||
static int vcn_v2_0_wait_for_idle(void *handle)
|
||||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
int ret = 0;
|
||||
int ret;
|
||||
|
||||
SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
|
||||
UVD_STATUS__IDLE, ret);
|
||||
ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
|
||||
UVD_STATUS__IDLE);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -549,7 +549,6 @@ static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx
|
|||
static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev)
|
||||
{
|
||||
uint32_t data;
|
||||
int ret = 0;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
|
||||
|
|
@ -589,7 +588,7 @@ static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev)
|
|||
|
||||
WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data);
|
||||
|
||||
SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, ret);
|
||||
SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF);
|
||||
|
||||
data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
|
||||
data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
|
||||
|
|
@ -1302,25 +1301,24 @@ static int vcn_v2_5_sriov_start(struct amdgpu_device *adev)
|
|||
|
||||
static int vcn_v2_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
|
||||
{
|
||||
int ret_code = 0;
|
||||
uint32_t tmp;
|
||||
|
||||
/* Wait for power status to be 1 */
|
||||
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
|
||||
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
|
||||
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
|
||||
|
||||
/* wait for read ptr to be equal to write ptr */
|
||||
tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR);
|
||||
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
|
||||
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
|
||||
|
||||
tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2);
|
||||
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code);
|
||||
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
|
||||
|
||||
tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
|
||||
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
|
||||
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
|
||||
|
||||
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
|
||||
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
|
||||
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
|
||||
|
||||
/* disable dynamic power gating mode */
|
||||
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0,
|
||||
|
|
@ -1343,7 +1341,7 @@ static int vcn_v2_5_stop(struct amdgpu_device *adev)
|
|||
}
|
||||
|
||||
/* wait for vcn idle */
|
||||
SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
|
||||
r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
|
|
@ -1351,7 +1349,7 @@ static int vcn_v2_5_stop(struct amdgpu_device *adev)
|
|||
UVD_LMI_STATUS__READ_CLEAN_MASK |
|
||||
UVD_LMI_STATUS__WRITE_CLEAN_MASK |
|
||||
UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
|
||||
SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp, r);
|
||||
r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
|
|
@ -1362,7 +1360,7 @@ static int vcn_v2_5_stop(struct amdgpu_device *adev)
|
|||
|
||||
tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
|
||||
UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
|
||||
SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp, r);
|
||||
r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
|
|
@ -1412,8 +1410,8 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
|
|||
(~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
|
||||
|
||||
if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
|
||||
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,
|
||||
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
|
||||
ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,
|
||||
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
|
||||
|
||||
if (!ret_code) {
|
||||
volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr;
|
||||
|
|
@ -1425,7 +1423,7 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
|
|||
/* wait for ACK */
|
||||
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE,
|
||||
UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
|
||||
UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code);
|
||||
UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
|
||||
|
||||
/* Stall DPG before WPTR/RPTR reset */
|
||||
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
|
||||
|
|
@ -1458,13 +1456,13 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
|
|||
0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
|
||||
|
||||
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS,
|
||||
UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
|
||||
UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
|
||||
}
|
||||
} else {
|
||||
reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
|
||||
WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);
|
||||
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,
|
||||
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
|
||||
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
|
||||
}
|
||||
adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
|
||||
}
|
||||
|
|
@ -1701,8 +1699,8 @@ static int vcn_v2_5_wait_for_idle(void *handle)
|
|||
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
|
||||
if (adev->vcn.harvest_config & (1 << i))
|
||||
continue;
|
||||
SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,
|
||||
UVD_STATUS__IDLE, ret);
|
||||
ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,
|
||||
UVD_STATUS__IDLE);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -482,7 +482,6 @@ static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx
|
|||
static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)
|
||||
{
|
||||
uint32_t data = 0;
|
||||
int ret;
|
||||
|
||||
if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
|
||||
data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
|
||||
|
|
@ -502,7 +501,7 @@ static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int
|
|||
|
||||
WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
|
||||
SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS,
|
||||
UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF, ret);
|
||||
UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF);
|
||||
} else {
|
||||
data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
|
||||
| 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
|
||||
|
|
@ -519,7 +518,7 @@ static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int
|
|||
| 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
|
||||
| 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
|
||||
WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
|
||||
SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF, ret);
|
||||
SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF);
|
||||
}
|
||||
|
||||
data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
|
||||
|
|
@ -534,7 +533,6 @@ static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int
|
|||
static void vcn_v3_0_enable_static_power_gating(struct amdgpu_device *adev, int inst)
|
||||
{
|
||||
uint32_t data;
|
||||
int ret;
|
||||
|
||||
if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
|
||||
/* Before power off, this indicator has to be turned on */
|
||||
|
|
@ -573,7 +571,7 @@ static void vcn_v3_0_enable_static_power_gating(struct amdgpu_device *adev, int
|
|||
| 2 << UVD_PGFSM_STATUS__UVDATD_PWR_STATUS__SHIFT
|
||||
| 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT
|
||||
| 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT);
|
||||
SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF, ret);
|
||||
SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -588,7 +586,6 @@ static void vcn_v3_0_enable_static_power_gating(struct amdgpu_device *adev, int
|
|||
static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst)
|
||||
{
|
||||
uint32_t data;
|
||||
int ret = 0;
|
||||
|
||||
/* VCN disable CGC */
|
||||
data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
|
||||
|
|
@ -624,7 +621,7 @@ static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst)
|
|||
|
||||
WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data);
|
||||
|
||||
SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, ret);
|
||||
SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF);
|
||||
|
||||
data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
|
||||
data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
|
||||
|
|
@ -1142,25 +1139,24 @@ static int vcn_v3_0_start(struct amdgpu_device *adev)
|
|||
|
||||
static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
|
||||
{
|
||||
int ret_code = 0;
|
||||
uint32_t tmp;
|
||||
|
||||
/* Wait for power status to be 1 */
|
||||
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
|
||||
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
|
||||
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
|
||||
|
||||
/* wait for read ptr to be equal to write ptr */
|
||||
tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR);
|
||||
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
|
||||
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
|
||||
|
||||
tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2);
|
||||
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code);
|
||||
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
|
||||
|
||||
tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
|
||||
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
|
||||
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
|
||||
|
||||
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
|
||||
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
|
||||
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
|
||||
|
||||
/* disable dynamic power gating mode */
|
||||
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0,
|
||||
|
|
@ -1184,7 +1180,7 @@ static int vcn_v3_0_stop(struct amdgpu_device *adev)
|
|||
}
|
||||
|
||||
/* wait for vcn idle */
|
||||
SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
|
||||
r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
|
|
@ -1192,7 +1188,7 @@ static int vcn_v3_0_stop(struct amdgpu_device *adev)
|
|||
UVD_LMI_STATUS__READ_CLEAN_MASK |
|
||||
UVD_LMI_STATUS__WRITE_CLEAN_MASK |
|
||||
UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
|
||||
SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp, r);
|
||||
r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
|
|
@ -1202,7 +1198,7 @@ static int vcn_v3_0_stop(struct amdgpu_device *adev)
|
|||
WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);
|
||||
tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
|
||||
UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
|
||||
SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp, r);
|
||||
r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
|
|
@ -1259,9 +1255,8 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
|
|||
(~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
|
||||
|
||||
if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
|
||||
ret_code = 0;
|
||||
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,
|
||||
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
|
||||
ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,
|
||||
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
|
||||
|
||||
if (!ret_code) {
|
||||
/* pause DPG */
|
||||
|
|
@ -1271,7 +1266,7 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
|
|||
/* wait for ACK */
|
||||
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE,
|
||||
UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
|
||||
UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code);
|
||||
UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
|
||||
|
||||
/* Restore */
|
||||
ring = &adev->vcn.inst[inst_idx].ring_enc[0];
|
||||
|
|
@ -1292,7 +1287,7 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
|
|||
RREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2) & 0x7FFFFFFF);
|
||||
|
||||
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS,
|
||||
UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
|
||||
UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
|
||||
}
|
||||
} else {
|
||||
/* unpause dpg, no need to wait */
|
||||
|
|
@ -1542,8 +1537,8 @@ static int vcn_v3_0_wait_for_idle(void *handle)
|
|||
if (adev->vcn.harvest_config & (1 << i))
|
||||
continue;
|
||||
|
||||
SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,
|
||||
UVD_STATUS__IDLE, ret);
|
||||
ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,
|
||||
UVD_STATUS__IDLE);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
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