Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (249 commits) powerpc: Fix pte_update for CONFIG_PTE_64BIT and !PTE_ATOMIC_UPDATES powerpc: Fix a build problem on ppc32 with new DMA_ATTRs ibm_newemac: Add MII mode support to the EMAC RGMII bridge. powerpc: Don't spin on sync instruction at boot time powerpc: Add VSX load/store alignment exception handler powerpc: fix giveup_vsx to save registers correctly powerpc: support for latencytop powerpc: Remove unnecessary condition when sanity-checking WIMG bits powerpc: Add PPC_FEATURE_PSERIES_PERFMON_COMPAT powerpc: Add driver for Barrier Synchronization Register powerpc: mman.h export fixups powerpc/fsl: update crypto node definition and device tree instances powerpc/fsl: Refactor device bindings powerpc/85xx: Minor fixes for 85xxds and 8536ds board. powerpc: Add 82xx/83xx/86xx to 6xx Multiplatform powerpc/85xx: publish of device for cds platforms powerpc/booke: don't reinitialize time base powerpc/86xx: Refactor pic init powerpc/CPM: Add i2c pins to dts and board setup cpm_uart: Support uart_wait_until_sent() ...
This commit is contained in:
Linus Torvalds
Коммит
45158894d4
|
|
@ -172,6 +172,7 @@ architectures:
|
|||
- ia64 (Does not support probes on instruction slot1.)
|
||||
- sparc64 (Return probes not yet implemented.)
|
||||
- arm
|
||||
- ppc
|
||||
|
||||
3. Configuring Kprobes
|
||||
|
||||
|
|
|
|||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
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@ -0,0 +1,141 @@
|
|||
The PowerPC boot wrapper
|
||||
------------------------
|
||||
Copyright (C) Secret Lab Technologies Ltd.
|
||||
|
||||
PowerPC image targets compresses and wraps the kernel image (vmlinux) with
|
||||
a boot wrapper to make it usable by the system firmware. There is no
|
||||
standard PowerPC firmware interface, so the boot wrapper is designed to
|
||||
be adaptable for each kind of image that needs to be built.
|
||||
|
||||
The boot wrapper can be found in the arch/powerpc/boot/ directory. The
|
||||
Makefile in that directory has targets for all the available image types.
|
||||
The different image types are used to support all of the various firmware
|
||||
interfaces found on PowerPC platforms. OpenFirmware is the most commonly
|
||||
used firmware type on general purpose PowerPC systems from Apple, IBM and
|
||||
others. U-Boot is typically found on embedded PowerPC hardware, but there
|
||||
are a handful of other firmware implementations which are also popular. Each
|
||||
firmware interface requires a different image format.
|
||||
|
||||
The boot wrapper is built from the makefile in arch/powerpc/boot/Makefile and
|
||||
it uses the wrapper script (arch/powerpc/boot/wrapper) to generate target
|
||||
image. The details of the build system is discussed in the next section.
|
||||
Currently, the following image format targets exist:
|
||||
|
||||
cuImage.%: Backwards compatible uImage for older version of
|
||||
U-Boot (for versions that don't understand the device
|
||||
tree). This image embeds a device tree blob inside
|
||||
the image. The boot wrapper, kernel and device tree
|
||||
are all embedded inside the U-Boot uImage file format
|
||||
with boot wrapper code that extracts data from the old
|
||||
bd_info structure and loads the data into the device
|
||||
tree before jumping into the kernel.
|
||||
Because of the series of #ifdefs found in the
|
||||
bd_info structure used in the old U-Boot interfaces,
|
||||
cuImages are platform specific. Each specific
|
||||
U-Boot platform has a different platform init file
|
||||
which populates the embedded device tree with data
|
||||
from the platform specific bd_info file. The platform
|
||||
specific cuImage platform init code can be found in
|
||||
arch/powerpc/boot/cuboot.*.c. Selection of the correct
|
||||
cuImage init code for a specific board can be found in
|
||||
the wrapper structure.
|
||||
dtbImage.%: Similar to zImage, except device tree blob is embedded
|
||||
inside the image instead of provided by firmware. The
|
||||
output image file can be either an elf file or a flat
|
||||
binary depending on the platform.
|
||||
dtbImages are used on systems which do not have an
|
||||
interface for passing a device tree directly.
|
||||
dtbImages are similar to simpleImages except that
|
||||
dtbImages have platform specific code for extracting
|
||||
data from the board firmware, but simpleImages do not
|
||||
talk to the firmware at all.
|
||||
PlayStation 3 support uses dtbImage. So do Embedded
|
||||
Planet boards using the PlanetCore firmware. Board
|
||||
specific initialization code is typically found in a
|
||||
file named arch/powerpc/boot/<platform>.c; but this
|
||||
can be overridden by the wrapper script.
|
||||
simpleImage.%: Firmware independent compressed image that does not
|
||||
depend on any particular firmware interface and embeds
|
||||
a device tree blob. This image is a flat binary that
|
||||
can be loaded to any location in RAM and jumped to.
|
||||
Firmware cannot pass any configuration data to the
|
||||
kernel with this image type and it depends entirely on
|
||||
the embedded device tree for all information.
|
||||
The simpleImage is useful for booting systems with
|
||||
an unknown firmware interface or for booting from
|
||||
a debugger when no firmware is present (such as on
|
||||
the Xilinx Virtex platform). The only assumption that
|
||||
simpleImage makes is that RAM is correctly initialized
|
||||
and that the MMU is either off or has RAM mapped to
|
||||
base address 0.
|
||||
simpleImage also supports inserting special platform
|
||||
specific initialization code to the start of the bootup
|
||||
sequence. The virtex405 platform uses this feature to
|
||||
ensure that the cache is invalidated before caching
|
||||
is enabled. Platform specific initialization code is
|
||||
added as part of the wrapper script and is keyed on
|
||||
the image target name. For example, all
|
||||
simpleImage.virtex405-* targets will add the
|
||||
virtex405-head.S initialization code (This also means
|
||||
that the dts file for virtex405 targets should be
|
||||
named (virtex405-<board>.dts). Search the wrapper
|
||||
script for 'virtex405' and see the file
|
||||
arch/powerpc/boot/virtex405-head.S for details.
|
||||
treeImage.%; Image format for used with OpenBIOS firmware found
|
||||
on some ppc4xx hardware. This image embeds a device
|
||||
tree blob inside the image.
|
||||
uImage: Native image format used by U-Boot. The uImage target
|
||||
does not add any boot code. It just wraps a compressed
|
||||
vmlinux in the uImage data structure. This image
|
||||
requires a version of U-Boot that is able to pass
|
||||
a device tree to the kernel at boot. If using an older
|
||||
version of U-Boot, then you need to use a cuImage
|
||||
instead.
|
||||
zImage.%: Image format which does not embed a device tree.
|
||||
Used by OpenFirmware and other firmware interfaces
|
||||
which are able to supply a device tree. This image
|
||||
expects firmware to provide the device tree at boot.
|
||||
Typically, if you have general purpose PowerPC
|
||||
hardware then you want this image format.
|
||||
|
||||
Image types which embed a device tree blob (simpleImage, dtbImage, treeImage,
|
||||
and cuImage) all generate the device tree blob from a file in the
|
||||
arch/powerpc/boot/dts/ directory. The Makefile selects the correct device
|
||||
tree source based on the name of the target. Therefore, if the kernel is
|
||||
built with 'make treeImage.walnut simpleImage.virtex405-ml403', then the
|
||||
build system will use arch/powerpc/boot/dts/walnut.dts to build
|
||||
treeImage.walnut and arch/powerpc/boot/dts/virtex405-ml403.dts to build
|
||||
the simpleImage.virtex405-ml403.
|
||||
|
||||
Two special targets called 'zImage' and 'zImage.initrd' also exist. These
|
||||
targets build all the default images as selected by the kernel configuration.
|
||||
Default images are selected by the boot wrapper Makefile
|
||||
(arch/powerpc/boot/Makefile) by adding targets to the $image-y variable. Look
|
||||
at the Makefile to see which default image targets are available.
|
||||
|
||||
How it is built
|
||||
---------------
|
||||
arch/powerpc is designed to support multiplatform kernels, which means
|
||||
that a single vmlinux image can be booted on many different target boards.
|
||||
It also means that the boot wrapper must be able to wrap for many kinds of
|
||||
images on a single build. The design decision was made to not use any
|
||||
conditional compilation code (#ifdef, etc) in the boot wrapper source code.
|
||||
All of the boot wrapper pieces are buildable at any time regardless of the
|
||||
kernel configuration. Building all the wrapper bits on every kernel build
|
||||
also ensures that obscure parts of the wrapper are at the very least compile
|
||||
tested in a large variety of environments.
|
||||
|
||||
The wrapper is adapted for different image types at link time by linking in
|
||||
just the wrapper bits that are appropriate for the image type. The 'wrapper
|
||||
script' (found in arch/powerpc/boot/wrapper) is called by the Makefile and
|
||||
is responsible for selecting the correct wrapper bits for the image type.
|
||||
The arguments are well documented in the script's comment block, so they
|
||||
are not repeated here. However, it is worth mentioning that the script
|
||||
uses the -p (platform) argument as the main method of deciding which wrapper
|
||||
bits to compile in. Look for the large 'case "$platform" in' block in the
|
||||
middle of the script. This is also the place where platform specific fixups
|
||||
can be selected by changing the link order.
|
||||
|
||||
In particular, care should be taken when working with cuImages. cuImage
|
||||
wrapper bits are very board specific and care should be taken to make sure
|
||||
the target you are trying to build is supported by the wrapper bits.
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
* Board Control and Status (BCSR)
|
||||
|
||||
Required properties:
|
||||
|
||||
- device_type : Should be "board-control"
|
||||
- reg : Offset and length of the register set for the device
|
||||
|
||||
Example:
|
||||
|
||||
bcsr@f8000000 {
|
||||
device_type = "board-control";
|
||||
reg = <f8000000 8000>;
|
||||
};
|
||||
|
||||
* Freescale on board FPGA
|
||||
|
||||
This is the memory-mapped registers for on board FPGA.
|
||||
|
||||
Required properities:
|
||||
- compatible : should be "fsl,fpga-pixis".
|
||||
- reg : should contain the address and the lenght of the FPPGA register
|
||||
set.
|
||||
|
||||
Example (MPC8610HPCD):
|
||||
|
||||
board-control@e8000000 {
|
||||
compatible = "fsl,fpga-pixis";
|
||||
reg = <0xe8000000 32>;
|
||||
};
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
* Freescale Communications Processor Module
|
||||
|
||||
NOTE: This is an interim binding, and will likely change slightly,
|
||||
as more devices are supported. The QE bindings especially are
|
||||
incomplete.
|
||||
|
||||
* Root CPM node
|
||||
|
||||
Properties:
|
||||
- compatible : "fsl,cpm1", "fsl,cpm2", or "fsl,qe".
|
||||
- reg : A 48-byte region beginning with CPCR.
|
||||
|
||||
Example:
|
||||
cpm@119c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
|
||||
reg = <119c0 30>;
|
||||
}
|
||||
|
||||
* Properties common to mulitple CPM/QE devices
|
||||
|
||||
- fsl,cpm-command : This value is ORed with the opcode and command flag
|
||||
to specify the device on which a CPM command operates.
|
||||
|
||||
- fsl,cpm-brg : Indicates which baud rate generator the device
|
||||
is associated with. If absent, an unused BRG
|
||||
should be dynamically allocated. If zero, the
|
||||
device uses an external clock rather than a BRG.
|
||||
|
||||
- reg : Unless otherwise specified, the first resource represents the
|
||||
scc/fcc/ucc registers, and the second represents the device's
|
||||
parameter RAM region (if it has one).
|
||||
|
||||
* Multi-User RAM (MURAM)
|
||||
|
||||
The multi-user/dual-ported RAM is expressed as a bus under the CPM node.
|
||||
|
||||
Ranges must be set up subject to the following restrictions:
|
||||
|
||||
- Children's reg nodes must be offsets from the start of all muram, even
|
||||
if the user-data area does not begin at zero.
|
||||
- If multiple range entries are used, the difference between the parent
|
||||
address and the child address must be the same in all, so that a single
|
||||
mapping can cover them all while maintaining the ability to determine
|
||||
CPM-side offsets with pointer subtraction. It is recommended that
|
||||
multiple range entries not be used.
|
||||
- A child address of zero must be translatable, even if no reg resources
|
||||
contain it.
|
||||
|
||||
A child "data" node must exist, compatible with "fsl,cpm-muram-data", to
|
||||
indicate the portion of muram that is usable by the OS for arbitrary
|
||||
purposes. The data node may have an arbitrary number of reg resources,
|
||||
all of which contribute to the allocatable muram pool.
|
||||
|
||||
Example, based on mpc8272:
|
||||
muram@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 10000>;
|
||||
|
||||
data@0 {
|
||||
compatible = "fsl,cpm-muram-data";
|
||||
reg = <0 2000 9800 800>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
* Baud Rate Generators
|
||||
|
||||
Currently defined compatibles:
|
||||
fsl,cpm-brg
|
||||
fsl,cpm1-brg
|
||||
fsl,cpm2-brg
|
||||
|
||||
Properties:
|
||||
- reg : There may be an arbitrary number of reg resources; BRG
|
||||
numbers are assigned to these in order.
|
||||
- clock-frequency : Specifies the base frequency driving
|
||||
the BRG.
|
||||
|
||||
Example:
|
||||
brg@119f0 {
|
||||
compatible = "fsl,mpc8272-brg",
|
||||
"fsl,cpm2-brg",
|
||||
"fsl,cpm-brg";
|
||||
reg = <119f0 10 115f0 10>;
|
||||
clock-frequency = <d#25000000>;
|
||||
};
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
* I2C
|
||||
|
||||
The I2C controller is expressed as a bus under the CPM node.
|
||||
|
||||
Properties:
|
||||
- compatible : "fsl,cpm1-i2c", "fsl,cpm2-i2c"
|
||||
- reg : On CPM2 devices, the second resource doesn't specify the I2C
|
||||
Parameter RAM itself, but the I2C_BASE field of the CPM2 Parameter RAM
|
||||
(typically 0x8afc 0x2).
|
||||
- #address-cells : Should be one. The cell is the i2c device address with
|
||||
the r/w bit set to zero.
|
||||
- #size-cells : Should be zero.
|
||||
- clock-frequency : Can be used to set the i2c clock frequency. If
|
||||
unspecified, a default frequency of 60kHz is being used.
|
||||
The following two properties are deprecated. They are only used by legacy
|
||||
i2c drivers to find the bus to probe:
|
||||
- linux,i2c-index : Can be used to hard code an i2c bus number. By default,
|
||||
the bus number is dynamically assigned by the i2c core.
|
||||
- linux,i2c-class : Can be used to override the i2c class. The class is used
|
||||
by legacy i2c device drivers to find a bus in a specific context like
|
||||
system management, video or sound. By default, I2C_CLASS_HWMON (1) is
|
||||
being used. The definition of the classes can be found in
|
||||
include/i2c/i2c.h
|
||||
|
||||
Example, based on mpc823:
|
||||
|
||||
i2c@860 {
|
||||
compatible = "fsl,mpc823-i2c",
|
||||
"fsl,cpm1-i2c";
|
||||
reg = <0x860 0x20 0x3c80 0x30>;
|
||||
interrupts = <16>;
|
||||
interrupt-parent = <&CPM_PIC>;
|
||||
fsl,cpm-command = <0x10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1307";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
* Interrupt Controllers
|
||||
|
||||
Currently defined compatibles:
|
||||
- fsl,cpm1-pic
|
||||
- only one interrupt cell
|
||||
- fsl,pq1-pic
|
||||
- fsl,cpm2-pic
|
||||
- second interrupt cell is level/sense:
|
||||
- 2 is falling edge
|
||||
- 8 is active low
|
||||
|
||||
Example:
|
||||
interrupt-controller@10c00 {
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
reg = <10c00 80>;
|
||||
compatible = "mpc8272-pic", "fsl,cpm2-pic";
|
||||
};
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
* USB (Universal Serial Bus Controller)
|
||||
|
||||
Properties:
|
||||
- compatible : "fsl,cpm1-usb", "fsl,cpm2-usb", "fsl,qe-usb"
|
||||
|
||||
Example:
|
||||
usb@11bc0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,cpm2-usb";
|
||||
reg = <11b60 18 8b00 100>;
|
||||
interrupts = <b 8>;
|
||||
interrupt-parent = <&PIC>;
|
||||
fsl,cpm-command = <2e600000>;
|
||||
};
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
* Network
|
||||
|
||||
Currently defined compatibles:
|
||||
- fsl,cpm1-scc-enet
|
||||
- fsl,cpm2-scc-enet
|
||||
- fsl,cpm1-fec-enet
|
||||
- fsl,cpm2-fcc-enet (third resource is GFEMR)
|
||||
- fsl,qe-enet
|
||||
|
||||
Example:
|
||||
|
||||
ethernet@11300 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc8272-fcc-enet",
|
||||
"fsl,cpm2-fcc-enet";
|
||||
reg = <11300 20 8400 100 11390 1>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <20 8>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy-handle = <&PHY0>;
|
||||
fsl,cpm-command = <12000300>;
|
||||
};
|
||||
|
||||
* MDIO
|
||||
|
||||
Currently defined compatibles:
|
||||
fsl,pq1-fec-mdio (reg is same as first resource of FEC device)
|
||||
fsl,cpm2-mdio-bitbang (reg is port C registers)
|
||||
|
||||
Properties for fsl,cpm2-mdio-bitbang:
|
||||
fsl,mdio-pin : pin of port C controlling mdio data
|
||||
fsl,mdc-pin : pin of port C controlling mdio clock
|
||||
|
||||
Example:
|
||||
mdio@10d40 {
|
||||
device_type = "mdio";
|
||||
compatible = "fsl,mpc8272ads-mdio-bitbang",
|
||||
"fsl,mpc8272-mdio-bitbang",
|
||||
"fsl,cpm2-mdio-bitbang";
|
||||
reg = <10d40 14>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
fsl,mdio-pin = <12>;
|
||||
fsl,mdc-pin = <13>;
|
||||
};
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
* Freescale QUICC Engine module (QE)
|
||||
This represents qe module that is installed on PowerQUICC II Pro.
|
||||
|
||||
NOTE: This is an interim binding; it should be updated to fit
|
||||
in with the CPM binding later in this document.
|
||||
|
||||
Basically, it is a bus of devices, that could act more or less
|
||||
as a complete entity (UCC, USB etc ). All of them should be siblings on
|
||||
the "root" qe node, using the common properties from there.
|
||||
The description below applies to the qe of MPC8360 and
|
||||
more nodes and properties would be extended in the future.
|
||||
|
||||
i) Root QE device
|
||||
|
||||
Required properties:
|
||||
- compatible : should be "fsl,qe";
|
||||
- model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
|
||||
- reg : offset and length of the device registers.
|
||||
- bus-frequency : the clock frequency for QUICC Engine.
|
||||
|
||||
Recommended properties
|
||||
- brg-frequency : the internal clock source frequency for baud-rate
|
||||
generators in Hz.
|
||||
|
||||
Example:
|
||||
qe@e0100000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "fsl,qe";
|
||||
ranges = <0 e0100000 00100000>;
|
||||
reg = <e0100000 480>;
|
||||
brg-frequency = <0>;
|
||||
bus-frequency = <179A7B00>;
|
||||
}
|
||||
|
||||
* Multi-User RAM (MURAM)
|
||||
|
||||
Required properties:
|
||||
- compatible : should be "fsl,qe-muram", "fsl,cpm-muram".
|
||||
- mode : the could be "host" or "slave".
|
||||
- ranges : Should be defined as specified in 1) to describe the
|
||||
translation of MURAM addresses.
|
||||
- data-only : sub-node which defines the address area under MURAM
|
||||
bus that can be allocated as data/parameter
|
||||
|
||||
Example:
|
||||
|
||||
muram@10000 {
|
||||
compatible = "fsl,qe-muram", "fsl,cpm-muram";
|
||||
ranges = <0 00010000 0000c000>;
|
||||
|
||||
data-only@0{
|
||||
compatible = "fsl,qe-muram-data",
|
||||
"fsl,cpm-muram-data";
|
||||
reg = <0 c000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
* Uploaded QE firmware
|
||||
|
||||
If a new firwmare has been uploaded to the QE (usually by the
|
||||
boot loader), then a 'firmware' child node should be added to the QE
|
||||
node. This node provides information on the uploaded firmware that
|
||||
device drivers may need.
|
||||
|
||||
Required properties:
|
||||
- id: The string name of the firmware. This is taken from the 'id'
|
||||
member of the qe_firmware structure of the uploaded firmware.
|
||||
Device drivers can search this string to determine if the
|
||||
firmware they want is already present.
|
||||
- extended-modes: The Extended Modes bitfield, taken from the
|
||||
firmware binary. It is a 64-bit number represented
|
||||
as an array of two 32-bit numbers.
|
||||
- virtual-traps: The virtual traps, taken from the firmware binary.
|
||||
It is an array of 8 32-bit numbers.
|
||||
|
||||
Example:
|
||||
firmware {
|
||||
id = "Soft-UART";
|
||||
extended-modes = <0 0>;
|
||||
virtual-traps = <0 0 0 0 0 0 0 0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
* Parallel I/O Ports
|
||||
|
||||
This node configures Parallel I/O ports for CPUs with QE support.
|
||||
The node should reside in the "soc" node of the tree. For each
|
||||
device that using parallel I/O ports, a child node should be created.
|
||||
See the definition of the Pin configuration nodes below for more
|
||||
information.
|
||||
|
||||
Required properties:
|
||||
- device_type : should be "par_io".
|
||||
- reg : offset to the register set and its length.
|
||||
- num-ports : number of Parallel I/O ports
|
||||
|
||||
Example:
|
||||
par_io@1400 {
|
||||
reg = <1400 100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
device_type = "par_io";
|
||||
num-ports = <7>;
|
||||
ucc_pin@01 {
|
||||
......
|
||||
};
|
||||
|
||||
Note that "par_io" nodes are obsolete, and should not be used for
|
||||
the new device trees. Instead, each Par I/O bank should be represented
|
||||
via its own gpio-controller node:
|
||||
|
||||
Required properties:
|
||||
- #gpio-cells : should be "2".
|
||||
- compatible : should be "fsl,<chip>-qe-pario-bank",
|
||||
"fsl,mpc8323-qe-pario-bank".
|
||||
- reg : offset to the register set and its length.
|
||||
- gpio-controller : node to identify gpio controllers.
|
||||
|
||||
Example:
|
||||
qe_pio_a: gpio-controller@1400 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,mpc8360-qe-pario-bank",
|
||||
"fsl,mpc8323-qe-pario-bank";
|
||||
reg = <0x1400 0x18>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
qe_pio_e: gpio-controller@1460 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,mpc8360-qe-pario-bank",
|
||||
"fsl,mpc8323-qe-pario-bank";
|
||||
reg = <0x1460 0x18>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
* Pin configuration nodes
|
||||
|
||||
Required properties:
|
||||
- linux,phandle : phandle of this node; likely referenced by a QE
|
||||
device.
|
||||
- pio-map : array of pin configurations. Each pin is defined by 6
|
||||
integers. The six numbers are respectively: port, pin, dir,
|
||||
open_drain, assignment, has_irq.
|
||||
- port : port number of the pin; 0-6 represent port A-G in UM.
|
||||
- pin : pin number in the port.
|
||||
- dir : direction of the pin, should encode as follows:
|
||||
|
||||
0 = The pin is disabled
|
||||
1 = The pin is an output
|
||||
2 = The pin is an input
|
||||
3 = The pin is I/O
|
||||
|
||||
- open_drain : indicates the pin is normal or wired-OR:
|
||||
|
||||
0 = The pin is actively driven as an output
|
||||
1 = The pin is an open-drain driver. As an output, the pin is
|
||||
driven active-low, otherwise it is three-stated.
|
||||
|
||||
- assignment : function number of the pin according to the Pin Assignment
|
||||
tables in User Manual. Each pin can have up to 4 possible functions in
|
||||
QE and two options for CPM.
|
||||
- has_irq : indicates if the pin is used as source of external
|
||||
interrupts.
|
||||
|
||||
Example:
|
||||
ucc_pin@01 {
|
||||
linux,phandle = <140001>;
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
0 3 1 0 1 0 /* TxD0 */
|
||||
0 4 1 0 1 0 /* TxD1 */
|
||||
0 5 1 0 1 0 /* TxD2 */
|
||||
0 6 1 0 1 0 /* TxD3 */
|
||||
1 6 1 0 3 0 /* TxD4 */
|
||||
1 7 1 0 1 0 /* TxD5 */
|
||||
1 9 1 0 2 0 /* TxD6 */
|
||||
1 a 1 0 2 0 /* TxD7 */
|
||||
0 9 2 0 1 0 /* RxD0 */
|
||||
0 a 2 0 1 0 /* RxD1 */
|
||||
0 b 2 0 1 0 /* RxD2 */
|
||||
0 c 2 0 1 0 /* RxD3 */
|
||||
0 d 2 0 1 0 /* RxD4 */
|
||||
1 1 2 0 2 0 /* RxD5 */
|
||||
1 0 2 0 2 0 /* RxD6 */
|
||||
1 4 2 0 2 0 /* RxD7 */
|
||||
0 7 1 0 1 0 /* TX_EN */
|
||||
0 8 1 0 1 0 /* TX_ER */
|
||||
0 f 2 0 1 0 /* RX_DV */
|
||||
0 10 2 0 1 0 /* RX_ER */
|
||||
0 0 2 0 1 0 /* RX_CLK */
|
||||
2 9 1 0 3 0 /* GTX_CLK - CLK10 */
|
||||
2 8 2 0 1 0>; /* GTX125 - CLK9 */
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
* UCC (Unified Communications Controllers)
|
||||
|
||||
Required properties:
|
||||
- device_type : should be "network", "hldc", "uart", "transparent"
|
||||
"bisync", "atm", or "serial".
|
||||
- compatible : could be "ucc_geth" or "fsl_atm" and so on.
|
||||
- cell-index : the ucc number(1-8), corresponding to UCCx in UM.
|
||||
- reg : Offset and length of the register set for the device
|
||||
- interrupts : <a b> where a is the interrupt number and b is a
|
||||
field that represents an encoding of the sense and level
|
||||
information for the interrupt. This should be encoded based on
|
||||
the information in section 2) depending on the type of interrupt
|
||||
controller you have.
|
||||
- interrupt-parent : the phandle for the interrupt controller that
|
||||
services interrupts for this device.
|
||||
- pio-handle : The phandle for the Parallel I/O port configuration.
|
||||
- port-number : for UART drivers, the port number to use, between 0 and 3.
|
||||
This usually corresponds to the /dev/ttyQE device, e.g. <0> = /dev/ttyQE0.
|
||||
The port number is added to the minor number of the device. Unlike the
|
||||
CPM UART driver, the port-number is required for the QE UART driver.
|
||||
- soft-uart : for UART drivers, if specified this means the QE UART device
|
||||
driver should use "Soft-UART" mode, which is needed on some SOCs that have
|
||||
broken UART hardware. Soft-UART is provided via a microcode upload.
|
||||
- rx-clock-name: the UCC receive clock source
|
||||
"none": clock source is disabled
|
||||
"brg1" through "brg16": clock source is BRG1-BRG16, respectively
|
||||
"clk1" through "clk24": clock source is CLK1-CLK24, respectively
|
||||
- tx-clock-name: the UCC transmit clock source
|
||||
"none": clock source is disabled
|
||||
"brg1" through "brg16": clock source is BRG1-BRG16, respectively
|
||||
"clk1" through "clk24": clock source is CLK1-CLK24, respectively
|
||||
The following two properties are deprecated. rx-clock has been replaced
|
||||
with rx-clock-name, and tx-clock has been replaced with tx-clock-name.
|
||||
Drivers that currently use the deprecated properties should continue to
|
||||
do so, in order to support older device trees, but they should be updated
|
||||
to check for the new properties first.
|
||||
- rx-clock : represents the UCC receive clock source.
|
||||
0x00 : clock source is disabled;
|
||||
0x1~0x10 : clock source is BRG1~BRG16 respectively;
|
||||
0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
|
||||
- tx-clock: represents the UCC transmit clock source;
|
||||
0x00 : clock source is disabled;
|
||||
0x1~0x10 : clock source is BRG1~BRG16 respectively;
|
||||
0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
|
||||
|
||||
Required properties for network device_type:
|
||||
- mac-address : list of bytes representing the ethernet address.
|
||||
- phy-handle : The phandle for the PHY connected to this controller.
|
||||
|
||||
Recommended properties:
|
||||
- phy-connection-type : a string naming the controller/PHY interface type,
|
||||
i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id" (Internal
|
||||
Delay), "rgmii-txid" (delay on TX only), "rgmii-rxid" (delay on RX only),
|
||||
"tbi", or "rtbi".
|
||||
|
||||
Example:
|
||||
ucc@2000 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <1>;
|
||||
reg = <2000 200>;
|
||||
interrupts = <a0 0>;
|
||||
interrupt-parent = <700>;
|
||||
mac-address = [ 00 04 9f 00 23 23 ];
|
||||
rx-clock = "none";
|
||||
tx-clock = "clk9";
|
||||
phy-handle = <212000>;
|
||||
phy-connection-type = "gmii";
|
||||
pio-handle = <140001>;
|
||||
};
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
* USB (Universal Serial Bus Controller)
|
||||
|
||||
Required properties:
|
||||
- compatible : could be "qe_udc" or "fhci-hcd".
|
||||
- mode : the could be "host" or "slave".
|
||||
- reg : Offset and length of the register set for the device
|
||||
- interrupts : <a b> where a is the interrupt number and b is a
|
||||
field that represents an encoding of the sense and level
|
||||
information for the interrupt. This should be encoded based on
|
||||
the information in section 2) depending on the type of interrupt
|
||||
controller you have.
|
||||
- interrupt-parent : the phandle for the interrupt controller that
|
||||
services interrupts for this device.
|
||||
|
||||
Example(slave):
|
||||
usb@6c0 {
|
||||
compatible = "qe_udc";
|
||||
reg = <6c0 40>;
|
||||
interrupts = <8b 0>;
|
||||
interrupt-parent = <700>;
|
||||
mode = "slave";
|
||||
};
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
* Serial
|
||||
|
||||
Currently defined compatibles:
|
||||
- fsl,cpm1-smc-uart
|
||||
- fsl,cpm2-smc-uart
|
||||
- fsl,cpm1-scc-uart
|
||||
- fsl,cpm2-scc-uart
|
||||
- fsl,qe-uart
|
||||
|
||||
Example:
|
||||
|
||||
serial@11a00 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc8272-scc-uart",
|
||||
"fsl,cpm2-scc-uart";
|
||||
reg = <11a00 20 8000 100>;
|
||||
interrupts = <28 8>;
|
||||
interrupt-parent = <&PIC>;
|
||||
fsl,cpm-brg = <1>;
|
||||
fsl,cpm-command = <00800000>;
|
||||
};
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
* Freescale Display Interface Unit
|
||||
|
||||
The Freescale DIU is a LCD controller, with proper hardware, it can also
|
||||
drive DVI monitors.
|
||||
|
||||
Required properties:
|
||||
- compatible : should be "fsl-diu".
|
||||
- reg : should contain at least address and length of the DIU register
|
||||
set.
|
||||
- Interrupts : one DIU interrupt should be describe here.
|
||||
|
||||
Example (MPC8610HPCD):
|
||||
display@2c000 {
|
||||
compatible = "fsl,diu";
|
||||
reg = <0x2c000 100>;
|
||||
interrupts = <72 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
|
@ -0,0 +1,127 @@
|
|||
* Freescale 83xx DMA Controller
|
||||
|
||||
Freescale PowerPC 83xx have on chip general purpose DMA controllers.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : compatible list, contains 2 entries, first is
|
||||
"fsl,CHIP-dma", where CHIP is the processor
|
||||
(mpc8349, mpc8360, etc.) and the second is
|
||||
"fsl,elo-dma"
|
||||
- reg : <registers mapping for DMA general status reg>
|
||||
- ranges : Should be defined as specified in 1) to describe the
|
||||
DMA controller channels.
|
||||
- cell-index : controller index. 0 for controller @ 0x8100
|
||||
- interrupts : <interrupt mapping for DMA IRQ>
|
||||
- interrupt-parent : optional, if needed for interrupt mapping
|
||||
|
||||
|
||||
- DMA channel nodes:
|
||||
- compatible : compatible list, contains 2 entries, first is
|
||||
"fsl,CHIP-dma-channel", where CHIP is the processor
|
||||
(mpc8349, mpc8350, etc.) and the second is
|
||||
"fsl,elo-dma-channel"
|
||||
- reg : <registers mapping for channel>
|
||||
- cell-index : dma channel index starts at 0.
|
||||
|
||||
Optional properties:
|
||||
- interrupts : <interrupt mapping for DMA channel IRQ>
|
||||
(on 83xx this is expected to be identical to
|
||||
the interrupts property of the parent node)
|
||||
- interrupt-parent : optional, if needed for interrupt mapping
|
||||
|
||||
Example:
|
||||
dma@82a8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
|
||||
reg = <82a8 4>;
|
||||
ranges = <0 8100 1a4>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <47 8>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
||||
cell-index = <0>;
|
||||
reg = <0 80>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
||||
cell-index = <1>;
|
||||
reg = <80 80>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
||||
cell-index = <2>;
|
||||
reg = <100 80>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
||||
cell-index = <3>;
|
||||
reg = <180 80>;
|
||||
};
|
||||
};
|
||||
|
||||
* Freescale 85xx/86xx DMA Controller
|
||||
|
||||
Freescale PowerPC 85xx/86xx have on chip general purpose DMA controllers.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : compatible list, contains 2 entries, first is
|
||||
"fsl,CHIP-dma", where CHIP is the processor
|
||||
(mpc8540, mpc8540, etc.) and the second is
|
||||
"fsl,eloplus-dma"
|
||||
- reg : <registers mapping for DMA general status reg>
|
||||
- cell-index : controller index. 0 for controller @ 0x21000,
|
||||
1 for controller @ 0xc000
|
||||
- ranges : Should be defined as specified in 1) to describe the
|
||||
DMA controller channels.
|
||||
|
||||
- DMA channel nodes:
|
||||
- compatible : compatible list, contains 2 entries, first is
|
||||
"fsl,CHIP-dma-channel", where CHIP is the processor
|
||||
(mpc8540, mpc8560, etc.) and the second is
|
||||
"fsl,eloplus-dma-channel"
|
||||
- cell-index : dma channel index starts at 0.
|
||||
- reg : <registers mapping for channel>
|
||||
- interrupts : <interrupt mapping for DMA channel IRQ>
|
||||
- interrupt-parent : optional, if needed for interrupt mapping
|
||||
|
||||
Example:
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
|
||||
reg = <21300 4>;
|
||||
ranges = <0 21100 200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
|
||||
reg = <0 80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <14 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
|
||||
reg = <80 80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <15 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
|
||||
reg = <100 80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
|
||||
reg = <180 80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <17 2>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
* Freescale General-purpose Timers Module
|
||||
|
||||
Required properties:
|
||||
- compatible : should be
|
||||
"fsl,<chip>-gtm", "fsl,gtm" for SOC GTMs
|
||||
"fsl,<chip>-qe-gtm", "fsl,qe-gtm", "fsl,gtm" for QE GTMs
|
||||
"fsl,<chip>-cpm2-gtm", "fsl,cpm2-gtm", "fsl,gtm" for CPM2 GTMs
|
||||
- reg : should contain gtm registers location and length (0x40).
|
||||
- interrupts : should contain four interrupts.
|
||||
- interrupt-parent : interrupt source phandle.
|
||||
- clock-frequency : specifies the frequency driving the timer.
|
||||
|
||||
Example:
|
||||
|
||||
timer@500 {
|
||||
compatible = "fsl,mpc8360-gtm", "fsl,gtm";
|
||||
reg = <0x500 0x40>;
|
||||
interrupts = <90 8 78 8 84 8 72 8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
/* filled by u-boot */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
timer@440 {
|
||||
compatible = "fsl,mpc8360-qe-gtm", "fsl,qe-gtm", "fsl,gtm";
|
||||
reg = <0x440 0x40>;
|
||||
interrupts = <12 13 14 15>;
|
||||
interrupt-parent = <&qeic>;
|
||||
/* filled by u-boot */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
* Global Utilities Block
|
||||
|
||||
The global utilities block controls power management, I/O device
|
||||
enabling, power-on-reset configuration monitoring, general-purpose
|
||||
I/O signal configuration, alternate function selection for multiplexed
|
||||
signals, and clock control.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Should define the compatible device type for
|
||||
global-utilities.
|
||||
- reg : Offset and length of the register set for the device.
|
||||
|
||||
Recommended properties:
|
||||
|
||||
- fsl,has-rstcr : Indicates that the global utilities register set
|
||||
contains a functioning "reset control register" (i.e. the board
|
||||
is wired to reset upon setting the HRESET_REQ bit in this register).
|
||||
|
||||
Example:
|
||||
global-utilities@e0000 { /* global utilities block */
|
||||
compatible = "fsl,mpc8548-guts";
|
||||
reg = <e0000 1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
* I2C
|
||||
|
||||
Required properties :
|
||||
|
||||
- device_type : Should be "i2c"
|
||||
- reg : Offset and length of the register set for the device
|
||||
|
||||
Recommended properties :
|
||||
|
||||
- compatible : Should be "fsl-i2c" for parts compatible with
|
||||
Freescale I2C specifications.
|
||||
- interrupts : <a b> where a is the interrupt number and b is a
|
||||
field that represents an encoding of the sense and level
|
||||
information for the interrupt. This should be encoded based on
|
||||
the information in section 2) depending on the type of interrupt
|
||||
controller you have.
|
||||
- interrupt-parent : the phandle for the interrupt controller that
|
||||
services interrupts for this device.
|
||||
- dfsrr : boolean; if defined, indicates that this I2C device has
|
||||
a digital filter sampling rate register
|
||||
- fsl5200-clocking : boolean; if defined, indicated that this device
|
||||
uses the FSL 5200 clocking mechanism.
|
||||
|
||||
Example :
|
||||
i2c@3000 {
|
||||
interrupt-parent = <40000>;
|
||||
interrupts = <1b 3>;
|
||||
reg = <3000 18>;
|
||||
device_type = "i2c";
|
||||
compatible = "fsl-i2c";
|
||||
dfsrr;
|
||||
};
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
* Chipselect/Local Bus
|
||||
|
||||
Properties:
|
||||
- name : Should be localbus
|
||||
- #address-cells : Should be either two or three. The first cell is the
|
||||
chipselect number, and the remaining cells are the
|
||||
offset into the chipselect.
|
||||
- #size-cells : Either one or two, depending on how large each chipselect
|
||||
can be.
|
||||
- ranges : Each range corresponds to a single chipselect, and cover
|
||||
the entire access window as configured.
|
||||
|
||||
Example:
|
||||
localbus@f0010100 {
|
||||
compatible = "fsl,mpc8272-localbus",
|
||||
"fsl,pq2-localbus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <f0010100 40>;
|
||||
|
||||
ranges = <0 0 fe000000 02000000
|
||||
1 0 f4500000 00008000>;
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "jedec-flash";
|
||||
reg = <0 0 2000000>;
|
||||
bank-width = <4>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
||||
board-control@1,0 {
|
||||
reg = <1 0 20>;
|
||||
compatible = "fsl,mpc8272ads-bcsr";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
* Freescale MSI interrupt controller
|
||||
|
||||
Reguired properities:
|
||||
- compatible : compatible list, contains 2 entries,
|
||||
first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
|
||||
etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on
|
||||
the parent type.
|
||||
- reg : should contain the address and the length of the shared message
|
||||
interrupt register set.
|
||||
- msi-available-ranges: use <start count> style section to define which
|
||||
msi interrupt can be used in the 256 msi interrupts. This property is
|
||||
optional, without this, all the 256 MSI interrupts can be used.
|
||||
- interrupts : each one of the interrupts here is one entry per 32 MSIs,
|
||||
and routed to the host interrupt controller. the interrupts should
|
||||
be set as edge sensitive.
|
||||
- interrupt-parent: the phandle for the interrupt controller
|
||||
that services interrupts for this device. for 83xx cpu, the interrupts
|
||||
are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed
|
||||
to MPIC.
|
||||
|
||||
Example:
|
||||
msi@41600 {
|
||||
compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0
|
||||
0xe4 0
|
||||
0xe5 0
|
||||
0xe6 0
|
||||
0xe7 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
* Freescale 8xxx/3.0 Gb/s SATA nodes
|
||||
|
||||
SATA nodes are defined to describe on-chip Serial ATA controllers.
|
||||
Each SATA port should have its own node.
|
||||
|
||||
Required properties:
|
||||
- compatible : compatible list, contains 2 entries, first is
|
||||
"fsl,CHIP-sata", where CHIP is the processor
|
||||
(mpc8315, mpc8379, etc.) and the second is
|
||||
"fsl,pq-sata"
|
||||
- interrupts : <interrupt mapping for SATA IRQ>
|
||||
- cell-index : controller index.
|
||||
1 for controller @ 0x18000
|
||||
2 for controller @ 0x19000
|
||||
3 for controller @ 0x1a000
|
||||
4 for controller @ 0x1b000
|
||||
|
||||
Optional properties:
|
||||
- interrupt-parent : optional, if needed for interrupt mapping
|
||||
- reg : <registers mapping>
|
||||
|
||||
Example:
|
||||
sata@18000 {
|
||||
compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
|
||||
reg = <0x18000 0x1000>;
|
||||
cell-index = <1>;
|
||||
interrupts = <2c 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
};
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
Freescale SoC SEC Security Engines
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Should contain entries for this and backward compatible
|
||||
SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0"
|
||||
- reg : Offset and length of the register set for the device
|
||||
- interrupts : the SEC's interrupt number
|
||||
- fsl,num-channels : An integer representing the number of channels
|
||||
available.
|
||||
- fsl,channel-fifo-len : An integer representing the number of
|
||||
descriptor pointers each channel fetch fifo can hold.
|
||||
- fsl,exec-units-mask : The bitmask representing what execution units
|
||||
(EUs) are available. It's a single 32-bit cell. EU information
|
||||
should be encoded following the SEC's Descriptor Header Dword
|
||||
EU_SEL0 field documentation, i.e. as follows:
|
||||
|
||||
bit 0 = reserved - should be 0
|
||||
bit 1 = set if SEC has the ARC4 EU (AFEU)
|
||||
bit 2 = set if SEC has the DES/3DES EU (DEU)
|
||||
bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A)
|
||||
bit 4 = set if SEC has the random number generator EU (RNG)
|
||||
bit 5 = set if SEC has the public key EU (PKEU)
|
||||
bit 6 = set if SEC has the AES EU (AESU)
|
||||
bit 7 = set if SEC has the Kasumi EU (KEU)
|
||||
bit 8 = set if SEC has the CRC EU (CRCU)
|
||||
bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B)
|
||||
|
||||
remaining bits are reserved for future SEC EUs.
|
||||
|
||||
- fsl,descriptor-types-mask : The bitmask representing what descriptors
|
||||
are available. It's a single 32-bit cell. Descriptor type information
|
||||
should be encoded following the SEC's Descriptor Header Dword DESC_TYPE
|
||||
field documentation, i.e. as follows:
|
||||
|
||||
bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type
|
||||
bit 1 = set if SEC supports the ipsec_esp descriptor type
|
||||
bit 2 = set if SEC supports the common_nonsnoop desc. type
|
||||
bit 3 = set if SEC supports the 802.11i AES ccmp desc. type
|
||||
bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type
|
||||
bit 5 = set if SEC supports the srtp descriptor type
|
||||
bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type
|
||||
bit 7 = set if SEC supports the pkeu_assemble descriptor type
|
||||
bit 8 = set if SEC supports the aesu_key_expand_output desc.type
|
||||
bit 9 = set if SEC supports the pkeu_ptmul descriptor type
|
||||
bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type
|
||||
bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type
|
||||
|
||||
..and so on and so forth.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- interrupt-parent : the phandle for the interrupt controller that
|
||||
services interrupts for this device.
|
||||
|
||||
Example:
|
||||
|
||||
/* MPC8548E */
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <29 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0xfe>;
|
||||
fsl,descriptor-types-mask = <0x12b0ebf>;
|
||||
};
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
* SPI (Serial Peripheral Interface)
|
||||
|
||||
Required properties:
|
||||
- cell-index : SPI controller index.
|
||||
- compatible : should be "fsl,spi".
|
||||
- mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
|
||||
- reg : Offset and length of the register set for the device
|
||||
- interrupts : <a b> where a is the interrupt number and b is a
|
||||
field that represents an encoding of the sense and level
|
||||
information for the interrupt. This should be encoded based on
|
||||
the information in section 2) depending on the type of interrupt
|
||||
controller you have.
|
||||
- interrupt-parent : the phandle for the interrupt controller that
|
||||
services interrupts for this device.
|
||||
|
||||
Example:
|
||||
spi@4c0 {
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <4c0 40>;
|
||||
interrupts = <82 0>;
|
||||
interrupt-parent = <700>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
Freescale Synchronous Serial Interface
|
||||
|
||||
The SSI is a serial device that communicates with audio codecs. It can
|
||||
be programmed in AC97, I2S, left-justified, or right-justified modes.
|
||||
|
||||
Required properties:
|
||||
- compatible : compatible list, containing "fsl,ssi"
|
||||
- cell-index : the SSI, <0> = SSI1, <1> = SSI2, and so on
|
||||
- reg : offset and length of the register set for the device
|
||||
- interrupts : <a b> where a is the interrupt number and b is a
|
||||
field that represents an encoding of the sense and
|
||||
level information for the interrupt. This should be
|
||||
encoded based on the information in section 2)
|
||||
depending on the type of interrupt controller you
|
||||
have.
|
||||
- interrupt-parent : the phandle for the interrupt controller that
|
||||
services interrupts for this device.
|
||||
- fsl,mode : the operating mode for the SSI interface
|
||||
"i2s-slave" - I2S mode, SSI is clock slave
|
||||
"i2s-master" - I2S mode, SSI is clock master
|
||||
"lj-slave" - left-justified mode, SSI is clock slave
|
||||
"lj-master" - l.j. mode, SSI is clock master
|
||||
"rj-slave" - right-justified mode, SSI is clock slave
|
||||
"rj-master" - r.j., SSI is clock master
|
||||
"ac97-slave" - AC97 mode, SSI is clock slave
|
||||
"ac97-master" - AC97 mode, SSI is clock master
|
||||
|
||||
Optional properties:
|
||||
- codec-handle : phandle to a 'codec' node that defines an audio
|
||||
codec connected to this SSI. This node is typically
|
||||
a child of an I2C or other control node.
|
||||
|
||||
Child 'codec' node required properties:
|
||||
- compatible : compatible list, contains the name of the codec
|
||||
|
||||
Child 'codec' node optional properties:
|
||||
- clock-frequency : The frequency of the input clock, which typically
|
||||
comes from an on-board dedicated oscillator.
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
* MDIO IO device
|
||||
|
||||
The MDIO is a bus to which the PHY devices are connected. For each
|
||||
device that exists on this bus, a child node should be created. See
|
||||
the definition of the PHY node below for an example of how to define
|
||||
a PHY.
|
||||
|
||||
Required properties:
|
||||
- reg : Offset and length of the register set for the device
|
||||
- compatible : Should define the compatible device type for the
|
||||
mdio. Currently, this is most likely to be "fsl,gianfar-mdio"
|
||||
|
||||
Example:
|
||||
|
||||
mdio@24520 {
|
||||
reg = <24520 20>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
|
||||
ethernet-phy@0 {
|
||||
......
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
* Gianfar-compatible ethernet nodes
|
||||
|
||||
Required properties:
|
||||
|
||||
- device_type : Should be "network"
|
||||
- model : Model of the device. Can be "TSEC", "eTSEC", or "FEC"
|
||||
- compatible : Should be "gianfar"
|
||||
- reg : Offset and length of the register set for the device
|
||||
- mac-address : List of bytes representing the ethernet address of
|
||||
this controller
|
||||
- interrupts : <a b> where a is the interrupt number and b is a
|
||||
field that represents an encoding of the sense and level
|
||||
information for the interrupt. This should be encoded based on
|
||||
the information in section 2) depending on the type of interrupt
|
||||
controller you have.
|
||||
- interrupt-parent : the phandle for the interrupt controller that
|
||||
services interrupts for this device.
|
||||
- phy-handle : The phandle for the PHY connected to this ethernet
|
||||
controller.
|
||||
- fixed-link : <a b c d e> where a is emulated phy id - choose any,
|
||||
but unique to the all specified fixed-links, b is duplex - 0 half,
|
||||
1 full, c is link speed - d#10/d#100/d#1000, d is pause - 0 no
|
||||
pause, 1 pause, e is asym_pause - 0 no asym_pause, 1 asym_pause.
|
||||
|
||||
Recommended properties:
|
||||
|
||||
- phy-connection-type : a string naming the controller/PHY interface type,
|
||||
i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id", "sgmii",
|
||||
"tbi", or "rtbi". This property is only really needed if the connection
|
||||
is of type "rgmii-id", as all other connection types are detected by
|
||||
hardware.
|
||||
|
||||
|
||||
Example:
|
||||
ethernet@24000 {
|
||||
#size-cells = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <24000 1000>;
|
||||
mac-address = [ 00 E0 0C 00 73 00 ];
|
||||
interrupts = <d 3 e 3 12 3>;
|
||||
interrupt-parent = <40000>;
|
||||
phy-handle = <2452000>
|
||||
};
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
Freescale SOC USB controllers
|
||||
|
||||
The device node for a USB controller that is part of a Freescale
|
||||
SOC is as described in the document "Open Firmware Recommended
|
||||
Practice : Universal Serial Bus" with the following modifications
|
||||
and additions :
|
||||
|
||||
Required properties :
|
||||
- compatible : Should be "fsl-usb2-mph" for multi port host USB
|
||||
controllers, or "fsl-usb2-dr" for dual role USB controllers
|
||||
- phy_type : For multi port host USB controllers, should be one of
|
||||
"ulpi", or "serial". For dual role USB controllers, should be
|
||||
one of "ulpi", "utmi", "utmi_wide", or "serial".
|
||||
- reg : Offset and length of the register set for the device
|
||||
- port0 : boolean; if defined, indicates port0 is connected for
|
||||
fsl-usb2-mph compatible controllers. Either this property or
|
||||
"port1" (or both) must be defined for "fsl-usb2-mph" compatible
|
||||
controllers.
|
||||
- port1 : boolean; if defined, indicates port1 is connected for
|
||||
fsl-usb2-mph compatible controllers. Either this property or
|
||||
"port0" (or both) must be defined for "fsl-usb2-mph" compatible
|
||||
controllers.
|
||||
- dr_mode : indicates the working mode for "fsl-usb2-dr" compatible
|
||||
controllers. Can be "host", "peripheral", or "otg". Default to
|
||||
"host" if not defined for backward compatibility.
|
||||
|
||||
Recommended properties :
|
||||
- interrupts : <a b> where a is the interrupt number and b is a
|
||||
field that represents an encoding of the sense and level
|
||||
information for the interrupt. This should be encoded based on
|
||||
the information in section 2) depending on the type of interrupt
|
||||
controller you have.
|
||||
- interrupt-parent : the phandle for the interrupt controller that
|
||||
services interrupts for this device.
|
||||
|
||||
Example multi port host USB controller device node :
|
||||
usb@22000 {
|
||||
compatible = "fsl-usb2-mph";
|
||||
reg = <22000 1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <700>;
|
||||
interrupts = <27 1>;
|
||||
phy_type = "ulpi";
|
||||
port0;
|
||||
port1;
|
||||
};
|
||||
|
||||
Example dual role USB controller device node :
|
||||
usb@23000 {
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <23000 1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <700>;
|
||||
interrupts = <26 1>;
|
||||
dr_mode = "otg";
|
||||
phy = "ulpi";
|
||||
};
|
||||
|
|
@ -2521,13 +2521,11 @@ W: http://www.penguinppc.org/
|
|||
L: linuxppc-dev@ozlabs.org
|
||||
S: Maintained
|
||||
|
||||
LINUX FOR POWERPC EMBEDDED MPC52XX
|
||||
LINUX FOR POWERPC EMBEDDED MPC5XXX
|
||||
P: Sylvain Munaut
|
||||
M: tnt@246tNt.com
|
||||
P: Grant Likely
|
||||
M: grant.likely@secretlab.ca
|
||||
W: http://www.246tNt.com/mpc52xx/
|
||||
W: http://www.penguinppc.org/
|
||||
L: linuxppc-dev@ozlabs.org
|
||||
S: Maintained
|
||||
|
||||
|
|
|
|||
1
Makefile
1
Makefile
|
|
@ -1,3 +1,4 @@
|
|||
FRED=42
|
||||
VERSION = 2
|
||||
PATCHLEVEL = 6
|
||||
SUBLEVEL = 26
|
||||
|
|
|
|||
|
|
@ -53,6 +53,9 @@ config STACKTRACE_SUPPORT
|
|||
bool
|
||||
default y
|
||||
|
||||
config HAVE_LATENCYTOP_SUPPORT
|
||||
def_bool y
|
||||
|
||||
config TRACE_IRQFLAGS_SUPPORT
|
||||
bool
|
||||
depends on PPC64
|
||||
|
|
@ -111,6 +114,7 @@ config PPC
|
|||
select HAVE_KPROBES
|
||||
select HAVE_KRETPROBES
|
||||
select HAVE_LMB
|
||||
select HAVE_DMA_ATTRS if PPC64
|
||||
select USE_GENERIC_SMP_HELPERS if SMP
|
||||
select HAVE_OPROFILE
|
||||
|
||||
|
|
@ -311,8 +315,8 @@ config KEXEC
|
|||
strongly in flux, so no good recommendation can be made.
|
||||
|
||||
config CRASH_DUMP
|
||||
bool "Build a kdump crash kernel (EXPERIMENTAL)"
|
||||
depends on PPC_MULTIPLATFORM && PPC64 && EXPERIMENTAL
|
||||
bool "Build a kdump crash kernel"
|
||||
depends on PPC_MULTIPLATFORM && PPC64
|
||||
help
|
||||
Build a kernel suitable for use as a kdump capture kernel.
|
||||
The kernel will be linked at a different address than normal, and
|
||||
|
|
@ -461,6 +465,19 @@ config CMDLINE
|
|||
some command-line options at build time by entering them here. In
|
||||
most cases you will need to specify the root device here.
|
||||
|
||||
config EXTRA_TARGETS
|
||||
string "Additional default image types"
|
||||
help
|
||||
List additional targets to be built by the bootwrapper here (separated
|
||||
by spaces). This is useful for targets that depend of device tree
|
||||
files in the .dts directory.
|
||||
|
||||
Targets in this list will be build as part of the default build
|
||||
target, or when the user does a 'make zImage' or a
|
||||
'make zImage.initrd'.
|
||||
|
||||
If unsure, leave blank
|
||||
|
||||
if !44x || BROKEN
|
||||
config ARCH_WANTS_FREEZER_CONTROL
|
||||
def_bool y
|
||||
|
|
@ -541,6 +558,12 @@ config FSL_LBC
|
|||
help
|
||||
Freescale Localbus support
|
||||
|
||||
config FSL_GTM
|
||||
bool
|
||||
depends on PPC_83xx || QUICC_ENGINE || CPM2
|
||||
help
|
||||
Freescale General-purpose Timers support
|
||||
|
||||
# Yes MCA RS/6000s exist but Linux-PPC does not currently support any
|
||||
config MCA
|
||||
bool
|
||||
|
|
|
|||
|
|
@ -57,6 +57,16 @@ config KGDB
|
|||
debugger. See <http://kgdb.sourceforge.net/> for more information.
|
||||
Unless you are intending to debug the kernel, say N here.
|
||||
|
||||
config CODE_PATCHING_SELFTEST
|
||||
bool "Run self-tests of the code-patching code."
|
||||
depends on DEBUG_KERNEL
|
||||
default n
|
||||
|
||||
config FTR_FIXUP_SELFTEST
|
||||
bool "Run self-tests of the feature-fixup code."
|
||||
depends on DEBUG_KERNEL
|
||||
default n
|
||||
|
||||
choice
|
||||
prompt "Serial Port"
|
||||
depends on KGDB
|
||||
|
|
|
|||
|
|
@ -18,22 +18,16 @@ HAS_BIARCH := $(call cc-option-yn, -m32)
|
|||
CROSS32_COMPILE ?=
|
||||
|
||||
CROSS32CC := $(CROSS32_COMPILE)gcc
|
||||
CROSS32AS := $(CROSS32_COMPILE)as
|
||||
CROSS32LD := $(CROSS32_COMPILE)ld
|
||||
CROSS32AR := $(CROSS32_COMPILE)ar
|
||||
CROSS32OBJCOPY := $(CROSS32_COMPILE)objcopy
|
||||
|
||||
ifeq ($(HAS_BIARCH),y)
|
||||
ifeq ($(CROSS32_COMPILE),)
|
||||
CROSS32CC := $(CC) -m32
|
||||
CROSS32AS := $(AS) -a32
|
||||
CROSS32LD := $(LD) -m elf32ppc
|
||||
CROSS32OBJCOPY := $(OBJCOPY)
|
||||
CROSS32AR := GNUTARGET=elf32-powerpc $(AR)
|
||||
endif
|
||||
endif
|
||||
|
||||
export CROSS32CC CROSS32AS CROSS32LD CROSS32AR CROSS32OBJCOPY
|
||||
export CROSS32CC CROSS32AR
|
||||
|
||||
ifeq ($(CROSS_COMPILE),)
|
||||
KBUILD_DEFCONFIG := $(shell uname -m)_defconfig
|
||||
|
|
@ -169,12 +163,25 @@ bootwrapper_install %.dtb:
|
|||
$(Q)$(MAKE) ARCH=ppc64 $(build)=$(boot) $(patsubst %,$(boot)/%,$@)
|
||||
|
||||
define archhelp
|
||||
@echo '* zImage - Compressed kernel image (arch/$(ARCH)/boot/zImage.*)'
|
||||
@echo '* zImage - Build default images selected by kernel config'
|
||||
@echo ' zImage.* - Compressed kernel image (arch/$(ARCH)/boot/zImage.*)'
|
||||
@echo ' uImage - U-Boot native image format'
|
||||
@echo ' cuImage.<dt> - Backwards compatible U-Boot image for older'
|
||||
@echo ' versions which do not support device trees'
|
||||
@echo ' dtbImage.<dt> - zImage with an embedded device tree blob'
|
||||
@echo ' simpleImage.<dt> - Firmware independent image.'
|
||||
@echo ' treeImage.<dt> - Support for older IBM 4xx firmware (not U-Boot)'
|
||||
@echo ' install - Install kernel using'
|
||||
@echo ' (your) ~/bin/installkernel or'
|
||||
@echo ' (distribution) /sbin/installkernel or'
|
||||
@echo ' install to $$(INSTALL_PATH) and run lilo'
|
||||
@echo ' *_defconfig - Select default config from arch/$(ARCH)/configs'
|
||||
@echo ''
|
||||
@echo ' Targets with <dt> embed a device tree blob inside the image'
|
||||
@echo ' These targets support board with firmware that does not'
|
||||
@echo ' support passing a device tree directly. Replace <dt> with the'
|
||||
@echo ' name of a dts file from the arch/$(ARCH)/boot/dts/ directory'
|
||||
@echo ' (minus the .dts extension).'
|
||||
endef
|
||||
|
||||
install:
|
||||
|
|
|
|||
|
|
@ -35,6 +35,8 @@ endif
|
|||
|
||||
BOOTCFLAGS += -I$(obj) -I$(srctree)/$(obj) -I$(srctree)/$(src)/libfdt
|
||||
|
||||
DTS_FLAGS ?= -p 1024
|
||||
|
||||
$(obj)/4xx.o: BOOTCFLAGS += -mcpu=405
|
||||
$(obj)/ebony.o: BOOTCFLAGS += -mcpu=405
|
||||
$(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=405
|
||||
|
|
@ -63,10 +65,10 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c
|
|||
ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c \
|
||||
cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c \
|
||||
cuboot-bamboo.c cuboot-mpc7448hpc2.c cuboot-taishan.c \
|
||||
fixed-head.S ep88xc.c ep405.c \
|
||||
fixed-head.S ep88xc.c ep405.c cuboot-c2k.c \
|
||||
cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
|
||||
cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
|
||||
virtex405-head.S
|
||||
virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c
|
||||
src-boot := $(src-wlib) $(src-plat) empty.c
|
||||
|
||||
src-boot := $(addprefix $(obj)/, $(src-boot))
|
||||
|
|
@ -213,6 +215,7 @@ image-$(CONFIG_WALNUT) += treeImage.walnut
|
|||
# Board ports in arch/powerpc/platform/44x/Kconfig
|
||||
image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony
|
||||
image-$(CONFIG_BAMBOO) += treeImage.bamboo cuImage.bamboo
|
||||
image-$(CONFIG_SAM440EP) += cuImage.sam440ep
|
||||
image-$(CONFIG_SEQUOIA) += cuImage.sequoia
|
||||
image-$(CONFIG_RAINIER) += cuImage.rainier
|
||||
image-$(CONFIG_TAISHAN) += cuImage.taishan
|
||||
|
|
@ -242,6 +245,7 @@ image-$(CONFIG_MPC834x_ITX) += cuImage.mpc8349emitx \
|
|||
cuImage.mpc8349emitxgp
|
||||
image-$(CONFIG_MPC834x_MDS) += cuImage.mpc834x_mds
|
||||
image-$(CONFIG_MPC836x_MDS) += cuImage.mpc836x_mds
|
||||
image-$(CONFIG_ASP834x) += dtbImage.asp834x-redboot
|
||||
|
||||
# Board ports in arch/powerpc/platform/85xx/Kconfig
|
||||
image-$(CONFIG_MPC8540_ADS) += cuImage.mpc8540ads
|
||||
|
|
@ -254,6 +258,7 @@ image-$(CONFIG_MPC85xx_DS) += cuImage.mpc8544ds \
|
|||
cuImage.mpc8572ds
|
||||
image-$(CONFIG_TQM8540) += cuImage.tqm8540
|
||||
image-$(CONFIG_TQM8541) += cuImage.tqm8541
|
||||
image-$(CONFIG_TQM8548) += cuImage.tqm8548
|
||||
image-$(CONFIG_TQM8555) += cuImage.tqm8555
|
||||
image-$(CONFIG_TQM8560) += cuImage.tqm8560
|
||||
image-$(CONFIG_SBC8548) += cuImage.sbc8548
|
||||
|
|
@ -263,6 +268,7 @@ image-$(CONFIG_KSI8560) += cuImage.ksi8560
|
|||
# Board ports in arch/powerpc/platform/embedded6xx/Kconfig
|
||||
image-$(CONFIG_STORCENTER) += cuImage.storcenter
|
||||
image-$(CONFIG_MPC7448HPC2) += cuImage.mpc7448hpc2
|
||||
image-$(CONFIG_PPC_C2K) += cuImage.c2k
|
||||
|
||||
# For 32-bit powermacs, build the COFF and miboot images
|
||||
# as well as the ELF images.
|
||||
|
|
@ -270,6 +276,9 @@ ifeq ($(CONFIG_PPC32),y)
|
|||
image-$(CONFIG_PPC_PMAC) += zImage.coff zImage.miboot
|
||||
endif
|
||||
|
||||
# Allow extra targets to be added to the defconfig
|
||||
image-y += $(subst ",,$(CONFIG_EXTRA_TARGETS))
|
||||
|
||||
initrd- := $(patsubst zImage%, zImage.initrd%, $(image-n) $(image-))
|
||||
initrd-y := $(patsubst zImage%, zImage.initrd%, \
|
||||
$(patsubst dtbImage%, dtbImage.initrd%, \
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ char arch[] = "PowerPC";
|
|||
#define N_DESCR 6
|
||||
unsigned int descr[N_DESCR] = {
|
||||
0xffffffff, /* real-mode = true */
|
||||
0x00c00000, /* real-base, i.e. where we expect OF to be */
|
||||
0x02000000, /* real-base, i.e. where we expect OF to be */
|
||||
0xffffffff, /* real-size */
|
||||
0xffffffff, /* virt-base */
|
||||
0xffffffff, /* virt-size */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,190 @@
|
|||
/*
|
||||
* GEFanuc C2K platform code.
|
||||
*
|
||||
* Author: Remi Machet <rmachet@slac.stanford.edu>
|
||||
*
|
||||
* Originated from prpmc2800.c
|
||||
*
|
||||
* 2008 (c) Stanford University
|
||||
* 2007 (c) MontaVista, Software, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "types.h"
|
||||
#include "stdio.h"
|
||||
#include "io.h"
|
||||
#include "ops.h"
|
||||
#include "elf.h"
|
||||
#include "gunzip_util.h"
|
||||
#include "mv64x60.h"
|
||||
#include "cuboot.h"
|
||||
#include "ppcboot.h"
|
||||
|
||||
static u8 *bridge_base;
|
||||
|
||||
static void c2k_bridge_setup(u32 mem_size)
|
||||
{
|
||||
u32 i, v[30], enables, acc_bits;
|
||||
u32 pci_base_hi, pci_base_lo, size, buf[2];
|
||||
unsigned long cpu_base;
|
||||
int rc;
|
||||
void *devp, *mv64x60_devp;
|
||||
u8 *bridge_pbase, is_coherent;
|
||||
struct mv64x60_cpu2pci_win *tbl;
|
||||
int bus;
|
||||
|
||||
bridge_pbase = mv64x60_get_bridge_pbase();
|
||||
is_coherent = mv64x60_is_coherent();
|
||||
|
||||
if (is_coherent)
|
||||
acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_WB
|
||||
| MV64x60_PCI_ACC_CNTL_SWAP_NONE
|
||||
| MV64x60_PCI_ACC_CNTL_MBURST_32_BYTES
|
||||
| MV64x60_PCI_ACC_CNTL_RDSIZE_32_BYTES;
|
||||
else
|
||||
acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_NONE
|
||||
| MV64x60_PCI_ACC_CNTL_SWAP_NONE
|
||||
| MV64x60_PCI_ACC_CNTL_MBURST_128_BYTES
|
||||
| MV64x60_PCI_ACC_CNTL_RDSIZE_256_BYTES;
|
||||
|
||||
mv64x60_config_ctlr_windows(bridge_base, bridge_pbase, is_coherent);
|
||||
mv64x60_devp = find_node_by_compatible(NULL, "marvell,mv64360");
|
||||
if (mv64x60_devp == NULL)
|
||||
fatal("Error: Missing marvell,mv64360 device tree node\n\r");
|
||||
|
||||
enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE));
|
||||
enables |= 0x007ffe00; /* Disable all cpu->pci windows */
|
||||
out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables);
|
||||
|
||||
/* Get the cpu -> pci i/o & mem mappings from the device tree */
|
||||
devp = NULL;
|
||||
for (bus = 0; ; bus++) {
|
||||
char name[] = "pci ";
|
||||
|
||||
name[strlen(name)-1] = bus+'0';
|
||||
|
||||
devp = find_node_by_alias(name);
|
||||
if (devp == NULL)
|
||||
break;
|
||||
|
||||
if (bus >= 2)
|
||||
fatal("Error: Only 2 PCI controllers are supported at" \
|
||||
" this time.\n");
|
||||
|
||||
mv64x60_config_pci_windows(bridge_base, bridge_pbase, bus, 0,
|
||||
mem_size, acc_bits);
|
||||
|
||||
rc = getprop(devp, "ranges", v, sizeof(v));
|
||||
if (rc == 0)
|
||||
fatal("Error: Can't find marvell,mv64360-pci ranges"
|
||||
" property\n\r");
|
||||
|
||||
/* Get the cpu -> pci i/o & mem mappings from the device tree */
|
||||
|
||||
for (i = 0; i < rc; i += 6) {
|
||||
switch (v[i] & 0xff000000) {
|
||||
case 0x01000000: /* PCI I/O Space */
|
||||
tbl = mv64x60_cpu2pci_io;
|
||||
break;
|
||||
case 0x02000000: /* PCI MEM Space */
|
||||
tbl = mv64x60_cpu2pci_mem;
|
||||
break;
|
||||
default:
|
||||
continue;
|
||||
}
|
||||
|
||||
pci_base_hi = v[i+1];
|
||||
pci_base_lo = v[i+2];
|
||||
cpu_base = v[i+3];
|
||||
size = v[i+5];
|
||||
|
||||
buf[0] = cpu_base;
|
||||
buf[1] = size;
|
||||
|
||||
if (!dt_xlate_addr(devp, buf, sizeof(buf), &cpu_base))
|
||||
fatal("Error: Can't translate PCI address " \
|
||||
"0x%x\n\r", (u32)cpu_base);
|
||||
|
||||
mv64x60_config_cpu2pci_window(bridge_base, bus,
|
||||
pci_base_hi, pci_base_lo, cpu_base, size, tbl);
|
||||
}
|
||||
|
||||
enables &= ~(3<<(9+bus*5)); /* Enable cpu->pci<bus> i/o,
|
||||
cpu->pci<bus> mem0 */
|
||||
out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE),
|
||||
enables);
|
||||
};
|
||||
}
|
||||
|
||||
static void c2k_fixups(void)
|
||||
{
|
||||
u32 mem_size;
|
||||
|
||||
mem_size = mv64x60_get_mem_size(bridge_base);
|
||||
c2k_bridge_setup(mem_size); /* Do necessary bridge setup */
|
||||
}
|
||||
|
||||
#define MV64x60_MPP_CNTL_0 0xf000
|
||||
#define MV64x60_MPP_CNTL_2 0xf008
|
||||
#define MV64x60_GPP_IO_CNTL 0xf100
|
||||
#define MV64x60_GPP_LEVEL_CNTL 0xf110
|
||||
#define MV64x60_GPP_VALUE_SET 0xf118
|
||||
|
||||
static void c2k_reset(void)
|
||||
{
|
||||
u32 temp;
|
||||
|
||||
udelay(5000000);
|
||||
|
||||
if (bridge_base != 0) {
|
||||
temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0));
|
||||
temp &= 0xFFFF0FFF;
|
||||
out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0), temp);
|
||||
|
||||
temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL));
|
||||
temp |= 0x00000004;
|
||||
out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp);
|
||||
|
||||
temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL));
|
||||
temp |= 0x00000004;
|
||||
out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp);
|
||||
|
||||
temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2));
|
||||
temp &= 0xFFFF0FFF;
|
||||
out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2), temp);
|
||||
|
||||
temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL));
|
||||
temp |= 0x00080000;
|
||||
out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp);
|
||||
|
||||
temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL));
|
||||
temp |= 0x00080000;
|
||||
out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp);
|
||||
|
||||
out_le32((u32 *)(bridge_base + MV64x60_GPP_VALUE_SET),
|
||||
0x00080004);
|
||||
}
|
||||
|
||||
for (;;);
|
||||
}
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
|
||||
fdt_init(_dtb_start);
|
||||
|
||||
bridge_base = mv64x60_get_bridge_base();
|
||||
|
||||
platform_ops.fixups = c2k_fixups;
|
||||
platform_ops.exit = c2k_reset;
|
||||
|
||||
if (serial_console_init() < 0)
|
||||
exit();
|
||||
}
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
* Old U-boot compatibility for Sam440ep based off bamboo.c code
|
||||
* original copyrights below
|
||||
*
|
||||
* Author: Josh Boyer <jwboyer@linux.vnet.ibm.com>
|
||||
*
|
||||
* Copyright 2007 IBM Corporation
|
||||
*
|
||||
* Based on cuboot-ebony.c
|
||||
*
|
||||
* Modified from cuboot-bamboo.c for sam440ep:
|
||||
* Copyright 2008 Giuseppe Coviello <gicoviello@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "stdio.h"
|
||||
#include "44x.h"
|
||||
#include "4xx.h"
|
||||
#include "cuboot.h"
|
||||
|
||||
#define TARGET_4xx
|
||||
#define TARGET_44x
|
||||
#include "ppcboot.h"
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
static void sam440ep_fixups(void)
|
||||
{
|
||||
unsigned long sysclk = 66666666;
|
||||
|
||||
ibm440ep_fixup_clocks(sysclk, 11059200, 25000000);
|
||||
ibm4xx_sdram_fixup_memsize();
|
||||
ibm4xx_quiesce_eth((u32 *)0xef600e00, (u32 *)0xef600f00);
|
||||
dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
platform_ops.fixups = sam440ep_fixups;
|
||||
platform_ops.exit = ibm44x_dbcr_reset;
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
}
|
||||
|
|
@ -10,6 +10,7 @@
|
|||
#include "ops.h"
|
||||
#include "4xx.h"
|
||||
#include "cuboot.h"
|
||||
#include "stdio.h"
|
||||
|
||||
#define TARGET_4xx
|
||||
#define TARGET_44x
|
||||
|
|
@ -17,14 +18,54 @@
|
|||
|
||||
static bd_t bd;
|
||||
|
||||
static void warp_fixup_one_nor(u32 from, u32 to)
|
||||
{
|
||||
void *devp;
|
||||
char name[50];
|
||||
u32 v[2];
|
||||
|
||||
sprintf(name, "/plb/opb/ebc/nor_flash@0,0/partition@%x", from);
|
||||
|
||||
devp = finddevice(name);
|
||||
if (!devp)
|
||||
return;
|
||||
|
||||
if (getprop(devp, "reg", v, sizeof(v)) == sizeof(v)) {
|
||||
v[0] = to;
|
||||
setprop(devp, "reg", v, sizeof(v));
|
||||
|
||||
printf("NOR 64M fixup %x -> %x\r\n", from, to);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void warp_fixups(void)
|
||||
{
|
||||
unsigned long sysclk = 66000000;
|
||||
|
||||
ibm440ep_fixup_clocks(sysclk, 11059200, 50000000);
|
||||
ibm440ep_fixup_clocks(66000000, 11059200, 50000000);
|
||||
ibm4xx_sdram_fixup_memsize();
|
||||
ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
|
||||
dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
|
||||
|
||||
/* Fixup for 64M flash on Rev A boards. */
|
||||
if (bd.bi_flashsize == 0x4000000) {
|
||||
void *devp;
|
||||
u32 v[3];
|
||||
|
||||
devp = finddevice("/plb/opb/ebc/nor_flash@0,0");
|
||||
if (!devp)
|
||||
return;
|
||||
|
||||
/* Fixup the size */
|
||||
if (getprop(devp, "reg", v, sizeof(v)) == sizeof(v)) {
|
||||
v[2] = bd.bi_flashsize;
|
||||
setprop(devp, "reg", v, sizeof(v));
|
||||
}
|
||||
|
||||
/* Fixup parition offsets */
|
||||
warp_fixup_one_nor(0x300000, 0x3f00000);
|
||||
warp_fixup_one_nor(0x340000, 0x3f40000);
|
||||
warp_fixup_one_nor(0x380000, 0x3f80000);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,282 @@
|
|||
/*
|
||||
* Analogue & Micro ASP8347 Device Tree Source
|
||||
*
|
||||
* Copyright 2008 Codehermit
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "Analogue & Micro ASP8347E";
|
||||
compatible = "analogue-and-micro,asp8347e";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8347@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
timebase-frequency = <0>; // from bootloader
|
||||
bus-frequency = <0>; // from bootloader
|
||||
clock-frequency = <0>; // from bootloader
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x8000000>; // 128MB at 0
|
||||
};
|
||||
|
||||
localbus@ff005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8347e-localbus",
|
||||
"fsl,pq2pro-localbus",
|
||||
"simple-bus";
|
||||
reg = <0xff005000 0x1000>;
|
||||
interrupts = <77 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
|
||||
ranges = <
|
||||
0 0 0xf0000000 0x02000000
|
||||
>;
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 0x02000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
soc8349@ff000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0x0 0xff000000 0x00100000>;
|
||||
reg = <0xff000000 0x00000200>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
wdt@200 {
|
||||
device_type = "watchdog";
|
||||
compatible = "mpc83xx_wdt";
|
||||
reg = <0x200 0x100>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <14 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1374";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <15 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <16 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
dma@82a8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8347-dma", "fsl,elo-dma";
|
||||
reg = <0x82a8 4>;
|
||||
ranges = <0 0x8100 0x1a8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x180 0x28>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
};
|
||||
|
||||
/* phy type (ULPI or SERIAL) are only types supported for MPH */
|
||||
/* port = 0 or 1 */
|
||||
usb@22000 {
|
||||
compatible = "fsl-usb2-mph";
|
||||
reg = <0x22000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <39 0x8>;
|
||||
phy_type = "ulpi";
|
||||
port1;
|
||||
};
|
||||
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
|
||||
usb@23000 {
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x23000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <38 0x8>;
|
||||
dr_mode = "otg";
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x24520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <17 0x8>;
|
||||
reg = <0x1>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <18 0x8>;
|
||||
reg = <0x2>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
local-mac-address = [ 00 08 e5 11 32 33 ];
|
||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
phy-handle = <&phy0>;
|
||||
linux,network-index = <0>;
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
local-mac-address = [ 00 08 e5 11 32 34 ];
|
||||
interrupts = <35 0x8 36 0x8 37 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
phy-handle = <&phy1>;
|
||||
linux,network-index = <1>;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <400000000>;
|
||||
interrupts = <9 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <400000000>;
|
||||
interrupts = <10 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
/* May need to remove if on a part without crypto engine */
|
||||
crypto@30000 {
|
||||
device_type = "crypto";
|
||||
model = "SEC2";
|
||||
compatible = "talitos";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x0000007e>;
|
||||
/* desc mask is for rev2.0,
|
||||
* we need runtime fixup for >2.0 */
|
||||
descriptor-types-mask = <0x01010ebf>;
|
||||
};
|
||||
|
||||
/* IPIC
|
||||
* interrupts cell = <intr #, sense>
|
||||
* sense values match linux IORESOURCE_IRQ_* defines:
|
||||
* sense == 8: Level, low assertion
|
||||
* sense == 2: Edge, high-to-low change
|
||||
*/
|
||||
ipic: pic@700 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x700 0x100>;
|
||||
device_type = "ipic";
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,38400 root=/dev/mtdblock3 rootfstype=jffs2";
|
||||
linux,stdout-path = &serial0;
|
||||
};
|
||||
|
||||
};
|
||||
|
|
@ -11,12 +11,14 @@
|
|||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,bamboo";
|
||||
compatible = "amcc,bamboo";
|
||||
dcr-parent = <&/cpus/cpu@0>;
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
|
|
@ -34,13 +36,13 @@
|
|||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,440EP";
|
||||
reg = <0>;
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
timebase-frequency = <0>; /* Filled in by zImage */
|
||||
i-cache-line-size = <20>;
|
||||
d-cache-line-size = <20>;
|
||||
i-cache-size = <8000>;
|
||||
d-cache-size = <8000>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
|
|
@ -48,14 +50,14 @@
|
|||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0 0>; /* Filled in by zImage */
|
||||
reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller0 {
|
||||
compatible = "ibm,uic-440ep","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0c0 009>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
|
|
@ -65,22 +67,22 @@
|
|||
compatible = "ibm,uic-440ep","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0d0 009>;
|
||||
dcr-reg = <0x0d0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <1e 4 1f 4>; /* cascade */
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
SDR0: sdr {
|
||||
compatible = "ibm,sdr-440ep";
|
||||
dcr-reg = <00e 002>;
|
||||
dcr-reg = <0x00e 0x002>;
|
||||
};
|
||||
|
||||
CPR0: cpr {
|
||||
compatible = "ibm,cpr-440ep";
|
||||
dcr-reg = <00c 002>;
|
||||
dcr-reg = <0x00c 0x002>;
|
||||
};
|
||||
|
||||
plb {
|
||||
|
|
@ -92,29 +94,29 @@
|
|||
|
||||
SDRAM0: sdram {
|
||||
compatible = "ibm,sdram-440ep", "ibm,sdram-405gp";
|
||||
dcr-reg = <010 2>;
|
||||
dcr-reg = <0x010 0x002>;
|
||||
};
|
||||
|
||||
DMA0: dma {
|
||||
compatible = "ibm,dma-440ep", "ibm,dma-440gp";
|
||||
dcr-reg = <100 027>;
|
||||
dcr-reg = <0x100 0x027>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal";
|
||||
dcr-reg = <180 62>;
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <4>;
|
||||
num-rx-chans = <2>;
|
||||
interrupt-parent = <&MAL0>;
|
||||
interrupts = <0 1 2 3 4>;
|
||||
interrupts = <0x0 0x1 0x2 0x3 0x4>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
|
||||
/*RXEOB*/ 1 &UIC0 b 4
|
||||
/*SERR*/ 2 &UIC1 0 4
|
||||
/*TXDE*/ 3 &UIC1 1 4
|
||||
/*RXDE*/ 4 &UIC1 2 4>;
|
||||
interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
|
||||
/*RXEOB*/ 0x1 &UIC0 0xb 0x4
|
||||
/*SERR*/ 0x2 &UIC1 0x0 0x4
|
||||
/*TXDE*/ 0x3 &UIC1 0x1 0x4
|
||||
/*RXDE*/ 0x4 &UIC1 0x2 0x4>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
|
|
@ -124,101 +126,101 @@
|
|||
/* Bamboo is oddball in the 44x world and doesn't use the ERPN
|
||||
* bits.
|
||||
*/
|
||||
ranges = <00000000 0 00000000 80000000
|
||||
80000000 0 80000000 80000000>;
|
||||
ranges = <0x00000000 0x00000000 0x00000000 0x80000000
|
||||
0x80000000 0x00000000 0x80000000 0x80000000>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <7 4>;
|
||||
interrupts = <0x7 0x4>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc";
|
||||
dcr-reg = <012 2>;
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
interrupts = <5 1>;
|
||||
interrupts = <0x5 0x1>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
};
|
||||
|
||||
UART0: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600300 8>;
|
||||
virtual-reg = <ef600300>;
|
||||
reg = <0xef600300 0x00000008>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
current-speed = <1c200>;
|
||||
current-speed = <115200>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0 4>;
|
||||
interrupts = <0x0 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600400 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600400 8>;
|
||||
virtual-reg = <ef600400>;
|
||||
reg = <0xef600400 0x00000008>;
|
||||
virtual-reg = <0xef600400>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <1 4>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
UART2: serial@ef600500 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600500 8>;
|
||||
virtual-reg = <ef600500>;
|
||||
reg = <0xef600500 0x00000008>;
|
||||
virtual-reg = <0xef600500>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <3 4>;
|
||||
interrupts = <0x3 0x4>;
|
||||
};
|
||||
|
||||
UART3: serial@ef600600 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600600 8>;
|
||||
virtual-reg = <ef600600>;
|
||||
reg = <0xef600600 0x00000008>;
|
||||
virtual-reg = <0xef600600>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <4 4>;
|
||||
interrupts = <0x4 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@ef600700 {
|
||||
compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
|
||||
reg = <ef600700 14>;
|
||||
reg = <0xef600700 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <2 4>;
|
||||
interrupts = <0x2 0x4>;
|
||||
};
|
||||
|
||||
IIC1: i2c@ef600800 {
|
||||
compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
|
||||
reg = <ef600800 14>;
|
||||
reg = <0xef600800 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <7 4>;
|
||||
interrupts = <0x7 0x4>;
|
||||
};
|
||||
|
||||
ZMII0: emac-zmii@ef600d00 {
|
||||
compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii";
|
||||
reg = <ef600d00 c>;
|
||||
reg = <0xef600d00 0x0000000c>;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600e00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <1c 4 1d 4>;
|
||||
reg = <ef600e00 70>;
|
||||
interrupts = <0x1c 0x4 0x1d 0x4>;
|
||||
reg = <0xef600e00 0x00000070>;
|
||||
local-mac-address = [000000000000];
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0 1>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <5dc>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
max-frame-size = <1500>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rmii";
|
||||
phy-map = <00000000>;
|
||||
phy-map = <0x00000000>;
|
||||
zmii-device = <&ZMII0>;
|
||||
zmii-channel = <0>;
|
||||
};
|
||||
|
|
@ -227,26 +229,26 @@
|
|||
device_type = "network";
|
||||
compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <1e 4 1f 4>;
|
||||
reg = <ef600f00 70>;
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>;
|
||||
reg = <0xef600f00 0x00000070>;
|
||||
local-mac-address = [000000000000];
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <2 3>;
|
||||
mal-rx-channel = <1>;
|
||||
cell-index = <1>;
|
||||
max-frame-size = <5dc>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
max-frame-size = <1500>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rmii";
|
||||
phy-map = <00000000>;
|
||||
phy-map = <0x00000000>;
|
||||
zmii-device = <&ZMII0>;
|
||||
zmii-channel = <1>;
|
||||
};
|
||||
|
||||
usb@ef601000 {
|
||||
compatible = "ohci-be";
|
||||
reg = <ef601000 80>;
|
||||
interrupts = <8 1 9 1>;
|
||||
reg = <0xef601000 0x00000080>;
|
||||
interrupts = <0x8 0x1 0x9 0x1>;
|
||||
interrupt-parent = < &UIC1 >;
|
||||
};
|
||||
};
|
||||
|
|
@ -258,35 +260,35 @@
|
|||
#address-cells = <3>;
|
||||
compatible = "ibm,plb440ep-pci", "ibm,plb-pci";
|
||||
primary;
|
||||
reg = <0 eec00000 8 /* Config space access */
|
||||
0 eed00000 4 /* IACK */
|
||||
0 eed00000 4 /* Special cycle */
|
||||
0 ef400000 40>; /* Internal registers */
|
||||
reg = <0x00000000 0xeec00000 0x00000008 /* Config space access */
|
||||
0x00000000 0xeed00000 0x00000004 /* IACK */
|
||||
0x00000000 0xeed00000 0x00000004 /* Special cycle */
|
||||
0x00000000 0xef400000 0x00000040>; /* Internal registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed. Chip supports a second
|
||||
* IO range but we don't use it for now
|
||||
*/
|
||||
ranges = <02000000 0 a0000000 0 a0000000 0 20000000
|
||||
01000000 0 00000000 0 e8000000 0 00010000>;
|
||||
ranges = <0x02000000 0x00000000 0xa0000000 0x00000000 0xa0000000 0x00000000 0x20000000
|
||||
0x01000000 0x00000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 0 80000000>;
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* Bamboo has all 4 IRQ pins tied together per slot */
|
||||
interrupt-map-mask = <f800 0 0 0>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 1 */
|
||||
0800 0 0 0 &UIC0 1c 8
|
||||
0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8
|
||||
|
||||
/* IDSEL 2 */
|
||||
1000 0 0 0 &UIC0 1b 8
|
||||
0x1000 0x0 0x0 0x0 &UIC0 0x1b 0x8
|
||||
|
||||
/* IDSEL 3 */
|
||||
1800 0 0 0 &UIC0 1a 8
|
||||
0x1800 0x0 0x0 0x0 &UIC0 0x1a 0x8
|
||||
|
||||
/* IDSEL 4 */
|
||||
2000 0 0 0 &UIC0 19 8
|
||||
0x2000 0x0 0x0 0x0 &UIC0 0x19 0x8
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,371 @@
|
|||
/* Device Tree Source for GEFanuc C2K
|
||||
*
|
||||
* Author: Remi Machet <rmachet@slac.stanford.edu>
|
||||
*
|
||||
* Originated from prpmc2800.dts
|
||||
*
|
||||
* 2008 (c) Stanford University
|
||||
* 2007 (c) MontaVista, Software, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "C2K";
|
||||
compatible = "GEFanuc,C2K";
|
||||
coherency-off;
|
||||
|
||||
aliases {
|
||||
pci0 = &PCI0;
|
||||
pci1 = &PCI1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "PowerPC,7447";
|
||||
reg = <0>;
|
||||
clock-frequency = <996000000>; /* 996 MHz */
|
||||
bus-frequency = <166666667>; /* 166.6666 MHz */
|
||||
timebase-frequency = <41666667>; /* 166.6666/4 MHz */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x40000000>; /* 1GB */
|
||||
};
|
||||
|
||||
system-controller@d8000000 { /* Marvell Discovery */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "mv64460";
|
||||
compatible = "marvell,mv64360";
|
||||
clock-frequency = <166666667>; /* 166.66... MHz */
|
||||
reg = <0xd8000000 0x00010000>;
|
||||
virtual-reg = <0xd8000000>;
|
||||
ranges = <0xd4000000 0xd4000000 0x01000000 /* PCI 0 I/O Space */
|
||||
0x80000000 0x80000000 0x08000000 /* PCI 0 MEM Space */
|
||||
0xd0000000 0xd0000000 0x01000000 /* PCI 1 I/O Space */
|
||||
0xa0000000 0xa0000000 0x08000000 /* PCI 1 MEM Space */
|
||||
0xd8100000 0xd8100000 0x00010000 /* FPGA */
|
||||
0xd8110000 0xd8110000 0x00010000 /* FPGA USARTs */
|
||||
0xf8000000 0xf8000000 0x08000000 /* User FLASH */
|
||||
0x00000000 0xd8000000 0x00010000 /* Bridge's regs */
|
||||
0xd8140000 0xd8140000 0x00040000>; /* Integrated SRAM */
|
||||
|
||||
mdio@2000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "marvell,mv64360-mdio";
|
||||
reg = <0x2000 4>;
|
||||
PHY0: ethernet-phy@0 {
|
||||
device_type = "ethernet-phy";
|
||||
interrupts = <76>; /* GPP 12 */
|
||||
interrupt-parent = <&PIC>;
|
||||
reg = <0>;
|
||||
};
|
||||
PHY1: ethernet-phy@1 {
|
||||
device_type = "ethernet-phy";
|
||||
interrupts = <76>; /* GPP 12 */
|
||||
interrupt-parent = <&PIC>;
|
||||
reg = <1>;
|
||||
};
|
||||
PHY2: ethernet-phy@2 {
|
||||
device_type = "ethernet-phy";
|
||||
interrupts = <76>; /* GPP 12 */
|
||||
interrupt-parent = <&PIC>;
|
||||
reg = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet-group@2000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "marvell,mv64360-eth-group";
|
||||
reg = <0x2000 0x2000>;
|
||||
ethernet@0 {
|
||||
device_type = "network";
|
||||
compatible = "marvell,mv64360-eth";
|
||||
reg = <0>;
|
||||
interrupts = <32>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy = <&PHY0>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
};
|
||||
ethernet@1 {
|
||||
device_type = "network";
|
||||
compatible = "marvell,mv64360-eth";
|
||||
reg = <1>;
|
||||
interrupts = <33>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy = <&PHY1>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
};
|
||||
ethernet@2 {
|
||||
device_type = "network";
|
||||
compatible = "marvell,mv64360-eth";
|
||||
reg = <2>;
|
||||
interrupts = <34>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy = <&PHY2>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
};
|
||||
};
|
||||
|
||||
SDMA0: sdma@4000 {
|
||||
compatible = "marvell,mv64360-sdma";
|
||||
reg = <0x4000 0xc18>;
|
||||
virtual-reg = <0xd8004000>;
|
||||
interrupt-base = <0>;
|
||||
interrupts = <36>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
SDMA1: sdma@6000 {
|
||||
compatible = "marvell,mv64360-sdma";
|
||||
reg = <0x6000 0xc18>;
|
||||
virtual-reg = <0xd8006000>;
|
||||
interrupt-base = <0>;
|
||||
interrupts = <38>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
BRG0: brg@b200 {
|
||||
compatible = "marvell,mv64360-brg";
|
||||
reg = <0xb200 0x8>;
|
||||
clock-src = <8>;
|
||||
clock-frequency = <133333333>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
|
||||
BRG1: brg@b208 {
|
||||
compatible = "marvell,mv64360-brg";
|
||||
reg = <0xb208 0x8>;
|
||||
clock-src = <8>;
|
||||
clock-frequency = <133333333>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
|
||||
CUNIT: cunit@f200 {
|
||||
reg = <0xf200 0x200>;
|
||||
};
|
||||
|
||||
MPSCROUTING: mpscrouting@b400 {
|
||||
reg = <0xb400 0xc>;
|
||||
};
|
||||
|
||||
MPSCINTR: mpscintr@b800 {
|
||||
reg = <0xb800 0x100>;
|
||||
virtual-reg = <0xd800b800>;
|
||||
};
|
||||
|
||||
MPSC0: mpsc@8000 {
|
||||
device_type = "serial";
|
||||
compatible = "marvell,mv64360-mpsc";
|
||||
reg = <0x8000 0x38>;
|
||||
virtual-reg = <0xd8008000>;
|
||||
sdma = <&SDMA0>;
|
||||
brg = <&BRG0>;
|
||||
cunit = <&CUNIT>;
|
||||
mpscrouting = <&MPSCROUTING>;
|
||||
mpscintr = <&MPSCINTR>;
|
||||
cell-index = <0>;
|
||||
interrupts = <40>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
MPSC1: mpsc@9000 {
|
||||
device_type = "serial";
|
||||
compatible = "marvell,mv64360-mpsc";
|
||||
reg = <0x9000 0x38>;
|
||||
virtual-reg = <0xd8009000>;
|
||||
sdma = <&SDMA1>;
|
||||
brg = <&BRG1>;
|
||||
cunit = <&CUNIT>;
|
||||
mpscrouting = <&MPSCROUTING>;
|
||||
mpscintr = <&MPSCINTR>;
|
||||
cell-index = <1>;
|
||||
interrupts = <42>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
wdt@b410 { /* watchdog timer */
|
||||
compatible = "marvell,mv64360-wdt";
|
||||
reg = <0xb410 0x8>;
|
||||
};
|
||||
|
||||
i2c@c000 {
|
||||
compatible = "marvell,mv64360-i2c";
|
||||
reg = <0xc000 0x20>;
|
||||
virtual-reg = <0xd800c000>;
|
||||
interrupts = <37>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
PIC: pic {
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
compatible = "marvell,mv64360-pic";
|
||||
reg = <0x0000 0x88>;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
mpp@f000 {
|
||||
compatible = "marvell,mv64360-mpp";
|
||||
reg = <0xf000 0x10>;
|
||||
};
|
||||
|
||||
gpp@f100 {
|
||||
compatible = "marvell,mv64360-gpp";
|
||||
reg = <0xf100 0x20>;
|
||||
};
|
||||
|
||||
PCI0: pci@80000000 {
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
device_type = "pci";
|
||||
compatible = "marvell,mv64360-pci";
|
||||
reg = <0x0cf8 0x8>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xd4000000 0x0 0x01000000
|
||||
0x02000000 0x0 0x80000000 0x80000000 0x0 0x08000000>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <66000000>;
|
||||
interrupt-pci-iack = <0x0c34>;
|
||||
interrupt-parent = <&PIC>;
|
||||
interrupt-map-mask = <0x0000 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* Only one interrupt line for PMC0 slot (INTA) */
|
||||
0x0000 0 0 1 &PIC 88
|
||||
>;
|
||||
};
|
||||
|
||||
|
||||
PCI1: pci@a0000000 {
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
device_type = "pci";
|
||||
compatible = "marvell,mv64360-pci";
|
||||
reg = <0x0c78 0x8>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xd0000000 0x0 0x01000000
|
||||
0x02000000 0x0 0x80000000 0xa0000000 0x0 0x08000000>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <66000000>;
|
||||
interrupt-pci-iack = <0x0cb4>;
|
||||
interrupt-parent = <&PIC>;
|
||||
interrupt-map-mask = <0xf800 0x00 0x00 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x01: PMC1 ? */
|
||||
0x0800 0 0 1 &PIC 88
|
||||
/* IDSEL 0x02: cPCI bridge */
|
||||
0x1000 0 0 1 &PIC 88
|
||||
/* IDSEL 0x03: USB controller */
|
||||
0x1800 0 0 1 &PIC 91
|
||||
/* IDSEL 0x04: SATA controller */
|
||||
0x2000 0 0 1 &PIC 95
|
||||
>;
|
||||
};
|
||||
|
||||
cpu-error@0070 {
|
||||
compatible = "marvell,mv64360-cpu-error";
|
||||
reg = <0x0070 0x10 0x0128 0x28>;
|
||||
interrupts = <3>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
sram-ctrl@0380 {
|
||||
compatible = "marvell,mv64360-sram-ctrl";
|
||||
reg = <0x0380 0x80>;
|
||||
interrupts = <13>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
pci-error@1d40 {
|
||||
compatible = "marvell,mv64360-pci-error";
|
||||
reg = <0x1d40 0x40 0x0c28 0x4>;
|
||||
interrupts = <12>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
pci-error@1dc0 {
|
||||
compatible = "marvell,mv64360-pci-error";
|
||||
reg = <0x1dc0 0x40 0x0ca8 0x4>;
|
||||
interrupts = <16>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
mem-ctrl@1400 {
|
||||
compatible = "marvell,mv64360-mem-ctrl";
|
||||
reg = <0x1400 0x60>;
|
||||
interrupts = <17>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
/* Devices attached to the device controller */
|
||||
devicebus@045c {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "marvell,mv64306-devctrl";
|
||||
reg = <0x45C 0x88>;
|
||||
interrupts = <1>;
|
||||
interrupt-parent = <&PIC>;
|
||||
ranges = <0 0 0xd8100000 0x10000
|
||||
2 0 0xd8110000 0x10000
|
||||
4 0 0xf8000000 0x8000000>;
|
||||
fpga@0,0 {
|
||||
compatible = "sbs,fpga-c2k";
|
||||
reg = <0 0 0x10000>;
|
||||
};
|
||||
fpga_usart@2,0 {
|
||||
compatible = "sbs,fpga_usart-c2k";
|
||||
reg = <2 0 0x10000>;
|
||||
};
|
||||
nor_flash@4,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <4 0 0x8000000>; /* 128MB */
|
||||
bank-width = <4>;
|
||||
device-width = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "boot";
|
||||
reg = <0x00000000 0x00080000>;
|
||||
};
|
||||
partition@40000 {
|
||||
label = "kernel";
|
||||
reg = <0x00080000 0x00400000>;
|
||||
};
|
||||
partition@440000 {
|
||||
label = "initrd";
|
||||
reg = <0x00480000 0x00B80000>;
|
||||
};
|
||||
partition@1000000 {
|
||||
label = "rootfs";
|
||||
reg = <0x01000000 0x06800000>;
|
||||
};
|
||||
partition@7800000 {
|
||||
label = "recovery";
|
||||
reg = <0x07800000 0x00800000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
chosen {
|
||||
linux,stdout-path = &MPSC0;
|
||||
};
|
||||
};
|
||||
|
|
@ -8,12 +8,14 @@
|
|||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,canyonlands";
|
||||
compatible = "amcc,canyonlands";
|
||||
dcr-parent = <&/cpus/cpu@0>;
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
|
|
@ -29,13 +31,13 @@
|
|||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,460EX";
|
||||
reg = <0>;
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
timebase-frequency = <0>; /* Filled in by U-Boot */
|
||||
i-cache-line-size = <20>;
|
||||
d-cache-line-size = <20>;
|
||||
i-cache-size = <8000>;
|
||||
d-cache-size = <8000>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
|
|
@ -43,14 +45,14 @@
|
|||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0 0>; /* Filled in by U-Boot */
|
||||
reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller0 {
|
||||
compatible = "ibm,uic-460ex","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0c0 009>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
|
|
@ -60,11 +62,11 @@
|
|||
compatible = "ibm,uic-460ex","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0d0 009>;
|
||||
dcr-reg = <0x0d0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <1e 4 1f 4>; /* cascade */
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
|
|
@ -72,11 +74,11 @@
|
|||
compatible = "ibm,uic-460ex","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <2>;
|
||||
dcr-reg = <0e0 009>;
|
||||
dcr-reg = <0x0e0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <a 4 b 4>; /* cascade */
|
||||
interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
|
|
@ -84,22 +86,22 @@
|
|||
compatible = "ibm,uic-460ex","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <3>;
|
||||
dcr-reg = <0f0 009>;
|
||||
dcr-reg = <0x0f0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <10 4 11 4>; /* cascade */
|
||||
interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
SDR0: sdr {
|
||||
compatible = "ibm,sdr-460ex";
|
||||
dcr-reg = <00e 002>;
|
||||
dcr-reg = <0x00e 0x002>;
|
||||
};
|
||||
|
||||
CPR0: cpr {
|
||||
compatible = "ibm,cpr-460ex";
|
||||
dcr-reg = <00c 002>;
|
||||
dcr-reg = <0x00c 0x002>;
|
||||
};
|
||||
|
||||
plb {
|
||||
|
|
@ -111,74 +113,74 @@
|
|||
|
||||
SDRAM0: sdram {
|
||||
compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
|
||||
dcr-reg = <010 2>;
|
||||
dcr-reg = <0x010 0x002>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
|
||||
dcr-reg = <180 62>;
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <2>;
|
||||
num-rx-chans = <10>;
|
||||
num-rx-chans = <16>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&UIC2>;
|
||||
interrupts = < /*TXEOB*/ 6 4
|
||||
/*RXEOB*/ 7 4
|
||||
/*SERR*/ 3 4
|
||||
/*TXDE*/ 4 4
|
||||
/*RXDE*/ 5 4>;
|
||||
interrupts = < /*TXEOB*/ 0x6 0x4
|
||||
/*RXEOB*/ 0x7 0x4
|
||||
/*SERR*/ 0x3 0x4
|
||||
/*TXDE*/ 0x4 0x4
|
||||
/*RXDE*/ 0x5 0x4>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-460ex", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <b0000000 4 b0000000 50000000>;
|
||||
ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-460ex", "ibm,ebc";
|
||||
dcr-reg = <012 2>;
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
/* ranges property is supplied by U-Boot */
|
||||
interrupts = <6 4>;
|
||||
interrupts = <0x6 0x4>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
|
||||
nor_flash@0,0 {
|
||||
compatible = "amd,s29gl512n", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0 000000 4000000>;
|
||||
reg = <0x00000000 0x00000000 0x04000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0 1e0000>;
|
||||
reg = <0x00000000 0x001e0000>;
|
||||
};
|
||||
partition@1e0000 {
|
||||
label = "dtb";
|
||||
reg = <1e0000 20000>;
|
||||
reg = <0x001e0000 0x00020000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "ramdisk";
|
||||
reg = <200000 1400000>;
|
||||
reg = <0x00200000 0x01400000>;
|
||||
};
|
||||
partition@1600000 {
|
||||
label = "jffs2";
|
||||
reg = <1600000 400000>;
|
||||
reg = <0x01600000 0x00400000>;
|
||||
};
|
||||
partition@1a00000 {
|
||||
label = "user";
|
||||
reg = <1a00000 2560000>;
|
||||
reg = <0x01a00000 0x02560000>;
|
||||
};
|
||||
partition@3f60000 {
|
||||
label = "env";
|
||||
reg = <3f60000 40000>;
|
||||
reg = <0x03f60000 0x00040000>;
|
||||
};
|
||||
partition@3fa0000 {
|
||||
label = "u-boot";
|
||||
reg = <3fa0000 60000>;
|
||||
reg = <0x03fa0000 0x00060000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -186,103 +188,103 @@
|
|||
UART0: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600300 8>;
|
||||
virtual-reg = <ef600300>;
|
||||
reg = <0xef600300 0x00000008>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>; /* Filled in by U-Boot */
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <1 4>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600400 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600400 8>;
|
||||
virtual-reg = <ef600400>;
|
||||
reg = <0xef600400 0x00000008>;
|
||||
virtual-reg = <0xef600400>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>; /* Filled in by U-Boot */
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <1 4>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
UART2: serial@ef600500 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600500 8>;
|
||||
virtual-reg = <ef600500>;
|
||||
reg = <0xef600500 0x00000008>;
|
||||
virtual-reg = <0xef600500>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>; /* Filled in by U-Boot */
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <1d 4>;
|
||||
interrupts = <0x1d 0x4>;
|
||||
};
|
||||
|
||||
UART3: serial@ef600600 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600600 8>;
|
||||
virtual-reg = <ef600600>;
|
||||
reg = <0xef600600 0x00000008>;
|
||||
virtual-reg = <0xef600600>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>; /* Filled in by U-Boot */
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <1e 4>;
|
||||
interrupts = <0x1e 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@ef600700 {
|
||||
compatible = "ibm,iic-460ex", "ibm,iic";
|
||||
reg = <ef600700 14>;
|
||||
reg = <0xef600700 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <2 4>;
|
||||
interrupts = <0x2 0x4>;
|
||||
};
|
||||
|
||||
IIC1: i2c@ef600800 {
|
||||
compatible = "ibm,iic-460ex", "ibm,iic";
|
||||
reg = <ef600800 14>;
|
||||
reg = <0xef600800 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <3 4>;
|
||||
interrupts = <0x3 0x4>;
|
||||
};
|
||||
|
||||
ZMII0: emac-zmii@ef600d00 {
|
||||
compatible = "ibm,zmii-460ex", "ibm,zmii";
|
||||
reg = <ef600d00 c>;
|
||||
reg = <0xef600d00 0x0000000c>;
|
||||
};
|
||||
|
||||
RGMII0: emac-rgmii@ef601500 {
|
||||
compatible = "ibm,rgmii-460ex", "ibm,rgmii";
|
||||
reg = <ef601500 8>;
|
||||
reg = <0xef601500 0x00000008>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
TAH0: emac-tah@ef601350 {
|
||||
compatible = "ibm,tah-460ex", "ibm,tah";
|
||||
reg = <ef601350 30>;
|
||||
reg = <0xef601350 0x00000030>;
|
||||
};
|
||||
|
||||
TAH1: emac-tah@ef601450 {
|
||||
compatible = "ibm,tah-460ex", "ibm,tah";
|
||||
reg = <ef601450 30>;
|
||||
reg = <0xef601450 0x00000030>;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600e00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-460ex", "ibm,emac4";
|
||||
compatible = "ibm,emac-460ex", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC0>;
|
||||
interrupts = <0 1>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0 &UIC2 10 4
|
||||
/*Wake*/ 1 &UIC2 14 4>;
|
||||
reg = <ef600e00 70>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x14 0x4>;
|
||||
reg = <0xef600e00 0x000000c4>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <2328>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <00000000>;
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <0>;
|
||||
tah-device = <&TAH0>;
|
||||
|
|
@ -293,25 +295,25 @@
|
|||
|
||||
EMAC1: ethernet@ef600f00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-460ex", "ibm,emac4";
|
||||
compatible = "ibm,emac-460ex", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC1>;
|
||||
interrupts = <0 1>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0 &UIC2 11 4
|
||||
/*Wake*/ 1 &UIC2 15 4>;
|
||||
reg = <ef600f00 70>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x15 0x4>;
|
||||
reg = <0xef600f00 0x000000c4>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <1>;
|
||||
mal-rx-channel = <8>;
|
||||
cell-index = <1>;
|
||||
max-frame-size = <2328>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <00000000>;
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <1>;
|
||||
tah-device = <&TAH1>;
|
||||
|
|
@ -331,27 +333,27 @@
|
|||
primary;
|
||||
large-inbound-windows;
|
||||
enable-msi-hole;
|
||||
reg = <c 0ec00000 8 /* Config space access */
|
||||
0 0 0 /* no IACK cycles */
|
||||
c 0ed00000 4 /* Special cycles */
|
||||
c 0ec80000 100 /* Internal registers */
|
||||
c 0ec80100 fc>; /* Internal messaging registers */
|
||||
reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
|
||||
0x00000000 0x00000000 0x00000000 /* no IACK cycles */
|
||||
0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
|
||||
0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
|
||||
0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <02000000 0 80000000 0000000d 80000000 0 80000000
|
||||
01000000 0 00000000 0000000c 08000000 0 00010000>;
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 0 80000000>;
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 0 to 0x3f */
|
||||
bus-range = <0 3f>;
|
||||
bus-range = <0x0 0x3f>;
|
||||
|
||||
/* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
|
||||
interrupt-map-mask = <0000 0 0 0>;
|
||||
interrupt-map = < 0000 0 0 0 &UIC1 0 8 >;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x0>;
|
||||
interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
|
||||
};
|
||||
|
||||
PCIE0: pciex@d00000000 {
|
||||
|
|
@ -361,23 +363,23 @@
|
|||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0>; /* port number */
|
||||
reg = <d 00000000 20000000 /* Config space access */
|
||||
c 08010000 00001000>; /* Registers */
|
||||
dcr-reg = <100 020>;
|
||||
sdr-base = <300>;
|
||||
port = <0x0>; /* port number */
|
||||
reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
|
||||
0x0000000c 0x08010000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x100 0x020>;
|
||||
sdr-base = <0x300>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <02000000 0 80000000 0000000e 00000000 0 80000000
|
||||
01000000 0 00000000 0000000f 80000000 0 00010000>;
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 0 80000000>;
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 40 to 0x7f */
|
||||
bus-range = <40 7f>;
|
||||
bus-range = <0x40 0x7f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
|
|
@ -387,12 +389,12 @@
|
|||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0000 0 0 7>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0000 0 0 1 &UIC3 c 4 /* swizzled int A */
|
||||
0000 0 0 2 &UIC3 d 4 /* swizzled int B */
|
||||
0000 0 0 3 &UIC3 e 4 /* swizzled int C */
|
||||
0000 0 0 4 &UIC3 f 4 /* swizzled int D */>;
|
||||
0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
PCIE1: pciex@d20000000 {
|
||||
|
|
@ -402,23 +404,23 @@
|
|||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <1>; /* port number */
|
||||
reg = <d 20000000 20000000 /* Config space access */
|
||||
c 08011000 00001000>; /* Registers */
|
||||
dcr-reg = <120 020>;
|
||||
sdr-base = <340>;
|
||||
port = <0x1>; /* port number */
|
||||
reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
|
||||
0x0000000c 0x08011000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x120 0x020>;
|
||||
sdr-base = <0x340>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <02000000 0 80000000 0000000e 80000000 0 80000000
|
||||
01000000 0 00000000 0000000f 80010000 0 00010000>;
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 0 80000000>;
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 80 to 0xbf */
|
||||
bus-range = <80 bf>;
|
||||
bus-range = <0x80 0xbf>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
|
|
@ -428,12 +430,12 @@
|
|||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0000 0 0 7>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0000 0 0 1 &UIC3 10 4 /* swizzled int A */
|
||||
0000 0 0 2 &UIC3 11 4 /* swizzled int B */
|
||||
0000 0 0 3 &UIC3 12 4 /* swizzled int C */
|
||||
0000 0 0 4 &UIC3 13 4 /* swizzled int D */>;
|
||||
0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -11,12 +11,14 @@
|
|||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
model = "ibm,ebony";
|
||||
compatible = "ibm,ebony";
|
||||
dcr-parent = <&/cpus/cpu@0>;
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
|
|
@ -32,13 +34,13 @@
|
|||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,440GP";
|
||||
reg = <0>;
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <0>; // Filled in by zImage
|
||||
timebase-frequency = <0>; // Filled in by zImage
|
||||
i-cache-line-size = <20>;
|
||||
d-cache-line-size = <20>;
|
||||
i-cache-size = <8000>; /* 32 kB */
|
||||
d-cache-size = <8000>; /* 32 kB */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>; /* 32 kB */
|
||||
d-cache-size = <32768>; /* 32 kB */
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
|
|
@ -46,14 +48,14 @@
|
|||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0 0>; // Filled in by zImage
|
||||
reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller0 {
|
||||
compatible = "ibm,uic-440gp", "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0c0 009>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
|
|
@ -64,17 +66,17 @@
|
|||
compatible = "ibm,uic-440gp", "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0d0 009>;
|
||||
dcr-reg = <0x0d0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <1e 4 1f 4>; /* cascade */
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
CPC0: cpc {
|
||||
compatible = "ibm,cpc-440gp";
|
||||
dcr-reg = <0b0 003 0e0 010>;
|
||||
dcr-reg = <0x0b0 0x003 0x0e0 0x010>;
|
||||
// FIXME: anything else?
|
||||
};
|
||||
|
||||
|
|
@ -87,37 +89,37 @@
|
|||
|
||||
SDRAM0: memory-controller {
|
||||
compatible = "ibm,sdram-440gp";
|
||||
dcr-reg = <010 2>;
|
||||
dcr-reg = <0x010 0x002>;
|
||||
// FIXME: anything else?
|
||||
};
|
||||
|
||||
SRAM0: sram {
|
||||
compatible = "ibm,sram-440gp";
|
||||
dcr-reg = <020 8 00a 1>;
|
||||
dcr-reg = <0x020 0x008 0x00a 0x001>;
|
||||
};
|
||||
|
||||
DMA0: dma {
|
||||
// FIXME: ???
|
||||
compatible = "ibm,dma-440gp";
|
||||
dcr-reg = <100 027>;
|
||||
dcr-reg = <0x100 0x027>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-440gp", "ibm,mcmal";
|
||||
dcr-reg = <180 62>;
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <4>;
|
||||
num-rx-chans = <4>;
|
||||
interrupt-parent = <&MAL0>;
|
||||
interrupts = <0 1 2 3 4>;
|
||||
interrupts = <0x0 0x1 0x2 0x3 0x4>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
|
||||
/*RXEOB*/ 1 &UIC0 b 4
|
||||
/*SERR*/ 2 &UIC1 0 4
|
||||
/*TXDE*/ 3 &UIC1 1 4
|
||||
/*RXDE*/ 4 &UIC1 2 4>;
|
||||
interrupt-map-mask = <ffffffff>;
|
||||
interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
|
||||
/*RXEOB*/ 0x1 &UIC0 0xb 0x4
|
||||
/*SERR*/ 0x2 &UIC1 0x0 0x4
|
||||
/*TXDE*/ 0x3 &UIC1 0x1 0x4
|
||||
/*RXDE*/ 0x4 &UIC1 0x2 0x4>;
|
||||
interrupt-map-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
|
|
@ -126,34 +128,34 @@
|
|||
#size-cells = <1>;
|
||||
/* Wish there was a nicer way of specifying a full 32-bit
|
||||
range */
|
||||
ranges = <00000000 1 00000000 80000000
|
||||
80000000 1 80000000 80000000>;
|
||||
dcr-reg = <090 00b>;
|
||||
ranges = <0x00000000 0x00000001 0x00000000 0x80000000
|
||||
0x80000000 0x00000001 0x80000000 0x80000000>;
|
||||
dcr-reg = <0x090 0x00b>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <7 4>;
|
||||
interrupts = <0x7 0x4>;
|
||||
clock-frequency = <0>; // Filled in by zImage
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-440gp", "ibm,ebc";
|
||||
dcr-reg = <012 2>;
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; // Filled in by zImage
|
||||
// ranges property is supplied by zImage
|
||||
// based on firmware's configuration of the
|
||||
// EBC bridge
|
||||
interrupts = <5 4>;
|
||||
interrupts = <0x5 0x4>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
|
||||
small-flash@0,80000 {
|
||||
compatible = "jedec-flash";
|
||||
bank-width = <1>;
|
||||
reg = <0 80000 80000>;
|
||||
reg = <0x00000000 0x00080000 0x00080000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "OpenBIOS";
|
||||
reg = <0 80000>;
|
||||
reg = <0x00000000 0x00080000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
|
@ -161,101 +163,101 @@
|
|||
nvram@1,0 {
|
||||
/* NVRAM & RTC */
|
||||
compatible = "ds1743-nvram";
|
||||
#bytes = <2000>;
|
||||
reg = <1 0 2000>;
|
||||
#bytes = <0x2000>;
|
||||
reg = <0x00000001 0x00000000 0x00002000>;
|
||||
};
|
||||
|
||||
large-flash@2,0 {
|
||||
compatible = "jedec-flash";
|
||||
bank-width = <1>;
|
||||
reg = <2 0 400000>;
|
||||
reg = <0x00000002 0x00000000 0x00400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "fs";
|
||||
reg = <0 380000>;
|
||||
reg = <0x00000000 0x00380000>;
|
||||
};
|
||||
partition@380000 {
|
||||
label = "firmware";
|
||||
reg = <380000 80000>;
|
||||
reg = <0x00380000 0x00080000>;
|
||||
};
|
||||
};
|
||||
|
||||
ir@3,0 {
|
||||
reg = <3 0 10>;
|
||||
reg = <0x00000003 0x00000000 0x00000010>;
|
||||
};
|
||||
|
||||
fpga@7,0 {
|
||||
compatible = "Ebony-FPGA";
|
||||
reg = <7 0 10>;
|
||||
virtual-reg = <e8300000>;
|
||||
reg = <0x00000007 0x00000000 0x00000010>;
|
||||
virtual-reg = <0xe8300000>;
|
||||
};
|
||||
};
|
||||
|
||||
UART0: serial@40000200 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <40000200 8>;
|
||||
virtual-reg = <e0000200>;
|
||||
clock-frequency = <A8C000>;
|
||||
current-speed = <2580>;
|
||||
reg = <0x40000200 0x00000008>;
|
||||
virtual-reg = <0xe0000200>;
|
||||
clock-frequency = <11059200>;
|
||||
current-speed = <9600>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0 4>;
|
||||
interrupts = <0x0 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@40000300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <40000300 8>;
|
||||
virtual-reg = <e0000300>;
|
||||
clock-frequency = <A8C000>;
|
||||
current-speed = <2580>;
|
||||
reg = <0x40000300 0x00000008>;
|
||||
virtual-reg = <0xe0000300>;
|
||||
clock-frequency = <11059200>;
|
||||
current-speed = <9600>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <1 4>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@40000400 {
|
||||
/* FIXME */
|
||||
compatible = "ibm,iic-440gp", "ibm,iic";
|
||||
reg = <40000400 14>;
|
||||
reg = <0x40000400 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <2 4>;
|
||||
interrupts = <0x2 0x4>;
|
||||
};
|
||||
IIC1: i2c@40000500 {
|
||||
/* FIXME */
|
||||
compatible = "ibm,iic-440gp", "ibm,iic";
|
||||
reg = <40000500 14>;
|
||||
reg = <0x40000500 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <3 4>;
|
||||
interrupts = <0x3 0x4>;
|
||||
};
|
||||
|
||||
GPIO0: gpio@40000700 {
|
||||
/* FIXME */
|
||||
compatible = "ibm,gpio-440gp";
|
||||
reg = <40000700 20>;
|
||||
reg = <0x40000700 0x00000020>;
|
||||
};
|
||||
|
||||
ZMII0: emac-zmii@40000780 {
|
||||
compatible = "ibm,zmii-440gp", "ibm,zmii";
|
||||
reg = <40000780 c>;
|
||||
reg = <0x40000780 0x0000000c>;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@40000800 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-440gp", "ibm,emac";
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <1c 4 1d 4>;
|
||||
reg = <40000800 70>;
|
||||
interrupts = <0x1c 0x4 0x1d 0x4>;
|
||||
reg = <0x40000800 0x00000070>;
|
||||
local-mac-address = [000000000000]; // Filled in by zImage
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0 1>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <5dc>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
max-frame-size = <1500>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rmii";
|
||||
phy-map = <00000001>;
|
||||
phy-map = <0x00000001>;
|
||||
zmii-device = <&ZMII0>;
|
||||
zmii-channel = <0>;
|
||||
};
|
||||
|
|
@ -263,18 +265,18 @@
|
|||
device_type = "network";
|
||||
compatible = "ibm,emac-440gp", "ibm,emac";
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <1e 4 1f 4>;
|
||||
reg = <40000900 70>;
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>;
|
||||
reg = <0x40000900 0x00000070>;
|
||||
local-mac-address = [000000000000]; // Filled in by zImage
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <2 3>;
|
||||
mal-rx-channel = <1>;
|
||||
cell-index = <1>;
|
||||
max-frame-size = <5dc>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
max-frame-size = <1500>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rmii";
|
||||
phy-map = <00000001>;
|
||||
phy-map = <0x00000001>;
|
||||
zmii-device = <&ZMII0>;
|
||||
zmii-channel = <1>;
|
||||
};
|
||||
|
|
@ -282,9 +284,9 @@
|
|||
|
||||
GPT0: gpt@40000a00 {
|
||||
/* FIXME */
|
||||
reg = <40000a00 d4>;
|
||||
reg = <0x40000a00 0x000000d4>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <12 4 13 4 14 4 15 4 16 4>;
|
||||
interrupts = <0x12 0x4 0x13 0x4 0x14 0x4 0x15 0x4 0x16 0x4>;
|
||||
};
|
||||
|
||||
};
|
||||
|
|
@ -296,35 +298,35 @@
|
|||
#address-cells = <3>;
|
||||
compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix";
|
||||
primary;
|
||||
reg = <2 0ec00000 8 /* Config space access */
|
||||
0 0 0 /* no IACK cycles */
|
||||
2 0ed00000 4 /* Special cycles */
|
||||
2 0ec80000 f0 /* Internal registers */
|
||||
2 0ec80100 fc>; /* Internal messaging registers */
|
||||
reg = <0x00000002 0x0ec00000 0x00000008 /* Config space access */
|
||||
0x00000000 0x00000000 0x00000000 /* no IACK cycles */
|
||||
0x00000002 0x0ed00000 0x00000004 /* Special cycles */
|
||||
0x00000002 0x0ec80000 0x000000f0 /* Internal registers */
|
||||
0x00000002 0x0ec80100 0x000000fc>; /* Internal messaging registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <02000000 0 80000000 00000003 80000000 0 80000000
|
||||
01000000 0 00000000 00000002 08000000 0 00010000>;
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x00000003 0x80000000 0x00000000 0x80000000
|
||||
0x01000000 0x00000000 0x00000000 0x00000002 0x08000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 0 80000000>;
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* Ebony has all 4 IRQ pins tied together per slot */
|
||||
interrupt-map-mask = <f800 0 0 0>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 1 */
|
||||
0800 0 0 0 &UIC0 17 8
|
||||
0x800 0x0 0x0 0x0 &UIC0 0x17 0x8
|
||||
|
||||
/* IDSEL 2 */
|
||||
1000 0 0 0 &UIC0 18 8
|
||||
0x1000 0x0 0x0 0x0 &UIC0 0x18 0x8
|
||||
|
||||
/* IDSEL 3 */
|
||||
1800 0 0 0 &UIC0 19 8
|
||||
0x1800 0x0 0x0 0x0 &UIC0 0x19 0x8
|
||||
|
||||
/* IDSEL 4 */
|
||||
2000 0 0 0 &UIC0 1a 8
|
||||
0x2000 0x0 0x0 0x0 &UIC0 0x1a 0x8
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -9,12 +9,14 @@
|
|||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "ep405";
|
||||
compatible = "ep405";
|
||||
dcr-parent = <&/cpus/cpu@0>;
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC;
|
||||
|
|
@ -29,13 +31,13 @@
|
|||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,405GP";
|
||||
reg = <0>;
|
||||
clock-frequency = <bebc200>; /* Filled in by zImage */
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <200000000>; /* Filled in by zImage */
|
||||
timebase-frequency = <0>; /* Filled in by zImage */
|
||||
i-cache-line-size = <20>;
|
||||
d-cache-line-size = <20>;
|
||||
i-cache-size = <4000>;
|
||||
d-cache-size = <4000>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <16384>;
|
||||
d-cache-size = <16384>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
|
|
@ -43,14 +45,14 @@
|
|||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0>; /* Filled in by zImage */
|
||||
reg = <0x00000000 0x00000000>; /* Filled in by zImage */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller {
|
||||
compatible = "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0c0 9>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
|
|
@ -65,91 +67,91 @@
|
|||
|
||||
SDRAM0: memory-controller {
|
||||
compatible = "ibm,sdram-405gp";
|
||||
dcr-reg = <010 2>;
|
||||
dcr-reg = <0x010 0x002>;
|
||||
};
|
||||
|
||||
MAL: mcmal {
|
||||
compatible = "ibm,mcmal-405gp", "ibm,mcmal";
|
||||
dcr-reg = <180 62>;
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <1>;
|
||||
num-rx-chans = <1>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <
|
||||
b 4 /* TXEOB */
|
||||
c 4 /* RXEOB */
|
||||
a 4 /* SERR */
|
||||
d 4 /* TXDE */
|
||||
e 4 /* RXDE */>;
|
||||
0xb 0x4 /* TXEOB */
|
||||
0xc 0x4 /* RXEOB */
|
||||
0xa 0x4 /* SERR */
|
||||
0xd 0x4 /* TXDE */
|
||||
0xe 0x4 /* RXDE */>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-405gp", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <ef600000 ef600000 a00000>;
|
||||
dcr-reg = <0a0 5>;
|
||||
ranges = <0xef600000 0xef600000 0x00a00000>;
|
||||
dcr-reg = <0x0a0 0x005>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
UART0: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600300 8>;
|
||||
virtual-reg = <ef600300>;
|
||||
reg = <0xef600300 0x00000008>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
current-speed = <2580>;
|
||||
current-speed = <9600>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0 4>;
|
||||
interrupts = <0x0 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600400 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600400 8>;
|
||||
virtual-reg = <ef600400>;
|
||||
reg = <0xef600400 0x00000008>;
|
||||
virtual-reg = <0xef600400>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
current-speed = <2580>;
|
||||
current-speed = <9600>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <1 4>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
IIC: i2c@ef600500 {
|
||||
compatible = "ibm,iic-405gp", "ibm,iic";
|
||||
reg = <ef600500 11>;
|
||||
reg = <0xef600500 0x00000011>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <2 4>;
|
||||
interrupts = <0x2 0x4>;
|
||||
};
|
||||
|
||||
GPIO: gpio@ef600700 {
|
||||
compatible = "ibm,gpio-405gp";
|
||||
reg = <ef600700 20>;
|
||||
reg = <0xef600700 0x00000020>;
|
||||
};
|
||||
|
||||
EMAC: ethernet@ef600800 {
|
||||
linux,network-index = <0>;
|
||||
linux,network-index = <0x0>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-405gp", "ibm,emac";
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <
|
||||
f 4 /* Ethernet */
|
||||
9 4 /* Ethernet Wake Up */>;
|
||||
0xf 0x4 /* Ethernet */
|
||||
0x9 0x4 /* Ethernet Wake Up */>;
|
||||
local-mac-address = [000000000000]; /* Filled in by zImage */
|
||||
reg = <ef600800 70>;
|
||||
reg = <0xef600800 0x00000070>;
|
||||
mal-device = <&MAL>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <5dc>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
max-frame-size = <1500>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rmii";
|
||||
phy-map = <00000000>;
|
||||
phy-map = <0x00000000>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-405gp", "ibm,ebc";
|
||||
dcr-reg = <012 2>;
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
|
|
@ -163,13 +165,13 @@
|
|||
/* NVRAM and RTC */
|
||||
nvrtc@4,200000 {
|
||||
compatible = "ds1742";
|
||||
reg = <4 200000 0>; /* size fixed up by zImage */
|
||||
reg = <0x00000004 0x00200000 0x00000000>; /* size fixed up by zImage */
|
||||
};
|
||||
|
||||
/* "BCSR" CPLD contains a PCI irq controller */
|
||||
bcsr@4,0 {
|
||||
compatible = "ep405-bcsr";
|
||||
reg = <4 0 10>;
|
||||
reg = <0x00000004 0x00000000 0x00000010>;
|
||||
interrupt-controller;
|
||||
/* Routing table */
|
||||
irq-routing = [ 00 /* SYSERR */
|
||||
|
|
@ -198,26 +200,26 @@
|
|||
#address-cells = <3>;
|
||||
compatible = "ibm,plb405gp-pci", "ibm,plb-pci";
|
||||
primary;
|
||||
reg = <eec00000 8 /* Config space access */
|
||||
eed80000 4 /* IACK */
|
||||
eed80000 4 /* Special cycle */
|
||||
ef480000 40>; /* Internal registers */
|
||||
reg = <0xeec00000 0x00000008 /* Config space access */
|
||||
0xeed80000 0x00000004 /* IACK */
|
||||
0xeed80000 0x00000004 /* Special cycle */
|
||||
0xef480000 0x00000040>; /* Internal registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed. Chip supports a second
|
||||
* IO range but we don't use it for now
|
||||
*/
|
||||
ranges = <02000000 0 80000000 80000000 0 20000000
|
||||
01000000 0 00000000 e8000000 0 00010000>;
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000
|
||||
0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 80000000>;
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* That's all I know about IRQs on that thing ... */
|
||||
interrupt-map-mask = <f800 0 0 0>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
|
||||
interrupt-map = <
|
||||
/* USB */
|
||||
7000 0 0 0 &UIC0 1e 8 /* IRQ5 */
|
||||
0x7000 0x0 0x0 0x0 &UIC0 0x1e 0x8 /* IRQ5 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -8,12 +8,14 @@
|
|||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,glacier";
|
||||
compatible = "amcc,glacier", "amcc,canyonlands";
|
||||
dcr-parent = <&/cpus/cpu@0>;
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
|
|
@ -31,13 +33,13 @@
|
|||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,460GT";
|
||||
reg = <0>;
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
timebase-frequency = <0>; /* Filled in by U-Boot */
|
||||
i-cache-line-size = <20>;
|
||||
d-cache-line-size = <20>;
|
||||
i-cache-size = <8000>;
|
||||
d-cache-size = <8000>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
|
|
@ -45,14 +47,14 @@
|
|||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0 0>; /* Filled in by U-Boot */
|
||||
reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller0 {
|
||||
compatible = "ibm,uic-460gt","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0c0 009>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
|
|
@ -62,11 +64,11 @@
|
|||
compatible = "ibm,uic-460gt","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0d0 009>;
|
||||
dcr-reg = <0x0d0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <1e 4 1f 4>; /* cascade */
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
|
|
@ -74,11 +76,11 @@
|
|||
compatible = "ibm,uic-460gt","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <2>;
|
||||
dcr-reg = <0e0 009>;
|
||||
dcr-reg = <0x0e0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <a 4 b 4>; /* cascade */
|
||||
interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
|
|
@ -86,22 +88,22 @@
|
|||
compatible = "ibm,uic-460gt","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <3>;
|
||||
dcr-reg = <0f0 009>;
|
||||
dcr-reg = <0x0f0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <10 4 11 4>; /* cascade */
|
||||
interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
SDR0: sdr {
|
||||
compatible = "ibm,sdr-460gt";
|
||||
dcr-reg = <00e 002>;
|
||||
dcr-reg = <0x00e 0x002>;
|
||||
};
|
||||
|
||||
CPR0: cpr {
|
||||
compatible = "ibm,cpr-460gt";
|
||||
dcr-reg = <00c 002>;
|
||||
dcr-reg = <0x00c 0x002>;
|
||||
};
|
||||
|
||||
plb {
|
||||
|
|
@ -113,75 +115,75 @@
|
|||
|
||||
SDRAM0: sdram {
|
||||
compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
|
||||
dcr-reg = <010 2>;
|
||||
dcr-reg = <0x010 0x002>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
|
||||
dcr-reg = <180 62>;
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <4>;
|
||||
num-rx-chans = <20>;
|
||||
num-rx-chans = <32>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&UIC2>;
|
||||
interrupts = < /*TXEOB*/ 6 4
|
||||
/*RXEOB*/ 7 4
|
||||
/*SERR*/ 3 4
|
||||
/*TXDE*/ 4 4
|
||||
/*RXDE*/ 5 4>;
|
||||
desc-base-addr-high = <8>;
|
||||
interrupts = < /*TXEOB*/ 0x6 0x4
|
||||
/*RXEOB*/ 0x7 0x4
|
||||
/*SERR*/ 0x3 0x4
|
||||
/*TXDE*/ 0x4 0x4
|
||||
/*RXDE*/ 0x5 0x4>;
|
||||
desc-base-addr-high = <0x8>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-460gt", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <b0000000 4 b0000000 50000000>;
|
||||
ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-460gt", "ibm,ebc";
|
||||
dcr-reg = <012 2>;
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
/* ranges property is supplied by U-Boot */
|
||||
interrupts = <6 4>;
|
||||
interrupts = <0x6 0x4>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
|
||||
nor_flash@0,0 {
|
||||
compatible = "amd,s29gl512n", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0 000000 4000000>;
|
||||
reg = <0x00000000 0x00000000 0x04000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0 1e0000>;
|
||||
reg = <0x00000000 0x001e0000>;
|
||||
};
|
||||
partition@1e0000 {
|
||||
label = "dtb";
|
||||
reg = <1e0000 20000>;
|
||||
reg = <0x001e0000 0x00020000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "ramdisk";
|
||||
reg = <200000 1400000>;
|
||||
reg = <0x00200000 0x01400000>;
|
||||
};
|
||||
partition@1600000 {
|
||||
label = "jffs2";
|
||||
reg = <1600000 400000>;
|
||||
reg = <0x01600000 0x00400000>;
|
||||
};
|
||||
partition@1a00000 {
|
||||
label = "user";
|
||||
reg = <1a00000 2560000>;
|
||||
reg = <0x01a00000 0x02560000>;
|
||||
};
|
||||
partition@3f60000 {
|
||||
label = "env";
|
||||
reg = <3f60000 40000>;
|
||||
reg = <0x03f60000 0x00040000>;
|
||||
};
|
||||
partition@3fa0000 {
|
||||
label = "u-boot";
|
||||
reg = <3fa0000 60000>;
|
||||
reg = <0x03fa0000 0x00060000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -189,109 +191,109 @@
|
|||
UART0: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600300 8>;
|
||||
virtual-reg = <ef600300>;
|
||||
reg = <0xef600300 0x00000008>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>; /* Filled in by U-Boot */
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <1 4>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600400 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600400 8>;
|
||||
virtual-reg = <ef600400>;
|
||||
reg = <0xef600400 0x00000008>;
|
||||
virtual-reg = <0xef600400>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>; /* Filled in by U-Boot */
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <1 4>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
UART2: serial@ef600500 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600500 8>;
|
||||
virtual-reg = <ef600500>;
|
||||
reg = <0xef600500 0x00000008>;
|
||||
virtual-reg = <0xef600500>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>; /* Filled in by U-Boot */
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <1d 4>;
|
||||
interrupts = <0x1d 0x4>;
|
||||
};
|
||||
|
||||
UART3: serial@ef600600 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600600 8>;
|
||||
virtual-reg = <ef600600>;
|
||||
reg = <0xef600600 0x00000008>;
|
||||
virtual-reg = <0xef600600>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>; /* Filled in by U-Boot */
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <1e 4>;
|
||||
interrupts = <0x1e 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@ef600700 {
|
||||
compatible = "ibm,iic-460gt", "ibm,iic";
|
||||
reg = <ef600700 14>;
|
||||
reg = <0xef600700 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <2 4>;
|
||||
interrupts = <0x2 0x4>;
|
||||
};
|
||||
|
||||
IIC1: i2c@ef600800 {
|
||||
compatible = "ibm,iic-460gt", "ibm,iic";
|
||||
reg = <ef600800 14>;
|
||||
reg = <0xef600800 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <3 4>;
|
||||
interrupts = <0x3 0x4>;
|
||||
};
|
||||
|
||||
ZMII0: emac-zmii@ef600d00 {
|
||||
compatible = "ibm,zmii-460gt", "ibm,zmii";
|
||||
reg = <ef600d00 c>;
|
||||
reg = <0xef600d00 0x0000000c>;
|
||||
};
|
||||
|
||||
RGMII0: emac-rgmii@ef601500 {
|
||||
compatible = "ibm,rgmii-460gt", "ibm,rgmii";
|
||||
reg = <ef601500 8>;
|
||||
reg = <0xef601500 0x00000008>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
RGMII1: emac-rgmii@ef601600 {
|
||||
compatible = "ibm,rgmii-460gt", "ibm,rgmii";
|
||||
reg = <ef601600 8>;
|
||||
reg = <0xef601600 0x00000008>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
TAH0: emac-tah@ef601350 {
|
||||
compatible = "ibm,tah-460gt", "ibm,tah";
|
||||
reg = <ef601350 30>;
|
||||
reg = <0xef601350 0x00000030>;
|
||||
};
|
||||
|
||||
TAH1: emac-tah@ef601450 {
|
||||
compatible = "ibm,tah-460gt", "ibm,tah";
|
||||
reg = <ef601450 30>;
|
||||
reg = <0xef601450 0x00000030>;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600e00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-460gt", "ibm,emac4";
|
||||
interrupt-parent = <&EMAC0>;
|
||||
interrupts = <0 1>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0 &UIC2 10 4
|
||||
/*Wake*/ 1 &UIC2 14 4>;
|
||||
reg = <ef600e00 70>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x14 0x4>;
|
||||
reg = <0xef600e00 0x00000074>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <2328>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <00000000>;
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <0>;
|
||||
tah-device = <&TAH0>;
|
||||
|
|
@ -304,23 +306,23 @@
|
|||
device_type = "network";
|
||||
compatible = "ibm,emac-460gt", "ibm,emac4";
|
||||
interrupt-parent = <&EMAC1>;
|
||||
interrupts = <0 1>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0 &UIC2 11 4
|
||||
/*Wake*/ 1 &UIC2 15 4>;
|
||||
reg = <ef600f00 70>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x15 0x4>;
|
||||
reg = <0xef600f00 0x00000074>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <1>;
|
||||
mal-rx-channel = <8>;
|
||||
cell-index = <1>;
|
||||
max-frame-size = <2328>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <00000000>;
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <1>;
|
||||
tah-device = <&TAH1>;
|
||||
|
|
@ -334,23 +336,23 @@
|
|||
device_type = "network";
|
||||
compatible = "ibm,emac-460gt", "ibm,emac4";
|
||||
interrupt-parent = <&EMAC2>;
|
||||
interrupts = <0 1>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0 &UIC2 12 4
|
||||
/*Wake*/ 1 &UIC2 16 4>;
|
||||
reg = <ef601100 70>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x16 0x4>;
|
||||
reg = <0xef601100 0x00000074>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <2>;
|
||||
mal-rx-channel = <10>;
|
||||
mal-rx-channel = <16>;
|
||||
cell-index = <2>;
|
||||
max-frame-size = <2328>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <00000000>;
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII1>;
|
||||
rgmii-channel = <0>;
|
||||
has-inverted-stacr-oc;
|
||||
|
|
@ -362,23 +364,23 @@
|
|||
device_type = "network";
|
||||
compatible = "ibm,emac-460gt", "ibm,emac4";
|
||||
interrupt-parent = <&EMAC3>;
|
||||
interrupts = <0 1>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0 &UIC2 13 4
|
||||
/*Wake*/ 1 &UIC2 17 4>;
|
||||
reg = <ef601200 70>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC2 0x13 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x17 0x4>;
|
||||
reg = <0xef601200 0x00000074>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <3>;
|
||||
mal-rx-channel = <18>;
|
||||
mal-rx-channel = <24>;
|
||||
cell-index = <3>;
|
||||
max-frame-size = <2328>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <00000000>;
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII1>;
|
||||
rgmii-channel = <1>;
|
||||
has-inverted-stacr-oc;
|
||||
|
|
@ -396,27 +398,27 @@
|
|||
primary;
|
||||
large-inbound-windows;
|
||||
enable-msi-hole;
|
||||
reg = <c 0ec00000 8 /* Config space access */
|
||||
0 0 0 /* no IACK cycles */
|
||||
c 0ed00000 4 /* Special cycles */
|
||||
c 0ec80000 100 /* Internal registers */
|
||||
c 0ec80100 fc>; /* Internal messaging registers */
|
||||
reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
|
||||
0x00000000 0x00000000 0x00000000 /* no IACK cycles */
|
||||
0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
|
||||
0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
|
||||
0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <02000000 0 80000000 0000000d 80000000 0 80000000
|
||||
01000000 0 00000000 0000000c 08000000 0 00010000>;
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 0 80000000>;
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 0 to 0x3f */
|
||||
bus-range = <0 3f>;
|
||||
bus-range = <0x0 0x3f>;
|
||||
|
||||
/* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
|
||||
interrupt-map-mask = <0000 0 0 0>;
|
||||
interrupt-map = < 0000 0 0 0 &UIC1 0 8 >;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x0>;
|
||||
interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
|
||||
};
|
||||
|
||||
PCIE0: pciex@d00000000 {
|
||||
|
|
@ -426,23 +428,23 @@
|
|||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0>; /* port number */
|
||||
reg = <d 00000000 20000000 /* Config space access */
|
||||
c 08010000 00001000>; /* Registers */
|
||||
dcr-reg = <100 020>;
|
||||
sdr-base = <300>;
|
||||
port = <0x0>; /* port number */
|
||||
reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
|
||||
0x0000000c 0x08010000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x100 0x020>;
|
||||
sdr-base = <0x300>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <02000000 0 80000000 0000000e 00000000 0 80000000
|
||||
01000000 0 00000000 0000000f 80000000 0 00010000>;
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 0 80000000>;
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 40 to 0x7f */
|
||||
bus-range = <40 7f>;
|
||||
bus-range = <0x40 0x7f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
|
|
@ -452,12 +454,12 @@
|
|||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0000 0 0 7>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0000 0 0 1 &UIC3 c 4 /* swizzled int A */
|
||||
0000 0 0 2 &UIC3 d 4 /* swizzled int B */
|
||||
0000 0 0 3 &UIC3 e 4 /* swizzled int C */
|
||||
0000 0 0 4 &UIC3 f 4 /* swizzled int D */>;
|
||||
0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
PCIE1: pciex@d20000000 {
|
||||
|
|
@ -467,23 +469,23 @@
|
|||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <1>; /* port number */
|
||||
reg = <d 20000000 20000000 /* Config space access */
|
||||
c 08011000 00001000>; /* Registers */
|
||||
dcr-reg = <120 020>;
|
||||
sdr-base = <340>;
|
||||
port = <0x1>; /* port number */
|
||||
reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
|
||||
0x0000000c 0x08011000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x120 0x020>;
|
||||
sdr-base = <0x340>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <02000000 0 80000000 0000000e 80000000 0 80000000
|
||||
01000000 0 00000000 0000000f 80010000 0 00010000>;
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 0 80000000>;
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 80 to 0xbf */
|
||||
bus-range = <80 bf>;
|
||||
bus-range = <0x80 0xbf>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
|
|
@ -493,12 +495,12 @@
|
|||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0000 0 0 7>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0000 0 0 1 &UIC3 10 4 /* swizzled int A */
|
||||
0000 0 0 2 &UIC3 11 4 /* swizzled int B */
|
||||
0000 0 0 3 &UIC3 12 4 /* swizzled int C */
|
||||
0000 0 0 4 &UIC3 13 4 /* swizzled int D */>;
|
||||
0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -8,12 +8,14 @@
|
|||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,haleakala";
|
||||
compatible = "amcc,haleakala", "amcc,kilauea";
|
||||
dcr-parent = <&/cpus/cpu@0>;
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
|
|
@ -28,13 +30,13 @@
|
|||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,405EXr";
|
||||
reg = <0>;
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
timebase-frequency = <0>; /* Filled in by U-Boot */
|
||||
i-cache-line-size = <20>;
|
||||
d-cache-line-size = <20>;
|
||||
i-cache-size = <4000>; /* 16 kB */
|
||||
d-cache-size = <4000>; /* 16 kB */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <16384>; /* 16 kB */
|
||||
d-cache-size = <16384>; /* 16 kB */
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
|
|
@ -42,14 +44,14 @@
|
|||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0>; /* Filled in by U-Boot */
|
||||
reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller {
|
||||
compatible = "ibm,uic-405exr", "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0c0 009>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
|
|
@ -59,11 +61,11 @@
|
|||
compatible = "ibm,uic-405exr","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0d0 009>;
|
||||
dcr-reg = <0x0d0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <1e 4 1f 4>; /* cascade */
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
|
|
@ -71,11 +73,11 @@
|
|||
compatible = "ibm,uic-405exr","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <2>;
|
||||
dcr-reg = <0e0 009>;
|
||||
dcr-reg = <0x0e0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <1c 4 1d 4>; /* cascade */
|
||||
interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
|
|
@ -88,72 +90,72 @@
|
|||
|
||||
SDRAM0: memory-controller {
|
||||
compatible = "ibm,sdram-405exr";
|
||||
dcr-reg = <010 2>;
|
||||
dcr-reg = <0x010 0x002>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-405exr", "ibm,mcmal2";
|
||||
dcr-reg = <180 62>;
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <2>;
|
||||
num-rx-chans = <2>;
|
||||
interrupt-parent = <&MAL0>;
|
||||
interrupts = <0 1 2 3 4>;
|
||||
interrupts = <0x0 0x1 0x2 0x3 0x4>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
|
||||
/*RXEOB*/ 1 &UIC0 b 4
|
||||
/*SERR*/ 2 &UIC1 0 4
|
||||
/*TXDE*/ 3 &UIC1 1 4
|
||||
/*RXDE*/ 4 &UIC1 2 4>;
|
||||
interrupt-map-mask = <ffffffff>;
|
||||
interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
|
||||
/*RXEOB*/ 0x1 &UIC0 0xb 0x4
|
||||
/*SERR*/ 0x2 &UIC1 0x0 0x4
|
||||
/*TXDE*/ 0x3 &UIC1 0x1 0x4
|
||||
/*RXDE*/ 0x4 &UIC1 0x2 0x4>;
|
||||
interrupt-map-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-405exr", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <80000000 80000000 10000000
|
||||
ef600000 ef600000 a00000
|
||||
f0000000 f0000000 10000000>;
|
||||
dcr-reg = <0a0 5>;
|
||||
ranges = <0x80000000 0x80000000 0x10000000
|
||||
0xef600000 0xef600000 0x00a00000
|
||||
0xf0000000 0xf0000000 0x10000000>;
|
||||
dcr-reg = <0x0a0 0x005>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-405exr", "ibm,ebc";
|
||||
dcr-reg = <012 2>;
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
/* ranges property is supplied by U-Boot */
|
||||
interrupts = <5 1>;
|
||||
interrupts = <0x5 0x1>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
|
||||
nor_flash@0,0 {
|
||||
compatible = "amd,s29gl512n", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0 000000 4000000>;
|
||||
reg = <0x00000000 0x00000000 0x04000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0 200000>;
|
||||
reg = <0x00000000 0x00200000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "root";
|
||||
reg = <200000 200000>;
|
||||
reg = <0x00200000 0x00200000>;
|
||||
};
|
||||
partition@400000 {
|
||||
label = "user";
|
||||
reg = <400000 3b60000>;
|
||||
reg = <0x00400000 0x03b60000>;
|
||||
};
|
||||
partition@3f60000 {
|
||||
label = "env";
|
||||
reg = <3f60000 40000>;
|
||||
reg = <0x03f60000 0x00040000>;
|
||||
};
|
||||
partition@3fa0000 {
|
||||
label = "u-boot";
|
||||
reg = <3fa0000 60000>;
|
||||
reg = <0x03fa0000 0x00060000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -161,68 +163,68 @@
|
|||
UART0: serial@ef600200 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600200 8>;
|
||||
virtual-reg = <ef600200>;
|
||||
reg = <0xef600200 0x00000008>;
|
||||
virtual-reg = <0xef600200>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <1a 4>;
|
||||
interrupts = <0x1a 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600300 8>;
|
||||
virtual-reg = <ef600300>;
|
||||
reg = <0xef600300 0x00000008>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <1 4>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@ef600400 {
|
||||
compatible = "ibm,iic-405exr", "ibm,iic";
|
||||
reg = <ef600400 14>;
|
||||
reg = <0xef600400 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <2 4>;
|
||||
interrupts = <0x2 0x4>;
|
||||
};
|
||||
|
||||
IIC1: i2c@ef600500 {
|
||||
compatible = "ibm,iic-405exr", "ibm,iic";
|
||||
reg = <ef600500 14>;
|
||||
reg = <0xef600500 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <7 4>;
|
||||
interrupts = <0x7 0x4>;
|
||||
};
|
||||
|
||||
|
||||
RGMII0: emac-rgmii@ef600b00 {
|
||||
compatible = "ibm,rgmii-405exr", "ibm,rgmii";
|
||||
reg = <ef600b00 104>;
|
||||
reg = <0xef600b00 0x00000104>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600900 {
|
||||
linux,network-index = <0>;
|
||||
linux,network-index = <0x0>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-405exr", "ibm,emac4";
|
||||
compatible = "ibm,emac-405exr", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC0>;
|
||||
interrupts = <0 1>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0 &UIC0 18 4
|
||||
/*Wake*/ 1 &UIC1 1d 4>;
|
||||
reg = <ef600900 70>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
|
||||
/*Wake*/ 0x1 &UIC1 0x1d 0x4>;
|
||||
reg = <0xef600900 0x000000c4>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <2328>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <00000000>;
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <0>;
|
||||
has-inverted-stacr-oc;
|
||||
|
|
@ -237,23 +239,23 @@
|
|||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0>; /* port number */
|
||||
reg = <a0000000 20000000 /* Config space access */
|
||||
ef000000 00001000>; /* Registers */
|
||||
dcr-reg = <040 020>;
|
||||
sdr-base = <400>;
|
||||
port = <0x0>; /* port number */
|
||||
reg = <0xa0000000 0x20000000 /* Config space access */
|
||||
0xef000000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x040 0x020>;
|
||||
sdr-base = <0x400>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <02000000 0 80000000 90000000 0 08000000
|
||||
01000000 0 00000000 e0000000 0 00010000>;
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000
|
||||
0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 80000000>;
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 0x00 to 0x3f */
|
||||
bus-range = <00 3f>;
|
||||
bus-range = <0x0 0x3f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
|
|
@ -263,12 +265,12 @@
|
|||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0000 0 0 7>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0000 0 0 1 &UIC2 0 4 /* swizzled int A */
|
||||
0000 0 0 2 &UIC2 1 4 /* swizzled int B */
|
||||
0000 0 0 3 &UIC2 2 4 /* swizzled int C */
|
||||
0000 0 0 4 &UIC2 3 4 /* swizzled int D */>;
|
||||
0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -10,6 +10,8 @@
|
|||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "41K7339";
|
||||
compatible = "ibm,holly";
|
||||
|
|
@ -21,22 +23,22 @@
|
|||
#size-cells =<0>;
|
||||
PowerPC,750CL@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <20>;
|
||||
i-cache-line-size = <20>;
|
||||
d-cache-size = <8000>;
|
||||
i-cache-size = <8000>;
|
||||
d-cache-sets = <80>;
|
||||
i-cache-sets = <80>;
|
||||
timebase-frequency = <2faf080>;
|
||||
clock-frequency = <23c34600>;
|
||||
bus-frequency = <bebc200>;
|
||||
reg = <0x00000000>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-sets = <128>;
|
||||
i-cache-sets = <128>;
|
||||
timebase-frequency = <50000000>;
|
||||
clock-frequency = <600000000>;
|
||||
bus-frequency = <200000000>;
|
||||
};
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <00000000 20000000>;
|
||||
reg = <0x00000000 0x20000000>;
|
||||
};
|
||||
|
||||
tsi109@c0000000 {
|
||||
|
|
@ -44,33 +46,33 @@
|
|||
compatible = "tsi109-bridge", "tsi108-bridge";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <00000000 c0000000 00010000>;
|
||||
reg = <c0000000 00010000>;
|
||||
ranges = <0x00000000 0xc0000000 0x00010000>;
|
||||
reg = <0xc0000000 0x00010000>;
|
||||
|
||||
i2c@7000 {
|
||||
device_type = "i2c";
|
||||
compatible = "tsi109-i2c", "tsi108-i2c";
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <e 2>;
|
||||
reg = <7000 400>;
|
||||
interrupts = <0xe 0x2>;
|
||||
reg = <0x00007000 0x00000400>;
|
||||
};
|
||||
|
||||
MDIO: mdio@6000 {
|
||||
device_type = "mdio";
|
||||
compatible = "tsi109-mdio", "tsi108-mdio";
|
||||
reg = <6000 50>;
|
||||
reg = <0x00006000 0x00000050>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PHY1: ethernet-phy@1 {
|
||||
compatible = "bcm5461a";
|
||||
reg = <1>;
|
||||
reg = <0x00000001>;
|
||||
txc-rxc-delay-disable;
|
||||
};
|
||||
|
||||
PHY2: ethernet-phy@2 {
|
||||
compatible = "bcm5461a";
|
||||
reg = <2>;
|
||||
reg = <0x00000002>;
|
||||
txc-rxc-delay-disable;
|
||||
};
|
||||
};
|
||||
|
|
@ -80,10 +82,10 @@
|
|||
compatible = "tsi109-ethernet", "tsi108-ethernet";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <6000 200>;
|
||||
reg = <0x00006000 0x00000200>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <10 2>;
|
||||
interrupts = <0x10 0x2>;
|
||||
mdio-handle = <&MDIO>;
|
||||
phy-handle = <&PHY1>;
|
||||
};
|
||||
|
|
@ -93,10 +95,10 @@
|
|||
compatible = "tsi109-ethernet", "tsi108-ethernet";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <6400 200>;
|
||||
reg = <0x00006400 0x00000200>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <11 2>;
|
||||
interrupts = <0x11 0x2>;
|
||||
mdio-handle = <&MDIO>;
|
||||
phy-handle = <&PHY2>;
|
||||
};
|
||||
|
|
@ -104,23 +106,23 @@
|
|||
serial@7808 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <7808 200>;
|
||||
virtual-reg = <c0007808>;
|
||||
clock-frequency = <3F9C6000>;
|
||||
current-speed = <1c200>;
|
||||
reg = <0x00007808 0x00000200>;
|
||||
virtual-reg = <0xc0007808>;
|
||||
clock-frequency = <1067212800>;
|
||||
current-speed = <115200>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <c 2>;
|
||||
interrupts = <0xc 0x2>;
|
||||
};
|
||||
|
||||
serial@7c08 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <7c08 200>;
|
||||
virtual-reg = <c0007c08>;
|
||||
clock-frequency = <3F9C6000>;
|
||||
current-speed = <1c200>;
|
||||
reg = <0x00007c08 0x00000200>;
|
||||
virtual-reg = <0xc0007c08>;
|
||||
clock-frequency = <1067212800>;
|
||||
current-speed = <115200>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <d 2>;
|
||||
interrupts = <0xd 0x2>;
|
||||
};
|
||||
|
||||
MPIC: pic@7400 {
|
||||
|
|
@ -128,7 +130,7 @@
|
|||
compatible = "chrp,open-pic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <7400 400>;
|
||||
reg = <0x00007400 0x00000400>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
|
|
@ -138,42 +140,42 @@
|
|||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <1000 1000>;
|
||||
bus-range = <0 0>;
|
||||
reg = <0x00001000 0x00001000>;
|
||||
bus-range = <0x0 0x0>;
|
||||
/*----------------------------------------------------+
|
||||
| PCI memory range.
|
||||
| 01 denotes I/O space
|
||||
| 02 denotes 32-bit memory space
|
||||
+----------------------------------------------------*/
|
||||
ranges = <02000000 0 40000000 40000000 0 10000000
|
||||
01000000 0 00000000 7e000000 0 00010000>;
|
||||
clock-frequency = <7f28154>;
|
||||
ranges = <0x02000000 0x00000000 0x40000000 0x40000000 0x00000000 0x10000000
|
||||
0x01000000 0x00000000 0x00000000 0x7e000000 0x00000000 0x00010000>;
|
||||
clock-frequency = <133333332>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <17 2>;
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupts = <0x17 0x2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
/*----------------------------------------------------+
|
||||
| The INTA, INTB, INTC, INTD are shared.
|
||||
+----------------------------------------------------*/
|
||||
interrupt-map = <
|
||||
0800 0 0 1 &RT0 24 0
|
||||
0800 0 0 2 &RT0 25 0
|
||||
0800 0 0 3 &RT0 26 0
|
||||
0800 0 0 4 &RT0 27 0
|
||||
0x800 0x0 0x0 0x1 &RT0 0x24 0x0
|
||||
0x800 0x0 0x0 0x2 &RT0 0x25 0x0
|
||||
0x800 0x0 0x0 0x3 &RT0 0x26 0x0
|
||||
0x800 0x0 0x0 0x4 &RT0 0x27 0x0
|
||||
|
||||
1000 0 0 1 &RT0 25 0
|
||||
1000 0 0 2 &RT0 26 0
|
||||
1000 0 0 3 &RT0 27 0
|
||||
1000 0 0 4 &RT0 24 0
|
||||
0x1000 0x0 0x0 0x1 &RT0 0x25 0x0
|
||||
0x1000 0x0 0x0 0x2 &RT0 0x26 0x0
|
||||
0x1000 0x0 0x0 0x3 &RT0 0x27 0x0
|
||||
0x1000 0x0 0x0 0x4 &RT0 0x24 0x0
|
||||
|
||||
1800 0 0 1 &RT0 26 0
|
||||
1800 0 0 2 &RT0 27 0
|
||||
1800 0 0 3 &RT0 24 0
|
||||
1800 0 0 4 &RT0 25 0
|
||||
0x1800 0x0 0x0 0x1 &RT0 0x26 0x0
|
||||
0x1800 0x0 0x0 0x2 &RT0 0x27 0x0
|
||||
0x1800 0x0 0x0 0x3 &RT0 0x24 0x0
|
||||
0x1800 0x0 0x0 0x4 &RT0 0x25 0x0
|
||||
|
||||
2000 0 0 1 &RT0 27 0
|
||||
2000 0 0 2 &RT0 24 0
|
||||
2000 0 0 3 &RT0 25 0
|
||||
2000 0 0 4 &RT0 26 0
|
||||
0x2000 0x0 0x0 0x1 &RT0 0x27 0x0
|
||||
0x2000 0x0 0x0 0x2 &RT0 0x24 0x0
|
||||
0x2000 0x0 0x0 0x3 &RT0 0x25 0x0
|
||||
0x2000 0x0 0x0 0x4 &RT0 0x26 0x0
|
||||
>;
|
||||
|
||||
RT0: router@1180 {
|
||||
|
|
@ -183,7 +185,7 @@
|
|||
clock-frequency = <0>;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <17 2>;
|
||||
interrupts = <0x17 0x2>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -12,12 +12,14 @@
|
|||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,katmai";
|
||||
compatible = "amcc,katmai";
|
||||
dcr-parent = <&/cpus/cpu@0>;
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
|
|
@ -33,13 +35,13 @@
|
|||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,440SPe";
|
||||
reg = <0>;
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
timebase-frequency = <0>; /* Filled in by zImage */
|
||||
i-cache-line-size = <20>;
|
||||
d-cache-line-size = <20>;
|
||||
i-cache-size = <8000>;
|
||||
d-cache-size = <8000>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
|
|
@ -47,14 +49,14 @@
|
|||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0 0>; /* Filled in by zImage */
|
||||
reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller0 {
|
||||
compatible = "ibm,uic-440spe","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0c0 009>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
|
|
@ -64,11 +66,11 @@
|
|||
compatible = "ibm,uic-440spe","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0d0 009>;
|
||||
dcr-reg = <0x0d0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <1e 4 1f 4>; /* cascade */
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
|
|
@ -76,11 +78,11 @@
|
|||
compatible = "ibm,uic-440spe","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <2>;
|
||||
dcr-reg = <0e0 009>;
|
||||
dcr-reg = <0x0e0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <a 4 b 4>; /* cascade */
|
||||
interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
|
|
@ -88,22 +90,22 @@
|
|||
compatible = "ibm,uic-440spe","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <3>;
|
||||
dcr-reg = <0f0 009>;
|
||||
dcr-reg = <0x0f0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <10 4 11 4>; /* cascade */
|
||||
interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
SDR0: sdr {
|
||||
compatible = "ibm,sdr-440spe";
|
||||
dcr-reg = <00e 002>;
|
||||
dcr-reg = <0x00e 0x002>;
|
||||
};
|
||||
|
||||
CPR0: cpr {
|
||||
compatible = "ibm,cpr-440spe";
|
||||
dcr-reg = <00c 002>;
|
||||
dcr-reg = <0x00c 0x002>;
|
||||
};
|
||||
|
||||
plb {
|
||||
|
|
@ -115,108 +117,108 @@
|
|||
|
||||
SDRAM0: sdram {
|
||||
compatible = "ibm,sdram-440spe", "ibm,sdram-405gp";
|
||||
dcr-reg = <010 2>;
|
||||
dcr-reg = <0x010 0x002>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-440spe", "ibm,mcmal2";
|
||||
dcr-reg = <180 62>;
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <2>;
|
||||
num-rx-chans = <1>;
|
||||
interrupt-parent = <&MAL0>;
|
||||
interrupts = <0 1 2 3 4>;
|
||||
interrupts = <0x0 0x1 0x2 0x3 0x4>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*TXEOB*/ 0 &UIC1 6 4
|
||||
/*RXEOB*/ 1 &UIC1 7 4
|
||||
/*SERR*/ 2 &UIC1 1 4
|
||||
/*TXDE*/ 3 &UIC1 2 4
|
||||
/*RXDE*/ 4 &UIC1 3 4>;
|
||||
interrupt-map = </*TXEOB*/ 0x0 &UIC1 0x6 0x4
|
||||
/*RXEOB*/ 0x1 &UIC1 0x7 0x4
|
||||
/*SERR*/ 0x2 &UIC1 0x1 0x4
|
||||
/*TXDE*/ 0x3 &UIC1 0x2 0x4
|
||||
/*RXDE*/ 0x4 &UIC1 0x3 0x4>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <00000000 4 e0000000 20000000>;
|
||||
ranges = <0x00000000 0x00000004 0xe0000000 0x20000000>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc";
|
||||
dcr-reg = <012 2>;
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
interrupts = <5 1>;
|
||||
interrupts = <0x5 0x1>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
};
|
||||
|
||||
UART0: serial@10000200 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <10000200 8>;
|
||||
virtual-reg = <a0000200>;
|
||||
reg = <0x10000200 0x00000008>;
|
||||
virtual-reg = <0xa0000200>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
current-speed = <1c200>;
|
||||
current-speed = <115200>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0 4>;
|
||||
interrupts = <0x0 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@10000300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <10000300 8>;
|
||||
virtual-reg = <a0000300>;
|
||||
reg = <0x10000300 0x00000008>;
|
||||
virtual-reg = <0xa0000300>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <1 4>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
|
||||
UART2: serial@10000600 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <10000600 8>;
|
||||
virtual-reg = <a0000600>;
|
||||
reg = <0x10000600 0x00000008>;
|
||||
virtual-reg = <0xa0000600>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <5 4>;
|
||||
interrupts = <0x5 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@10000400 {
|
||||
compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
|
||||
reg = <10000400 14>;
|
||||
reg = <0x10000400 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <2 4>;
|
||||
interrupts = <0x2 0x4>;
|
||||
};
|
||||
|
||||
IIC1: i2c@10000500 {
|
||||
compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
|
||||
reg = <10000500 14>;
|
||||
reg = <0x10000500 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <3 4>;
|
||||
interrupts = <0x3 0x4>;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@10000800 {
|
||||
linux,network-index = <0>;
|
||||
linux,network-index = <0x0>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-440spe", "ibm,emac4";
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <1c 4 1d 4>;
|
||||
reg = <10000800 70>;
|
||||
interrupts = <0x1c 0x4 0x1d 0x4>;
|
||||
reg = <0x10000800 0x00000074>;
|
||||
local-mac-address = [000000000000];
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <2328>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "gmii";
|
||||
phy-map = <00000000>;
|
||||
phy-map = <0x00000000>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
|
|
@ -231,23 +233,23 @@
|
|||
primary;
|
||||
large-inbound-windows;
|
||||
enable-msi-hole;
|
||||
reg = <c 0ec00000 8 /* Config space access */
|
||||
0 0 0 /* no IACK cycles */
|
||||
c 0ed00000 4 /* Special cycles */
|
||||
c 0ec80000 100 /* Internal registers */
|
||||
c 0ec80100 fc>; /* Internal messaging registers */
|
||||
reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
|
||||
0x00000000 0x00000000 0x00000000 /* no IACK cycles */
|
||||
0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
|
||||
0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
|
||||
0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <02000000 0 80000000 0000000d 80000000 0 80000000
|
||||
01000000 0 00000000 0000000c 08000000 0 00010000>;
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 0 80000000>;
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 0 to 0xf */
|
||||
bus-range = <0 f>;
|
||||
bus-range = <0x0 0xf>;
|
||||
|
||||
/*
|
||||
* On Katmai, the following PCI-X interrupts signals
|
||||
|
|
@ -258,13 +260,13 @@
|
|||
* INTC: J2: 1-2
|
||||
* INTD: J1: 1-2
|
||||
*/
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 1 */
|
||||
0800 0 0 1 &UIC1 14 8
|
||||
0800 0 0 2 &UIC1 13 8
|
||||
0800 0 0 3 &UIC1 12 8
|
||||
0800 0 0 4 &UIC1 11 8
|
||||
0x800 0x0 0x0 0x1 &UIC1 0x14 0x8
|
||||
0x800 0x0 0x0 0x2 &UIC1 0x13 0x8
|
||||
0x800 0x0 0x0 0x3 &UIC1 0x12 0x8
|
||||
0x800 0x0 0x0 0x4 &UIC1 0x11 0x8
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
@ -275,23 +277,23 @@
|
|||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0>; /* port number */
|
||||
reg = <d 00000000 20000000 /* Config space access */
|
||||
c 10000000 00001000>; /* Registers */
|
||||
dcr-reg = <100 020>;
|
||||
sdr-base = <300>;
|
||||
port = <0x0>; /* port number */
|
||||
reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
|
||||
0x0000000c 0x10000000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x100 0x020>;
|
||||
sdr-base = <0x300>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <02000000 0 80000000 0000000e 00000000 0 80000000
|
||||
01000000 0 00000000 0000000f 80000000 0 00010000>;
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 0 80000000>;
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 10 to 0x1f */
|
||||
bus-range = <10 1f>;
|
||||
bus-range = <0x10 0x1f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
|
|
@ -301,12 +303,12 @@
|
|||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0000 0 0 7>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0000 0 0 1 &UIC3 0 4 /* swizzled int A */
|
||||
0000 0 0 2 &UIC3 1 4 /* swizzled int B */
|
||||
0000 0 0 3 &UIC3 2 4 /* swizzled int C */
|
||||
0000 0 0 4 &UIC3 3 4 /* swizzled int D */>;
|
||||
0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
PCIE1: pciex@d20000000 {
|
||||
|
|
@ -316,23 +318,23 @@
|
|||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <1>; /* port number */
|
||||
reg = <d 20000000 20000000 /* Config space access */
|
||||
c 10001000 00001000>; /* Registers */
|
||||
dcr-reg = <120 020>;
|
||||
sdr-base = <340>;
|
||||
port = <0x1>; /* port number */
|
||||
reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
|
||||
0x0000000c 0x10001000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x120 0x020>;
|
||||
sdr-base = <0x340>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <02000000 0 80000000 0000000e 80000000 0 80000000
|
||||
01000000 0 00000000 0000000f 80010000 0 00010000>;
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 0 80000000>;
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 10 to 0x1f */
|
||||
bus-range = <20 2f>;
|
||||
bus-range = <0x20 0x2f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
|
|
@ -342,12 +344,12 @@
|
|||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0000 0 0 7>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0000 0 0 1 &UIC3 4 4 /* swizzled int A */
|
||||
0000 0 0 2 &UIC3 5 4 /* swizzled int B */
|
||||
0000 0 0 3 &UIC3 6 4 /* swizzled int C */
|
||||
0000 0 0 4 &UIC3 7 4 /* swizzled int D */>;
|
||||
0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
PCIE2: pciex@d40000000 {
|
||||
|
|
@ -357,23 +359,23 @@
|
|||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <2>; /* port number */
|
||||
reg = <d 40000000 20000000 /* Config space access */
|
||||
c 10002000 00001000>; /* Registers */
|
||||
dcr-reg = <140 020>;
|
||||
sdr-base = <370>;
|
||||
port = <0x2>; /* port number */
|
||||
reg = <0x0000000d 0x40000000 0x20000000 /* Config space access */
|
||||
0x0000000c 0x10002000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x140 0x020>;
|
||||
sdr-base = <0x370>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <02000000 0 80000000 0000000f 00000000 0 80000000
|
||||
01000000 0 00000000 0000000f 80020000 0 00010000>;
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000f 0x00000000 0x00000000 0x80000000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000f 0x80020000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 0 80000000>;
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 10 to 0x1f */
|
||||
bus-range = <30 3f>;
|
||||
bus-range = <0x30 0x3f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
|
|
@ -383,12 +385,12 @@
|
|||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0000 0 0 7>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0000 0 0 1 &UIC3 8 4 /* swizzled int A */
|
||||
0000 0 0 2 &UIC3 9 4 /* swizzled int B */
|
||||
0000 0 0 3 &UIC3 a 4 /* swizzled int C */
|
||||
0000 0 0 4 &UIC3 b 4 /* swizzled int D */>;
|
||||
0x0 0x0 0x0 0x1 &UIC3 0x8 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC3 0x9 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -8,12 +8,14 @@
|
|||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,kilauea";
|
||||
compatible = "amcc,kilauea";
|
||||
dcr-parent = <&/cpus/cpu@0>;
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
|
|
@ -29,13 +31,13 @@
|
|||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,405EX";
|
||||
reg = <0>;
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
timebase-frequency = <0>; /* Filled in by U-Boot */
|
||||
i-cache-line-size = <20>;
|
||||
d-cache-line-size = <20>;
|
||||
i-cache-size = <4000>; /* 16 kB */
|
||||
d-cache-size = <4000>; /* 16 kB */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <16384>; /* 16 kB */
|
||||
d-cache-size = <16384>; /* 16 kB */
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
|
|
@ -43,14 +45,14 @@
|
|||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0>; /* Filled in by U-Boot */
|
||||
reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller {
|
||||
compatible = "ibm,uic-405ex", "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0c0 009>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
|
|
@ -60,11 +62,11 @@
|
|||
compatible = "ibm,uic-405ex","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0d0 009>;
|
||||
dcr-reg = <0x0d0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <1e 4 1f 4>; /* cascade */
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
|
|
@ -72,11 +74,11 @@
|
|||
compatible = "ibm,uic-405ex","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <2>;
|
||||
dcr-reg = <0e0 009>;
|
||||
dcr-reg = <0x0e0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <1c 4 1d 4>; /* cascade */
|
||||
interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
|
|
@ -89,72 +91,72 @@
|
|||
|
||||
SDRAM0: memory-controller {
|
||||
compatible = "ibm,sdram-405ex";
|
||||
dcr-reg = <010 2>;
|
||||
dcr-reg = <0x010 0x002>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
|
||||
dcr-reg = <180 62>;
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <2>;
|
||||
num-rx-chans = <2>;
|
||||
interrupt-parent = <&MAL0>;
|
||||
interrupts = <0 1 2 3 4>;
|
||||
interrupts = <0x0 0x1 0x2 0x3 0x4>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
|
||||
/*RXEOB*/ 1 &UIC0 b 4
|
||||
/*SERR*/ 2 &UIC1 0 4
|
||||
/*TXDE*/ 3 &UIC1 1 4
|
||||
/*RXDE*/ 4 &UIC1 2 4>;
|
||||
interrupt-map-mask = <ffffffff>;
|
||||
interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
|
||||
/*RXEOB*/ 0x1 &UIC0 0xb 0x4
|
||||
/*SERR*/ 0x2 &UIC1 0x0 0x4
|
||||
/*TXDE*/ 0x3 &UIC1 0x1 0x4
|
||||
/*RXDE*/ 0x4 &UIC1 0x2 0x4>;
|
||||
interrupt-map-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-405ex", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <80000000 80000000 10000000
|
||||
ef600000 ef600000 a00000
|
||||
f0000000 f0000000 10000000>;
|
||||
dcr-reg = <0a0 5>;
|
||||
ranges = <0x80000000 0x80000000 0x10000000
|
||||
0xef600000 0xef600000 0x00a00000
|
||||
0xf0000000 0xf0000000 0x10000000>;
|
||||
dcr-reg = <0x0a0 0x005>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-405ex", "ibm,ebc";
|
||||
dcr-reg = <012 2>;
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
/* ranges property is supplied by U-Boot */
|
||||
interrupts = <5 1>;
|
||||
interrupts = <0x5 0x1>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
|
||||
nor_flash@0,0 {
|
||||
compatible = "amd,s29gl512n", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0 000000 4000000>;
|
||||
reg = <0x00000000 0x00000000 0x04000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0 200000>;
|
||||
reg = <0x00000000 0x00200000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "root";
|
||||
reg = <200000 200000>;
|
||||
reg = <0x00200000 0x00200000>;
|
||||
};
|
||||
partition@400000 {
|
||||
label = "user";
|
||||
reg = <400000 3b60000>;
|
||||
reg = <0x00400000 0x03b60000>;
|
||||
};
|
||||
partition@3f60000 {
|
||||
label = "env";
|
||||
reg = <3f60000 40000>;
|
||||
reg = <0x03f60000 0x00040000>;
|
||||
};
|
||||
partition@3fa0000 {
|
||||
label = "u-boot";
|
||||
reg = <3fa0000 60000>;
|
||||
reg = <0x03fa0000 0x00060000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -162,68 +164,68 @@
|
|||
UART0: serial@ef600200 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600200 8>;
|
||||
virtual-reg = <ef600200>;
|
||||
reg = <0xef600200 0x00000008>;
|
||||
virtual-reg = <0xef600200>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <1a 4>;
|
||||
interrupts = <0x1a 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600300 8>;
|
||||
virtual-reg = <ef600300>;
|
||||
reg = <0xef600300 0x00000008>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <1 4>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@ef600400 {
|
||||
compatible = "ibm,iic-405ex", "ibm,iic";
|
||||
reg = <ef600400 14>;
|
||||
reg = <0xef600400 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <2 4>;
|
||||
interrupts = <0x2 0x4>;
|
||||
};
|
||||
|
||||
IIC1: i2c@ef600500 {
|
||||
compatible = "ibm,iic-405ex", "ibm,iic";
|
||||
reg = <ef600500 14>;
|
||||
reg = <0xef600500 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <7 4>;
|
||||
interrupts = <0x7 0x4>;
|
||||
};
|
||||
|
||||
|
||||
RGMII0: emac-rgmii@ef600b00 {
|
||||
compatible = "ibm,rgmii-405ex", "ibm,rgmii";
|
||||
reg = <ef600b00 104>;
|
||||
reg = <0xef600b00 0x00000104>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600900 {
|
||||
linux,network-index = <0>;
|
||||
linux,network-index = <0x0>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-405ex", "ibm,emac4";
|
||||
compatible = "ibm,emac-405ex", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC0>;
|
||||
interrupts = <0 1>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0 &UIC0 18 4
|
||||
/*Wake*/ 1 &UIC1 1d 4>;
|
||||
reg = <ef600900 70>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
|
||||
/*Wake*/ 0x1 &UIC1 0x1d 0x4>;
|
||||
reg = <0xef600900 0x000000c4>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <2328>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <00000000>;
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <0>;
|
||||
has-inverted-stacr-oc;
|
||||
|
|
@ -231,27 +233,27 @@
|
|||
};
|
||||
|
||||
EMAC1: ethernet@ef600a00 {
|
||||
linux,network-index = <1>;
|
||||
linux,network-index = <0x1>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-405ex", "ibm,emac4";
|
||||
compatible = "ibm,emac-405ex", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC1>;
|
||||
interrupts = <0 1>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0 &UIC0 19 4
|
||||
/*Wake*/ 1 &UIC1 1f 4>;
|
||||
reg = <ef600a00 70>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
|
||||
/*Wake*/ 0x1 &UIC1 0x1f 0x4>;
|
||||
reg = <0xef600a00 0x000000c4>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <1>;
|
||||
mal-rx-channel = <1>;
|
||||
cell-index = <1>;
|
||||
max-frame-size = <2328>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <00000000>;
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <1>;
|
||||
has-inverted-stacr-oc;
|
||||
|
|
@ -266,23 +268,23 @@
|
|||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0>; /* port number */
|
||||
reg = <a0000000 20000000 /* Config space access */
|
||||
ef000000 00001000>; /* Registers */
|
||||
dcr-reg = <040 020>;
|
||||
sdr-base = <400>;
|
||||
port = <0x0>; /* port number */
|
||||
reg = <0xa0000000 0x20000000 /* Config space access */
|
||||
0xef000000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x040 0x020>;
|
||||
sdr-base = <0x400>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <02000000 0 80000000 90000000 0 08000000
|
||||
01000000 0 00000000 e0000000 0 00010000>;
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000
|
||||
0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 80000000>;
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 0x00 to 0x3f */
|
||||
bus-range = <00 3f>;
|
||||
bus-range = <0x0 0x3f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
|
|
@ -292,12 +294,12 @@
|
|||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0000 0 0 7>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0000 0 0 1 &UIC2 0 4 /* swizzled int A */
|
||||
0000 0 0 2 &UIC2 1 4 /* swizzled int B */
|
||||
0000 0 0 3 &UIC2 2 4 /* swizzled int C */
|
||||
0000 0 0 4 &UIC2 3 4 /* swizzled int D */>;
|
||||
0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
PCIE1: pciex@0c0000000 {
|
||||
|
|
@ -307,23 +309,23 @@
|
|||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <1>; /* port number */
|
||||
reg = <c0000000 20000000 /* Config space access */
|
||||
ef001000 00001000>; /* Registers */
|
||||
dcr-reg = <060 020>;
|
||||
sdr-base = <440>;
|
||||
port = <0x1>; /* port number */
|
||||
reg = <0xc0000000 0x20000000 /* Config space access */
|
||||
0xef001000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x060 0x020>;
|
||||
sdr-base = <0x440>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <02000000 0 80000000 98000000 0 08000000
|
||||
01000000 0 00000000 e0010000 0 00010000>;
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000
|
||||
0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 80000000>;
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 0x40 to 0x7f */
|
||||
bus-range = <40 7f>;
|
||||
bus-range = <0x40 0x7f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
|
|
@ -333,12 +335,12 @@
|
|||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0000 0 0 7>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0000 0 0 1 &UIC2 b 4 /* swizzled int A */
|
||||
0000 0 0 2 &UIC2 c 4 /* swizzled int B */
|
||||
0000 0 0 3 &UIC2 d 4 /* swizzled int C */
|
||||
0000 0 0 4 &UIC2 e 4 /* swizzled int D */>;
|
||||
0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -40,6 +40,7 @@
|
|||
timebase-frequency = <0>; /* From U-boot */
|
||||
bus-frequency = <0>; /* From U-boot */
|
||||
clock-frequency = <0>; /* From U-boot */
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -58,16 +59,16 @@
|
|||
memory-controller@2000 {
|
||||
compatible = "fsl,8540-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <0x12 0x2>;
|
||||
};
|
||||
|
||||
l2-cache-controller@20000 {
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,8540-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <0x20>; /* 32 bytes */
|
||||
cache-size = <0x40000>; /* L2, 256K */
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <0x10 0x2>;
|
||||
};
|
||||
|
||||
|
|
@ -78,10 +79,51 @@
|
|||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <0x2b 0x2>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8560-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8560-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8560-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8560-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24520 { /* For TSECs */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -89,13 +131,13 @@
|
|||
reg = <0x24520 0x20>;
|
||||
|
||||
PHY1: ethernet-phy@1 {
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupt-parent = <&mpic>;
|
||||
reg = <0x1>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
|
||||
PHY2: ethernet-phy@2 {
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupt-parent = <&mpic>;
|
||||
reg = <0x2>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
|
|
@ -109,7 +151,7 @@
|
|||
/* Mac address filled in by bootwrapper */
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&PHY1>;
|
||||
};
|
||||
|
||||
|
|
@ -121,11 +163,11 @@
|
|||
/* Mac address filled in by bootwrapper */
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&PHY2>;
|
||||
};
|
||||
|
||||
MPIC: pic@40000 {
|
||||
mpic: pic@40000 {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
|
|
@ -164,7 +206,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
interrupts = <0x2e 0x2>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupt-parent = <&mpic>;
|
||||
reg = <0x90c00 0x80>;
|
||||
compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
|
||||
};
|
||||
|
|
@ -202,7 +244,7 @@
|
|||
fsl,mdc-pin = <25>;
|
||||
|
||||
PHY0: ethernet-phy@0 {
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupt-parent = <&mpic>;
|
||||
reg = <0x0>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -8,12 +8,14 @@
|
|||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,makalu";
|
||||
compatible = "amcc,makalu";
|
||||
dcr-parent = <&/cpus/cpu@0>;
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
|
|
@ -29,13 +31,13 @@
|
|||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,405EX";
|
||||
reg = <0>;
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
timebase-frequency = <0>; /* Filled in by U-Boot */
|
||||
i-cache-line-size = <20>;
|
||||
d-cache-line-size = <20>;
|
||||
i-cache-size = <4000>; /* 16 kB */
|
||||
d-cache-size = <4000>; /* 16 kB */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <16384>; /* 16 kB */
|
||||
d-cache-size = <16384>; /* 16 kB */
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
|
|
@ -43,14 +45,14 @@
|
|||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0>; /* Filled in by U-Boot */
|
||||
reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller {
|
||||
compatible = "ibm,uic-405ex", "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0c0 009>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
|
|
@ -60,11 +62,11 @@
|
|||
compatible = "ibm,uic-405ex","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0d0 009>;
|
||||
dcr-reg = <0x0d0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <1e 4 1f 4>; /* cascade */
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
|
|
@ -72,11 +74,11 @@
|
|||
compatible = "ibm,uic-405ex","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <2>;
|
||||
dcr-reg = <0e0 009>;
|
||||
dcr-reg = <0x0e0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <1c 4 1d 4>; /* cascade */
|
||||
interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
|
|
@ -89,72 +91,72 @@
|
|||
|
||||
SDRAM0: memory-controller {
|
||||
compatible = "ibm,sdram-405ex";
|
||||
dcr-reg = <010 2>;
|
||||
dcr-reg = <0x010 0x002>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
|
||||
dcr-reg = <180 62>;
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <2>;
|
||||
num-rx-chans = <2>;
|
||||
interrupt-parent = <&MAL0>;
|
||||
interrupts = <0 1 2 3 4>;
|
||||
interrupts = <0x0 0x1 0x2 0x3 0x4>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
|
||||
/*RXEOB*/ 1 &UIC0 b 4
|
||||
/*SERR*/ 2 &UIC1 0 4
|
||||
/*TXDE*/ 3 &UIC1 1 4
|
||||
/*RXDE*/ 4 &UIC1 2 4>;
|
||||
interrupt-map-mask = <ffffffff>;
|
||||
interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
|
||||
/*RXEOB*/ 0x1 &UIC0 0xb 0x4
|
||||
/*SERR*/ 0x2 &UIC1 0x0 0x4
|
||||
/*TXDE*/ 0x3 &UIC1 0x1 0x4
|
||||
/*RXDE*/ 0x4 &UIC1 0x2 0x4>;
|
||||
interrupt-map-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-405ex", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <80000000 80000000 10000000
|
||||
ef600000 ef600000 a00000
|
||||
f0000000 f0000000 10000000>;
|
||||
dcr-reg = <0a0 5>;
|
||||
ranges = <0x80000000 0x80000000 0x10000000
|
||||
0xef600000 0xef600000 0x00a00000
|
||||
0xf0000000 0xf0000000 0x10000000>;
|
||||
dcr-reg = <0x0a0 0x005>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-405ex", "ibm,ebc";
|
||||
dcr-reg = <012 2>;
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
/* ranges property is supplied by U-Boot */
|
||||
interrupts = <5 1>;
|
||||
interrupts = <0x5 0x1>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
|
||||
nor_flash@0,0 {
|
||||
compatible = "amd,s29gl512n", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0 000000 4000000>;
|
||||
reg = <0x00000000 0x00000000 0x04000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0 200000>;
|
||||
reg = <0x00000000 0x00200000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "root";
|
||||
reg = <200000 200000>;
|
||||
reg = <0x00200000 0x00200000>;
|
||||
};
|
||||
partition@400000 {
|
||||
label = "user";
|
||||
reg = <400000 3b60000>;
|
||||
reg = <0x00400000 0x03b60000>;
|
||||
};
|
||||
partition@3f60000 {
|
||||
label = "env";
|
||||
reg = <3f60000 40000>;
|
||||
reg = <0x03f60000 0x00040000>;
|
||||
};
|
||||
partition@3fa0000 {
|
||||
label = "u-boot";
|
||||
reg = <3fa0000 60000>;
|
||||
reg = <0x03fa0000 0x00060000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -162,68 +164,68 @@
|
|||
UART0: serial@ef600200 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600200 8>;
|
||||
virtual-reg = <ef600200>;
|
||||
reg = <0xef600200 0x00000008>;
|
||||
virtual-reg = <0xef600200>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <1a 4>;
|
||||
interrupts = <0x1a 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600300 8>;
|
||||
virtual-reg = <ef600300>;
|
||||
reg = <0xef600300 0x00000008>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <1 4>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@ef600400 {
|
||||
compatible = "ibm,iic-405ex", "ibm,iic";
|
||||
reg = <ef600400 14>;
|
||||
reg = <0xef600400 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <2 4>;
|
||||
interrupts = <0x2 0x4>;
|
||||
};
|
||||
|
||||
IIC1: i2c@ef600500 {
|
||||
compatible = "ibm,iic-405ex", "ibm,iic";
|
||||
reg = <ef600500 14>;
|
||||
reg = <0xef600500 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <7 4>;
|
||||
interrupts = <0x7 0x4>;
|
||||
};
|
||||
|
||||
|
||||
RGMII0: emac-rgmii@ef600b00 {
|
||||
compatible = "ibm,rgmii-405ex", "ibm,rgmii";
|
||||
reg = <ef600b00 104>;
|
||||
reg = <0xef600b00 0x00000104>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600900 {
|
||||
linux,network-index = <0>;
|
||||
linux,network-index = <0x0>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-405ex", "ibm,emac4";
|
||||
compatible = "ibm,emac-405ex", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC0>;
|
||||
interrupts = <0 1>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0 &UIC0 18 4
|
||||
/*Wake*/ 1 &UIC1 1d 4>;
|
||||
reg = <ef600900 70>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
|
||||
/*Wake*/ 0x1 &UIC1 0x1d 0x4>;
|
||||
reg = <0xef600900 0x000000c4>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <2328>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0000003f>; /* Start at 6 */
|
||||
phy-map = <0x0000003f>; /* Start at 6 */
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <0>;
|
||||
has-inverted-stacr-oc;
|
||||
|
|
@ -231,27 +233,27 @@
|
|||
};
|
||||
|
||||
EMAC1: ethernet@ef600a00 {
|
||||
linux,network-index = <1>;
|
||||
linux,network-index = <0x1>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-405ex", "ibm,emac4";
|
||||
compatible = "ibm,emac-405ex", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC1>;
|
||||
interrupts = <0 1>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0 &UIC0 19 4
|
||||
/*Wake*/ 1 &UIC1 1f 4>;
|
||||
reg = <ef600a00 70>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
|
||||
/*Wake*/ 0x1 &UIC1 0x1f 0x4>;
|
||||
reg = <0xef600a00 0x000000c4>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <1>;
|
||||
mal-rx-channel = <1>;
|
||||
cell-index = <1>;
|
||||
max-frame-size = <2328>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <00000000>;
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <1>;
|
||||
has-inverted-stacr-oc;
|
||||
|
|
@ -266,23 +268,23 @@
|
|||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0>; /* port number */
|
||||
reg = <a0000000 20000000 /* Config space access */
|
||||
ef000000 00001000>; /* Registers */
|
||||
dcr-reg = <040 020>;
|
||||
sdr-base = <400>;
|
||||
port = <0x0>; /* port number */
|
||||
reg = <0xa0000000 0x20000000 /* Config space access */
|
||||
0xef000000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x040 0x020>;
|
||||
sdr-base = <0x400>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <02000000 0 80000000 90000000 0 08000000
|
||||
01000000 0 00000000 e0000000 0 00010000>;
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000
|
||||
0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 80000000>;
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 0x00 to 0x3f */
|
||||
bus-range = <00 3f>;
|
||||
bus-range = <0x0 0x3f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
|
|
@ -292,12 +294,12 @@
|
|||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0000 0 0 7>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0000 0 0 1 &UIC2 0 4 /* swizzled int A */
|
||||
0000 0 0 2 &UIC2 1 4 /* swizzled int B */
|
||||
0000 0 0 3 &UIC2 2 4 /* swizzled int C */
|
||||
0000 0 0 4 &UIC2 3 4 /* swizzled int D */>;
|
||||
0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
PCIE1: pciex@0c0000000 {
|
||||
|
|
@ -307,23 +309,23 @@
|
|||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <1>; /* port number */
|
||||
reg = <c0000000 20000000 /* Config space access */
|
||||
ef001000 00001000>; /* Registers */
|
||||
dcr-reg = <060 020>;
|
||||
sdr-base = <440>;
|
||||
port = <0x1>; /* port number */
|
||||
reg = <0xc0000000 0x20000000 /* Config space access */
|
||||
0xef001000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x060 0x020>;
|
||||
sdr-base = <0x440>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <02000000 0 80000000 98000000 0 08000000
|
||||
01000000 0 00000000 e0010000 0 00010000>;
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000
|
||||
0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 80000000>;
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 0x40 to 0x7f */
|
||||
bus-range = <40 7f>;
|
||||
bus-range = <0x40 0x7f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
|
|
@ -333,12 +335,12 @@
|
|||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0000 0 0 7>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0000 0 0 1 &UIC2 b 4 /* swizzled int A */
|
||||
0000 0 0 2 &UIC2 c 4 /* swizzled int B */
|
||||
0000 0 0 3 &UIC2 d 4 /* swizzled int C */
|
||||
0000 0 0 4 &UIC2 e 4 /* swizzled int D */>;
|
||||
0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* MPC5121E MDS Device Tree Source
|
||||
* MPC5121E ADS Device Tree Source
|
||||
*
|
||||
* Copyright 2007 Freescale Semiconductor Inc.
|
||||
* Copyright 2007,2008 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
|
|
@ -17,6 +17,10 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
pci = &pci;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -39,8 +43,41 @@
|
|||
reg = <0x00000000 0x10000000>; // 256MB at 0
|
||||
};
|
||||
|
||||
mbx@20000000 {
|
||||
compatible = "fsl,mpc5121-mbx";
|
||||
reg = <0x20000000 0x4000>;
|
||||
interrupts = <66 0x8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
};
|
||||
|
||||
sram@30000000 {
|
||||
compatible = "fsl,mpc5121-sram";
|
||||
reg = <0x30000000 0x20000>; // 128K at 0x30000000
|
||||
};
|
||||
|
||||
nfc@40000000 {
|
||||
compatible = "fsl,mpc5121-nfc";
|
||||
reg = <0x40000000 0x100000>; // 1M at 0x40000000
|
||||
interrupts = <6 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
bank-width = <1>;
|
||||
// ADS has two Hynix 512MB Nand flash chips in a single
|
||||
// stacked package .
|
||||
chips = <2>;
|
||||
nand0@0 {
|
||||
label = "nand0";
|
||||
reg = <0x00000000 0x02000000>; // first 32 MB of chip 0
|
||||
};
|
||||
nand1@20000000 {
|
||||
label = "nand1";
|
||||
reg = <0x20000000 0x02000000>; // first 32 MB of chip 1
|
||||
};
|
||||
};
|
||||
|
||||
localbus@80000020 {
|
||||
compatible = "fsl,mpc5121ads-localbus";
|
||||
compatible = "fsl,mpc5121-localbus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x80000020 0x40>;
|
||||
|
|
@ -51,14 +88,51 @@
|
|||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x0 0x4000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
bank-width = <4>;
|
||||
device-width = <1>;
|
||||
device-width = <2>;
|
||||
protected@0 {
|
||||
label = "protected";
|
||||
reg = <0x00000000 0x00040000>; // first sector is protected
|
||||
read-only;
|
||||
};
|
||||
filesystem@40000 {
|
||||
label = "filesystem";
|
||||
reg = <0x00040000 0x03c00000>; // 60M for filesystem
|
||||
};
|
||||
kernel@3c40000 {
|
||||
label = "kernel";
|
||||
reg = <0x03c40000 0x00280000>; // 2.5M for kernel
|
||||
};
|
||||
device-tree@3ec0000 {
|
||||
label = "device-tree";
|
||||
reg = <0x03ec0000 0x00040000>; // one sector for device tree
|
||||
};
|
||||
u-boot@3f00000 {
|
||||
label = "u-boot";
|
||||
reg = <0x03f00000 0x00100000>; // 1M for u-boot
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
board-control@2,0 {
|
||||
compatible = "fsl,mpc5121ads-cpld";
|
||||
reg = <0x2 0x0 0x8000>;
|
||||
};
|
||||
|
||||
cpld_pic: pic@2,a {
|
||||
compatible = "fsl,mpc5121ads-cpld-pic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x2 0xa 0x5>;
|
||||
interrupt-parent = < &ipic >;
|
||||
// irq routing
|
||||
// all irqs but touch screen are routed to irq0 (ipic 48)
|
||||
// touch screen is statically routed to irq1 (ipic 17)
|
||||
// so don't use it here
|
||||
interrupts = <48 0x8>;
|
||||
};
|
||||
};
|
||||
|
||||
soc@80000000 {
|
||||
|
|
@ -85,38 +159,252 @@
|
|||
reg = <0xc00 0x100>;
|
||||
};
|
||||
|
||||
// 512x PSCs are not 52xx PSCs compatible
|
||||
rtc@a00 { // Real time clock
|
||||
compatible = "fsl,mpc5121-rtc";
|
||||
reg = <0xa00 0x100>;
|
||||
interrupts = <79 0x8 80 0x8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
};
|
||||
|
||||
clock@f00 { // Clock control
|
||||
compatible = "fsl,mpc5121-clock";
|
||||
reg = <0xf00 0x100>;
|
||||
};
|
||||
|
||||
pmc@1000{ //Power Management Controller
|
||||
compatible = "fsl,mpc5121-pmc";
|
||||
reg = <0x1000 0x100>;
|
||||
interrupts = <83 0x2>;
|
||||
interrupt-parent = < &ipic >;
|
||||
};
|
||||
|
||||
gpio@1100 {
|
||||
compatible = "fsl,mpc5121-gpio";
|
||||
reg = <0x1100 0x100>;
|
||||
interrupts = <78 0x8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
};
|
||||
|
||||
mscan@1300 {
|
||||
compatible = "fsl,mpc5121-mscan";
|
||||
cell-index = <0>;
|
||||
interrupts = <12 0x8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
reg = <0x1300 0x80>;
|
||||
};
|
||||
|
||||
mscan@1380 {
|
||||
compatible = "fsl,mpc5121-mscan";
|
||||
cell-index = <1>;
|
||||
interrupts = <13 0x8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
reg = <0x1380 0x80>;
|
||||
};
|
||||
|
||||
i2c@1700 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
|
||||
cell-index = <0>;
|
||||
reg = <0x1700 0x20>;
|
||||
interrupts = <9 0x8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
fsl5200-clocking;
|
||||
};
|
||||
|
||||
i2c@1720 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
|
||||
cell-index = <1>;
|
||||
reg = <0x1720 0x20>;
|
||||
interrupts = <10 0x8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
fsl5200-clocking;
|
||||
};
|
||||
|
||||
i2c@1740 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
|
||||
cell-index = <2>;
|
||||
reg = <0x1740 0x20>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
fsl5200-clocking;
|
||||
};
|
||||
|
||||
i2ccontrol@1760 {
|
||||
compatible = "fsl,mpc5121-i2c-ctrl";
|
||||
reg = <0x1760 0x8>;
|
||||
};
|
||||
|
||||
axe@2000 {
|
||||
compatible = "fsl,mpc5121-axe";
|
||||
reg = <0x2000 0x100>;
|
||||
interrupts = <42 0x8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
};
|
||||
|
||||
display@2100 {
|
||||
compatible = "fsl,mpc5121-diu", "fsl-diu";
|
||||
reg = <0x2100 0x100>;
|
||||
interrupts = <64 0x8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
};
|
||||
|
||||
mdio@2800 {
|
||||
compatible = "fsl,mpc5121-fec-mdio";
|
||||
reg = <0x2800 0x800>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
phy: ethernet-phy@0 {
|
||||
reg = <1>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@2800 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc5121-fec";
|
||||
reg = <0x2800 0x800>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <4 0x8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
phy-handle = < &phy >;
|
||||
fsl,align-tx-packets = <4>;
|
||||
};
|
||||
|
||||
// 5121e has two dr usb modules
|
||||
// mpc5121_ads only uses USB0
|
||||
|
||||
// USB1 using external ULPI PHY
|
||||
//usb@3000 {
|
||||
// compatible = "fsl,mpc5121-usb2-dr", "fsl-usb2-dr";
|
||||
// reg = <0x3000 0x1000>;
|
||||
// #address-cells = <1>;
|
||||
// #size-cells = <0>;
|
||||
// interrupt-parent = < &ipic >;
|
||||
// interrupts = <43 0x8>;
|
||||
// dr_mode = "otg";
|
||||
// phy_type = "ulpi";
|
||||
// port1;
|
||||
//};
|
||||
|
||||
// USB0 using internal UTMI PHY
|
||||
usb@4000 {
|
||||
compatible = "fsl,mpc5121-usb2-dr", "fsl-usb2-dr";
|
||||
reg = <0x4000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <44 0x8>;
|
||||
dr_mode = "otg";
|
||||
phy_type = "utmi_wide";
|
||||
port0;
|
||||
};
|
||||
|
||||
// IO control
|
||||
ioctl@a000 {
|
||||
compatible = "fsl,mpc5121-ioctl";
|
||||
reg = <0xA000 0x1000>;
|
||||
};
|
||||
|
||||
pata@10200 {
|
||||
compatible = "fsl,mpc5121-pata";
|
||||
reg = <0x10200 0x100>;
|
||||
interrupts = <5 0x8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
};
|
||||
|
||||
// 512x PSCs are not 52xx PSC compatible
|
||||
// PSC3 serial port A aka ttyPSC0
|
||||
serial@11300 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc5121-psc-uart";
|
||||
compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
|
||||
// Logical port assignment needed until driver
|
||||
// learns to use aliases
|
||||
port-number = <0>;
|
||||
cell-index = <3>;
|
||||
reg = <0x11300 0x100>;
|
||||
interrupts = <0x28 0x8>; // actually the fifo irq
|
||||
interrupts = <40 0x8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
rx-fifo-size = <16>;
|
||||
tx-fifo-size = <16>;
|
||||
};
|
||||
|
||||
// PSC4 serial port B aka ttyPSC1
|
||||
serial@11400 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc5121-psc-uart";
|
||||
compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
|
||||
// Logical port assignment needed until driver
|
||||
// learns to use aliases
|
||||
port-number = <1>;
|
||||
cell-index = <4>;
|
||||
reg = <0x11400 0x100>;
|
||||
interrupts = <0x28 0x8>; // actually the fifo irq
|
||||
interrupts = <40 0x8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
rx-fifo-size = <16>;
|
||||
tx-fifo-size = <16>;
|
||||
};
|
||||
|
||||
// PSC5 in ac97 mode
|
||||
ac97@11500 {
|
||||
compatible = "fsl,mpc5121-psc-ac97", "fsl,mpc5121-psc";
|
||||
cell-index = <5>;
|
||||
reg = <0x11500 0x100>;
|
||||
interrupts = <40 0x8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
fsl,mode = "ac97-slave";
|
||||
rx-fifo-size = <384>;
|
||||
tx-fifo-size = <384>;
|
||||
};
|
||||
|
||||
pscfifo@11f00 {
|
||||
compatible = "fsl,mpc5121-psc-fifo";
|
||||
reg = <0x11f00 0x100>;
|
||||
interrupts = <40 0x8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
};
|
||||
|
||||
pscsfifo@11f00 {
|
||||
compatible = "fsl,mpc5121-psc-fifo";
|
||||
reg = <0x11f00 0x100>;
|
||||
interrupts = <0x28 0x8>;
|
||||
dma@14000 {
|
||||
compatible = "fsl,mpc5121-dma2";
|
||||
reg = <0x14000 0x1800>;
|
||||
interrupts = <65 0x8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
pci: pci@80008500 {
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
// IDSEL 0x15 - Slot 1 PCI
|
||||
0xa800 0x0 0x0 0x1 &cpld_pic 0x0 0x8
|
||||
0xa800 0x0 0x0 0x2 &cpld_pic 0x1 0x8
|
||||
0xa800 0x0 0x0 0x3 &cpld_pic 0x2 0x8
|
||||
0xa800 0x0 0x0 0x4 &cpld_pic 0x3 0x8
|
||||
|
||||
// IDSEL 0x16 - Slot 2 MiniPCI
|
||||
0xb000 0x0 0x0 0x1 &cpld_pic 0x4 0x8
|
||||
0xb000 0x0 0x0 0x2 &cpld_pic 0x5 0x8
|
||||
|
||||
// IDSEL 0x17 - Slot 3 MiniPCI
|
||||
0xb800 0x0 0x0 0x1 &cpld_pic 0x6 0x8
|
||||
0xb800 0x0 0x0 0x2 &cpld_pic 0x7 0x8
|
||||
>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <1 0x8>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
|
||||
0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
|
||||
0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>;
|
||||
clock-frequency = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0x80008500 0x100>;
|
||||
compatible = "fsl,mpc5121-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -124,14 +124,12 @@
|
|||
};
|
||||
|
||||
mpic: pic@7400 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x7400 0x400>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
};
|
||||
pci@1000 {
|
||||
compatible = "tsi108-pci";
|
||||
|
|
|
|||
|
|
@ -217,6 +217,17 @@
|
|||
linux,network-index = <1>;
|
||||
fsl,cpm-command = <0x16200300>;
|
||||
};
|
||||
|
||||
i2c@11860 {
|
||||
compatible = "fsl,mpc8272-i2c",
|
||||
"fsl,cpm2-i2c";
|
||||
reg = <0x11860 0x20 0x8afc 0x2>;
|
||||
interrupts = <1 8>;
|
||||
interrupt-parent = <&PIC>;
|
||||
fsl,cpm-command = <0x29600000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
PIC: interrupt-controller@10c00 {
|
||||
|
|
@ -226,22 +237,15 @@
|
|||
compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic";
|
||||
};
|
||||
|
||||
/* May need to remove if on a part without crypto engine */
|
||||
crypto@30000 {
|
||||
device_type = "crypto";
|
||||
model = "SEC2";
|
||||
compatible = "fsl,mpc8272-talitos-sec2",
|
||||
"fsl,talitos-sec2",
|
||||
"fsl,talitos",
|
||||
"talitos";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 8>;
|
||||
compatible = "fsl,sec1.0";
|
||||
reg = <0x40000 0x13000>;
|
||||
interrupts = <47 0x8>;
|
||||
interrupt-parent = <&PIC>;
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x7e>;
|
||||
/* desc mask is for rev1.x, we need runtime fixup for >=2.x */
|
||||
descriptor-types-mask = <0x1010ebf>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x7e>;
|
||||
fsl,descriptor-types-mask = <0x1010415>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -144,6 +144,41 @@
|
|||
mode = "cpu";
|
||||
};
|
||||
|
||||
dma@82a8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8313-dma", "fsl,elo-dma";
|
||||
reg = <0x82a8 4>;
|
||||
ranges = <0 0x8100 0x1a8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x180 0x28>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
};
|
||||
|
||||
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
|
||||
usb@23000 {
|
||||
compatible = "fsl-usb2-dr";
|
||||
|
|
@ -219,17 +254,14 @@
|
|||
};
|
||||
|
||||
crypto@30000 {
|
||||
device_type = "crypto";
|
||||
model = "SEC2";
|
||||
compatible = "talitos";
|
||||
reg = <0x30000 0x7000>;
|
||||
compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
/* Rev. 2.2 */
|
||||
num-channels = <1>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x0000004c>;
|
||||
descriptor-types-mask = <0x0122003f>;
|
||||
fsl,num-channels = <1>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x4c>;
|
||||
fsl,descriptor-types-mask = <0x0122003f>;
|
||||
};
|
||||
|
||||
/* IPIC
|
||||
|
|
|
|||
|
|
@ -132,6 +132,41 @@
|
|||
mode = "cpu";
|
||||
};
|
||||
|
||||
dma@82a8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8315-dma", "fsl,elo-dma";
|
||||
reg = <0x82a8 4>;
|
||||
ranges = <0 0x8100 0x1a8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x180 0x28>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@23000 {
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x23000 0x1000>;
|
||||
|
|
@ -206,17 +241,16 @@
|
|||
};
|
||||
|
||||
crypto@30000 {
|
||||
model = "SEC3";
|
||||
device_type = "crypto";
|
||||
compatible = "talitos";
|
||||
compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
|
||||
"fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
|
||||
"fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
/* Rev. 3.0 geometry */
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x000001fe>;
|
||||
descriptor-types-mask = <0x03ab0ebf>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x97c>;
|
||||
fsl,descriptor-types-mask = <0x3ab0abf>;
|
||||
};
|
||||
|
||||
sata@18000 {
|
||||
|
|
|
|||
|
|
@ -114,18 +114,50 @@
|
|||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
dma@82a8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
|
||||
reg = <0x82a8 4>;
|
||||
ranges = <0 0x8100 0x1a8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x180 0x28>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
device_type = "crypto";
|
||||
model = "SEC2";
|
||||
compatible = "talitos";
|
||||
reg = <0x30000 0x7000>;
|
||||
compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
/* Rev. 2.2 */
|
||||
num-channels = <1>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x0000004c>;
|
||||
descriptor-types-mask = <0x0122003f>;
|
||||
fsl,num-channels = <1>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x4c>;
|
||||
fsl,descriptor-types-mask = <0x0122003f>;
|
||||
};
|
||||
|
||||
ipic: pic@700 {
|
||||
|
|
|
|||
|
|
@ -68,7 +68,7 @@
|
|||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <14 0x8>;
|
||||
interrupt-parent = <&pic>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
|
|
@ -79,7 +79,7 @@
|
|||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <9 0x8>;
|
||||
interrupt-parent = <&pic>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
|
|
@ -89,24 +89,56 @@
|
|||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <10 0x8>;
|
||||
interrupt-parent = <&pic>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
dma@82a8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
|
||||
reg = <0x82a8 4>;
|
||||
ranges = <0 0x8100 0x1a8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x180 0x28>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
device_type = "crypto";
|
||||
model = "SEC2";
|
||||
compatible = "talitos";
|
||||
reg = <0x30000 0x7000>;
|
||||
compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&pic>;
|
||||
/* Rev. 2.2 */
|
||||
num-channels = <1>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x0000004c>;
|
||||
descriptor-types-mask = <0x0122003f>;
|
||||
interrupt-parent = <&ipic>;
|
||||
fsl,num-channels = <1>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x4c>;
|
||||
fsl,descriptor-types-mask = <0x0122003f>;
|
||||
};
|
||||
|
||||
pic:pic@700 {
|
||||
ipic:pic@700 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
|
|
@ -240,13 +272,13 @@
|
|||
compatible = "fsl,ucc-mdio";
|
||||
|
||||
phy00:ethernet-phy@00 {
|
||||
interrupt-parent = <&pic>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <0>;
|
||||
reg = <0x0>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy04:ethernet-phy@04 {
|
||||
interrupt-parent = <&pic>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <0>;
|
||||
reg = <0x4>;
|
||||
device_type = "ethernet-phy";
|
||||
|
|
@ -261,7 +293,7 @@
|
|||
reg = <0x80 0x80>;
|
||||
big-endian;
|
||||
interrupts = <32 0x8 33 0x8>; //high:32 low:33
|
||||
interrupt-parent = <&pic>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -270,21 +302,21 @@
|
|||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x10 AD16 (USB) */
|
||||
0x8000 0x0 0x0 0x1 &pic 17 0x8
|
||||
0x8000 0x0 0x0 0x1 &ipic 17 0x8
|
||||
|
||||
/* IDSEL 0x11 AD17 (Mini1)*/
|
||||
0x8800 0x0 0x0 0x1 &pic 18 0x8
|
||||
0x8800 0x0 0x0 0x2 &pic 19 0x8
|
||||
0x8800 0x0 0x0 0x3 &pic 20 0x8
|
||||
0x8800 0x0 0x0 0x4 &pic 48 0x8
|
||||
0x8800 0x0 0x0 0x1 &ipic 18 0x8
|
||||
0x8800 0x0 0x0 0x2 &ipic 19 0x8
|
||||
0x8800 0x0 0x0 0x3 &ipic 20 0x8
|
||||
0x8800 0x0 0x0 0x4 &ipic 48 0x8
|
||||
|
||||
/* IDSEL 0x12 AD18 (PCI/Mini2) */
|
||||
0x9000 0x0 0x0 0x1 &pic 19 0x8
|
||||
0x9000 0x0 0x0 0x2 &pic 20 0x8
|
||||
0x9000 0x0 0x0 0x3 &pic 48 0x8
|
||||
0x9000 0x0 0x0 0x4 &pic 17 0x8>;
|
||||
0x9000 0x0 0x0 0x1 &ipic 19 0x8
|
||||
0x9000 0x0 0x0 0x2 &ipic 20 0x8
|
||||
0x9000 0x0 0x0 0x3 &ipic 48 0x8
|
||||
0x9000 0x0 0x0 0x4 &ipic 17 0x8>;
|
||||
|
||||
interrupt-parent = <&pic>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <66 0x8>;
|
||||
bus-range = <0x0 0x0>;
|
||||
ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
||||
|
|
|
|||
|
|
@ -93,6 +93,41 @@
|
|||
mode = "cpu";
|
||||
};
|
||||
|
||||
dma@82a8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
|
||||
reg = <0x82a8 4>;
|
||||
ranges = <0 0x8100 0x1a8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x180 0x28>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@22000 {
|
||||
compatible = "fsl-usb2-mph";
|
||||
reg = <0x22000 0x1000>;
|
||||
|
|
@ -178,16 +213,14 @@
|
|||
};
|
||||
|
||||
crypto@30000 {
|
||||
device_type = "crypto";
|
||||
model = "SEC2";
|
||||
compatible = "talitos";
|
||||
compatible = "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x0000007e>;
|
||||
descriptor-types-mask = <0x01010ebf>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x7e>;
|
||||
fsl,descriptor-types-mask = <0x01010ebf>;
|
||||
};
|
||||
|
||||
ipic: pic@700 {
|
||||
|
|
|
|||
|
|
@ -91,6 +91,41 @@
|
|||
mode = "cpu";
|
||||
};
|
||||
|
||||
dma@82a8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
|
||||
reg = <0x82a8 4>;
|
||||
ranges = <0 0x8100 0x1a8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x180 0x28>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@23000 {
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x23000 0x1000>;
|
||||
|
|
@ -151,16 +186,14 @@
|
|||
};
|
||||
|
||||
crypto@30000 {
|
||||
device_type = "crypto";
|
||||
model = "SEC2";
|
||||
compatible = "talitos";
|
||||
compatible = "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x0000007e>;
|
||||
descriptor-types-mask = <0x01010ebf>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x7e>;
|
||||
fsl,descriptor-types-mask = <0x01010ebf>;
|
||||
};
|
||||
|
||||
ipic: pic@700 {
|
||||
|
|
|
|||
|
|
@ -103,6 +103,41 @@
|
|||
mode = "cpu";
|
||||
};
|
||||
|
||||
dma@82a8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
|
||||
reg = <0x82a8 4>;
|
||||
ranges = <0 0x8100 0x1a8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x180 0x28>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
};
|
||||
|
||||
/* phy type (ULPI or SERIAL) are only types supported for MPH */
|
||||
/* port = 0 or 1 */
|
||||
usb@22000 {
|
||||
|
|
@ -193,20 +228,15 @@
|
|||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
/* May need to remove if on a part without crypto engine */
|
||||
crypto@30000 {
|
||||
device_type = "crypto";
|
||||
model = "SEC2";
|
||||
compatible = "talitos";
|
||||
compatible = "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x0000007e>;
|
||||
/* desc mask is for rev2.0,
|
||||
* we need runtime fixup for >2.0 */
|
||||
descriptor-types-mask = <0x01010ebf>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x7e>;
|
||||
fsl,descriptor-types-mask = <0x01010ebf>;
|
||||
};
|
||||
|
||||
/* IPIC
|
||||
|
|
|
|||
|
|
@ -118,18 +118,50 @@
|
|||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
dma@82a8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
|
||||
reg = <0x82a8 4>;
|
||||
ranges = <0 0x8100 0x1a8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x180 0x28>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
device_type = "crypto";
|
||||
model = "SEC2";
|
||||
compatible = "talitos";
|
||||
compatible = "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x0000007e>;
|
||||
/* desc mask is for rev1.x, we need runtime fixup for >=2.x */
|
||||
descriptor-types-mask = <0x01010ebf>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x7e>;
|
||||
fsl,descriptor-types-mask = <0x01010ebf>;
|
||||
};
|
||||
|
||||
ipic: pic@700 {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,432 @@
|
|||
/*
|
||||
* MPC8360E RDK Device Tree Source
|
||||
*
|
||||
* Copyright 2006 Freescale Semiconductor Inc.
|
||||
* Copyright 2007-2008 MontaVista Software, Inc.
|
||||
*
|
||||
* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8360rdk";
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
serial2 = &serial2;
|
||||
serial3 = &serial3;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8360@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
/* filled by u-boot */
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
/* filled by u-boot */
|
||||
reg = <0 0>;
|
||||
};
|
||||
|
||||
soc@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8360-immr", "fsl,immr", "fsl,soc",
|
||||
"simple-bus";
|
||||
ranges = <0 0xe0000000 0x200000>;
|
||||
reg = <0xe0000000 0x200>;
|
||||
/* filled by u-boot */
|
||||
bus-frequency = <0>;
|
||||
|
||||
wdt@200 {
|
||||
compatible = "mpc83xx_wdt";
|
||||
reg = <0x200 0x100>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <14 8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <16 8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
interrupts = <9 8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
/* filled by u-boot */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
interrupts = <10 8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
/* filled by u-boot */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
dma@82a8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
|
||||
reg = <0x82a8 4>;
|
||||
ranges = <0 0x8100 0x1a8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x180 0x28>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec2-crypto";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x7e>;
|
||||
/*
|
||||
* desc mask is for rev1.x, we need runtime fixup
|
||||
* for >=2.x
|
||||
*/
|
||||
descriptor-types-mask = <0x1010ebf>;
|
||||
};
|
||||
|
||||
ipic: interrupt-controller@700 {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "fsl,pq2pro-pic", "fsl,ipic";
|
||||
interrupt-controller;
|
||||
reg = <0x700 0x100>;
|
||||
};
|
||||
|
||||
qe_pio_b: gpio-controller@1418 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,mpc8360-qe-pario-bank",
|
||||
"fsl,mpc8323-qe-pario-bank";
|
||||
reg = <0x1418 0x18>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
qe_pio_e: gpio-controller@1460 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,mpc8360-qe-pario-bank",
|
||||
"fsl,mpc8323-qe-pario-bank";
|
||||
reg = <0x1460 0x18>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
qe@100000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "qe";
|
||||
compatible = "fsl,qe", "simple-bus";
|
||||
ranges = <0 0x100000 0x100000>;
|
||||
reg = <0x100000 0x480>;
|
||||
/* filled by u-boot */
|
||||
clock-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
brg-frequency = <0>;
|
||||
|
||||
muram@10000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,qe-muram", "fsl,cpm-muram";
|
||||
ranges = <0 0x10000 0xc000>;
|
||||
|
||||
data-only@0 {
|
||||
compatible = "fsl,qe-muram-data",
|
||||
"fsl,cpm-muram-data";
|
||||
reg = <0 0xc000>;
|
||||
};
|
||||
};
|
||||
|
||||
timer@440 {
|
||||
compatible = "fsl,mpc8360-qe-gtm",
|
||||
"fsl,qe-gtm", "fsl,gtm";
|
||||
reg = <0x440 0x40>;
|
||||
interrupts = <12 13 14 15>;
|
||||
interrupt-parent = <&qeic>;
|
||||
/* filled by u-boot */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
spi@4c0 {
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x4c0 0x40>;
|
||||
interrupts = <2>;
|
||||
interrupt-parent = <&qeic>;
|
||||
mode = "cpu-qe";
|
||||
};
|
||||
|
||||
spi@500 {
|
||||
cell-index = <1>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x500 0x40>;
|
||||
interrupts = <1>;
|
||||
interrupt-parent = <&qeic>;
|
||||
mode = "cpu-qe";
|
||||
};
|
||||
|
||||
enet0: ucc@2000 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <1>;
|
||||
reg = <0x2000 0x200>;
|
||||
interrupts = <32>;
|
||||
interrupt-parent = <&qeic>;
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk9";
|
||||
phy-handle = <&phy2>;
|
||||
phy-connection-type = "rgmii-rxid";
|
||||
/* filled by u-boot */
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
};
|
||||
|
||||
enet1: ucc@3000 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <2>;
|
||||
reg = <0x3000 0x200>;
|
||||
interrupts = <33>;
|
||||
interrupt-parent = <&qeic>;
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk4";
|
||||
phy-handle = <&phy4>;
|
||||
phy-connection-type = "rgmii-rxid";
|
||||
/* filled by u-boot */
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
};
|
||||
|
||||
enet2: ucc@2600 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <7>;
|
||||
reg = <0x2600 0x200>;
|
||||
interrupts = <42>;
|
||||
interrupt-parent = <&qeic>;
|
||||
rx-clock-name = "clk20";
|
||||
tx-clock-name = "clk19";
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "mii";
|
||||
/* filled by u-boot */
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
};
|
||||
|
||||
enet3: ucc@3200 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <4>;
|
||||
reg = <0x3200 0x200>;
|
||||
interrupts = <35>;
|
||||
interrupt-parent = <&qeic>;
|
||||
rx-clock-name = "clk8";
|
||||
tx-clock-name = "clk7";
|
||||
phy-handle = <&phy3>;
|
||||
phy-connection-type = "mii";
|
||||
/* filled by u-boot */
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
};
|
||||
|
||||
mdio@2120 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,ucc-mdio";
|
||||
reg = <0x2120 0x18>;
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
device_type = "ethernet-phy";
|
||||
compatible = "national,DP83848VV";
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
phy2: ethernet-phy@2 {
|
||||
device_type = "ethernet-phy";
|
||||
compatible = "broadcom,BCM5481UA2KMLG";
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
phy3: ethernet-phy@3 {
|
||||
device_type = "ethernet-phy";
|
||||
compatible = "national,DP83848VV";
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
phy4: ethernet-phy@4 {
|
||||
device_type = "ethernet-phy";
|
||||
compatible = "broadcom,BCM5481UA2KMLG";
|
||||
reg = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
serial2: ucc@2400 {
|
||||
device_type = "serial";
|
||||
compatible = "ucc_uart";
|
||||
reg = <0x2400 0x200>;
|
||||
cell-index = <5>;
|
||||
port-number = <0>;
|
||||
rx-clock-name = "brg7";
|
||||
tx-clock-name = "brg8";
|
||||
interrupts = <40>;
|
||||
interrupt-parent = <&qeic>;
|
||||
soft-uart;
|
||||
};
|
||||
|
||||
serial3: ucc@3400 {
|
||||
device_type = "serial";
|
||||
compatible = "ucc_uart";
|
||||
reg = <0x3400 0x200>;
|
||||
cell-index = <6>;
|
||||
port-number = <1>;
|
||||
rx-clock-name = "brg13";
|
||||
tx-clock-name = "brg14";
|
||||
interrupts = <41>;
|
||||
interrupt-parent = <&qeic>;
|
||||
soft-uart;
|
||||
};
|
||||
|
||||
qeic: interrupt-controller@80 {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "fsl,qe-ic";
|
||||
interrupt-controller;
|
||||
reg = <0x80 0x80>;
|
||||
big-endian;
|
||||
interrupts = <32 8 33 8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
localbus@e0005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
|
||||
"simple-bus";
|
||||
reg = <0xe0005000 0xd8>;
|
||||
ranges = <0 0 0xff800000 0x0800000
|
||||
1 0 0x60000000 0x0001000
|
||||
2 0 0x70000000 0x4000000>;
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "intel,PC28F640P30T85", "cfi-flash";
|
||||
reg = <0 0 0x800000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
||||
display@2,0 {
|
||||
device_type = "display";
|
||||
compatible = "fujitsu,MB86277", "fujitsu,mint";
|
||||
reg = <2 0 0x4000000>;
|
||||
fujitsu,sh3;
|
||||
little-endian;
|
||||
/* filled by u-boot */
|
||||
address = <0>;
|
||||
depth = <0>;
|
||||
width = <0>;
|
||||
height = <0>;
|
||||
linebytes = <0>;
|
||||
/* linux,opened; - added by uboot */
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pci@e0008500 {
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
device_type = "pci";
|
||||
compatible = "fsl,mpc8360-pci", "fsl,mpc8349-pci";
|
||||
reg = <0xe0008500 0x100>;
|
||||
ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
|
||||
0x42000000 0 0x80000000 0x80000000 0 0x10000000
|
||||
0x01000000 0 0xe0300000 0xe0300000 0 0x00100000>;
|
||||
interrupts = <66 8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = </* miniPCI0 IDSEL 0x14 AD20 */
|
||||
0xa000 0 0 1 &ipic 18 8
|
||||
0xa000 0 0 2 &ipic 19 8
|
||||
|
||||
/* PCI1 IDSEL 0x15 AD21 */
|
||||
0xa800 0 0 1 &ipic 19 8
|
||||
0xa800 0 0 2 &ipic 20 8
|
||||
0xa800 0 0 3 &ipic 21 8
|
||||
0xa800 0 0 4 &ipic 18 8>;
|
||||
/* filled by u-boot */
|
||||
bus-range = <0 0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -233,41 +233,6 @@
|
|||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
model = "SEC3";
|
||||
compatible = "talitos";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
/* Rev. 3.0 geometry */
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x000001fe>;
|
||||
descriptor-types-mask = <0x03ab0ebf>;
|
||||
};
|
||||
|
||||
sdhc@2e000 {
|
||||
model = "eSDHC";
|
||||
compatible = "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <42 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
sata@18000 {
|
||||
compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
|
||||
reg = <0x18000 0x1000>;
|
||||
interrupts = <44 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
sata@19000 {
|
||||
compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
|
||||
reg = <0x19000 0x1000>;
|
||||
interrupts = <45 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
dma@82a8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -303,6 +268,40 @@
|
|||
};
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
|
||||
"fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x9fe>;
|
||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||
};
|
||||
|
||||
sdhc@2e000 {
|
||||
model = "eSDHC";
|
||||
compatible = "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <42 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
sata@18000 {
|
||||
compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
|
||||
reg = <0x18000 0x1000>;
|
||||
interrupts = <44 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
sata@19000 {
|
||||
compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
|
||||
reg = <0x19000 0x1000>;
|
||||
interrupts = <45 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
/* IPIC
|
||||
* interrupts cell = <intr #, sense>
|
||||
* sense values match linux IORESOURCE_IRQ_* defines:
|
||||
|
|
|
|||
|
|
@ -143,6 +143,41 @@
|
|||
mode = "cpu";
|
||||
};
|
||||
|
||||
dma@82a8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
|
||||
reg = <0x82a8 4>;
|
||||
ranges = <0 0x8100 0x1a8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x180 0x28>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@23000 {
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x23000 0x1000>;
|
||||
|
|
@ -213,17 +248,15 @@
|
|||
};
|
||||
|
||||
crypto@30000 {
|
||||
model = "SEC3";
|
||||
device_type = "crypto";
|
||||
compatible = "talitos";
|
||||
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
|
||||
"fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
/* Rev. 3.0 geometry */
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x000001fe>;
|
||||
descriptor-types-mask = <0x03ab0ebf>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x9fe>;
|
||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||
};
|
||||
|
||||
sata@18000 {
|
||||
|
|
|
|||
|
|
@ -157,6 +157,41 @@
|
|||
mode = "cpu";
|
||||
};
|
||||
|
||||
dma@82a8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8378-dma", "fsl,elo-dma";
|
||||
reg = <0x82a8 4>;
|
||||
ranges = <0 0x8100 0x1a8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x180 0x28>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@23000 {
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x23000 0x1000>;
|
||||
|
|
@ -234,16 +269,15 @@
|
|||
};
|
||||
|
||||
crypto@30000 {
|
||||
model = "SEC3";
|
||||
compatible = "talitos";
|
||||
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
|
||||
"fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
/* Rev. 3.0 geometry */
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x000001fe>;
|
||||
descriptor-types-mask = <0x03ab0ebf>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x9fe>;
|
||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||
};
|
||||
|
||||
sdhc@2e000 {
|
||||
|
|
|
|||
|
|
@ -143,6 +143,41 @@
|
|||
mode = "cpu";
|
||||
};
|
||||
|
||||
dma@82a8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8378-dma", "fsl,elo-dma";
|
||||
reg = <0x82a8 4>;
|
||||
ranges = <0 0x8100 0x1a8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x180 0x28>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@23000 {
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x23000 0x1000>;
|
||||
|
|
@ -213,17 +248,15 @@
|
|||
};
|
||||
|
||||
crypto@30000 {
|
||||
model = "SEC3";
|
||||
device_type = "crypto";
|
||||
compatible = "talitos";
|
||||
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
|
||||
"fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
/* Rev. 3.0 geometry */
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x000001fe>;
|
||||
descriptor-types-mask = <0x03ab0ebf>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x9fe>;
|
||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||
};
|
||||
|
||||
/* IPIC
|
||||
|
|
|
|||
|
|
@ -157,6 +157,41 @@
|
|||
mode = "cpu";
|
||||
};
|
||||
|
||||
dma@82a8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8379-dma", "fsl,elo-dma";
|
||||
reg = <0x82a8 4>;
|
||||
ranges = <0 0x8100 0x1a8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x180 0x28>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@23000 {
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x23000 0x1000>;
|
||||
|
|
@ -234,16 +269,15 @@
|
|||
};
|
||||
|
||||
crypto@30000 {
|
||||
model = "SEC3";
|
||||
compatible = "talitos";
|
||||
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
|
||||
"fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
/* Rev. 3.0 geometry */
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x000001fe>;
|
||||
descriptor-types-mask = <0x03ab0ebf>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x9fe>;
|
||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||
};
|
||||
|
||||
sdhc@2e000 {
|
||||
|
|
|
|||
|
|
@ -143,6 +143,41 @@
|
|||
mode = "cpu";
|
||||
};
|
||||
|
||||
dma@82a8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8379-dma", "fsl,elo-dma";
|
||||
reg = <0x82a8 4>;
|
||||
ranges = <0 0x8100 0x1a8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x180 0x28>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@23000 {
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x23000 0x1000>;
|
||||
|
|
@ -213,17 +248,15 @@
|
|||
};
|
||||
|
||||
crypto@30000 {
|
||||
model = "SEC3";
|
||||
device_type = "crypto";
|
||||
compatible = "talitos";
|
||||
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
|
||||
"fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
/* Rev. 3.0 geometry */
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x000001fe>;
|
||||
descriptor-types-mask = <0x03ab0ebf>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x9fe>;
|
||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||
};
|
||||
|
||||
sata@18000 {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,432 @@
|
|||
/*
|
||||
* MPC8536 DS Device Tree Source
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "fsl,mpc8536ds";
|
||||
compatible = "fsl,mpc8536ds";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
pci3 = &pci3;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#cpus = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8536@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <00000000 00000000>; // Filled by U-Boot
|
||||
};
|
||||
|
||||
soc@ffe00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0x0 0xffe00000 0x100000>;
|
||||
reg = <0xffe00000 0x1000>;
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8536-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 0x2>;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8536-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 0x2>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds3232";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8536-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 4>;
|
||||
ranges = <0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8536-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <14 0x2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8536-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <15 0x2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8536-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 0x2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8536-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <17 0x2>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x24520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <10 0x1>;
|
||||
reg = <0>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <10 0x1>;
|
||||
reg = <1>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
usb@22000 {
|
||||
compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
|
||||
reg = <0x22000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <28 0x2>;
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
usb@23000 {
|
||||
compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
|
||||
reg = <0x23000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <46 0x2>;
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
enet1: ethernet@26000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x26000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <31 2 32 2 33 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
usb@2b000 {
|
||||
compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
|
||||
reg = <0x2b000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <60 0x2>;
|
||||
dr_mode = "peripheral";
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
|
||||
"fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2 58 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x9fe>;
|
||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||
};
|
||||
|
||||
sata@18000 {
|
||||
compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
|
||||
reg = <0x18000 0x1000>;
|
||||
cell-index = <1>;
|
||||
interrupts = <74 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
sata@19000 {
|
||||
compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
|
||||
reg = <0x19000 0x1000>;
|
||||
cell-index = <2>;
|
||||
interrupts = <41 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { //global utilities block
|
||||
compatible = "fsl,mpc8548-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,mpc8536-msi", "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0
|
||||
0xe4 0
|
||||
0xe5 0
|
||||
0xe6 0
|
||||
0xe7 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pci@ffe08000 {
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
|
||||
/* IDSEL 0x11 J17 Slot 1 */
|
||||
0x8800 0 0 1 &mpic 1 1
|
||||
0x8800 0 0 2 &mpic 2 1
|
||||
0x8800 0 0 3 &mpic 3 1
|
||||
0x8800 0 0 4 &mpic 4 1>;
|
||||
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <24 0x2>;
|
||||
bus-range = <0 0xff>;
|
||||
ranges = <0x02000000 0 0x80000000 0x80000000 0 0x10000000
|
||||
0x01000000 0 0x00000000 0xffc00000 0 0x00010000>;
|
||||
clock-frequency = <66666666>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xffe08000 0x1000>;
|
||||
};
|
||||
|
||||
pci1: pcie@ffe09000 {
|
||||
cell-index = <1>;
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xffe09000 0x1000>;
|
||||
bus-range = <0 0xff>;
|
||||
ranges = <0x02000000 0 0x98000000 0x98000000 0 0x08000000
|
||||
0x01000000 0 0x00000000 0xffc20000 0 0x00010000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <25 0x2>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 4 1
|
||||
0000 0 0 2 &mpic 5 1
|
||||
0000 0 0 3 &mpic 6 1
|
||||
0000 0 0 4 &mpic 7 1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0 0x98000000
|
||||
0x02000000 0 0x98000000
|
||||
0 0x08000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci2: pcie@ffe0a000 {
|
||||
cell-index = <2>;
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xffe0a000 0x1000>;
|
||||
bus-range = <0 0xff>;
|
||||
ranges = <0x02000000 0 0x90000000 0x90000000 0 0x08000000
|
||||
0x01000000 0 0x00000000 0xffc10000 0 0x00010000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <26 0x2>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 0 1
|
||||
0000 0 0 2 &mpic 1 1
|
||||
0000 0 0 3 &mpic 2 1
|
||||
0000 0 0 4 &mpic 3 1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0 0x90000000
|
||||
0x02000000 0 0x90000000
|
||||
0 0x08000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci3: pcie@ffe0b000 {
|
||||
cell-index = <3>;
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xffe0b000 0x1000>;
|
||||
bus-range = <0 0xff>;
|
||||
ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
|
||||
0x01000000 0 0x00000000 0xffc30000 0 0x00010000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <27 0x2>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 8 1
|
||||
0000 0 0 2 &mpic 9 1
|
||||
0000 0 0 3 &mpic 10 1
|
||||
0000 0 0 4 &mpic 11 1
|
||||
>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0 0xa0000000
|
||||
0x02000000 0 0xa0000000
|
||||
0 0x20000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -40,6 +40,7 @@
|
|||
timebase-frequency = <0>; // 33 MHz, from uboot
|
||||
bus-frequency = <0>; // 166 MHz
|
||||
clock-frequency = <0>; // 825 MHz, from uboot
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -63,7 +64,7 @@
|
|||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
l2-cache-controller@20000 {
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,8540-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
|
|
@ -83,6 +84,47 @@
|
|||
dfsrr;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8540-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8540-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8540-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8540-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -165,14 +207,12 @@
|
|||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -40,6 +40,7 @@
|
|||
timebase-frequency = <0>; // 33 MHz, from uboot
|
||||
bus-frequency = <0>; // 166 MHz
|
||||
clock-frequency = <0>; // 825 MHz, from uboot
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -63,7 +64,7 @@
|
|||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
l2-cache-controller@20000 {
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,8541-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
|
|
@ -83,6 +84,47 @@
|
|||
dfsrr;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8541-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8541-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8541-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8541-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -147,15 +189,24 @@
|
|||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x7e>;
|
||||
fsl,descriptor-types-mask = <0x01010ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
};
|
||||
|
||||
cpm@919c0 {
|
||||
|
|
|
|||
|
|
@ -41,6 +41,7 @@
|
|||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -65,7 +66,7 @@
|
|||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
l2-cache-controller@20000 {
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,8544-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
|
|
@ -209,15 +210,40 @@
|
|||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0xfe>;
|
||||
fsl,descriptor-types-mask = <0x12b0ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,mpc8544-msi", "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0
|
||||
0xe4 0
|
||||
0xe5 0
|
||||
0xe6 0
|
||||
0xe7 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -45,6 +45,7 @@
|
|||
timebase-frequency = <0>; // 33 MHz, from uboot
|
||||
bus-frequency = <0>; // 166 MHz
|
||||
clock-frequency = <0>; // 825 MHz, from uboot
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -68,7 +69,7 @@
|
|||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
l2-cache-controller@20000 {
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,8548-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
|
|
@ -99,6 +100,47 @@
|
|||
dfsrr;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -207,15 +249,24 @@
|
|||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0xfe>;
|
||||
fsl,descriptor-types-mask = <0x12b0ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -40,6 +40,7 @@
|
|||
timebase-frequency = <0>; // 33 MHz, from uboot
|
||||
bus-frequency = <0>; // 166 MHz
|
||||
clock-frequency = <0>; // 825 MHz, from uboot
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -63,7 +64,7 @@
|
|||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
l2-cache-controller@20000 {
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,8555-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
|
|
@ -83,6 +84,47 @@
|
|||
dfsrr;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8555-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8555-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8555-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8555-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -147,15 +189,24 @@
|
|||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x7e>;
|
||||
fsl,descriptor-types-mask = <0x01010ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
};
|
||||
|
||||
cpm@919c0 {
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@
|
|||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
l2-cache-controller@20000 {
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,8540-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
|
|
@ -73,6 +73,47 @@
|
|||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8560-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8560-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8560-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8560-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -134,6 +175,7 @@
|
|||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -42,6 +42,7 @@
|
|||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -70,7 +71,7 @@
|
|||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
l2-cache-controller@20000 {
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,8568-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
|
|
@ -106,6 +107,47 @@
|
|||
dfsrr;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8568-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8568-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8568-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8568-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8568-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -189,27 +231,23 @@
|
|||
};
|
||||
|
||||
crypto@30000 {
|
||||
device_type = "crypto";
|
||||
model = "SEC2";
|
||||
compatible = "talitos";
|
||||
reg = <0x30000 0xf000>;
|
||||
compatible = "fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0xfe>;
|
||||
descriptor-types-mask = <0x12b0ebf>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0xfe>;
|
||||
fsl,descriptor-types-mask = <0x12b0ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
};
|
||||
|
||||
par_io@e0100 {
|
||||
|
|
|
|||
|
|
@ -42,6 +42,7 @@
|
|||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
PowerPC,8572@1 {
|
||||
|
|
@ -54,6 +55,7 @@
|
|||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -84,7 +86,7 @@
|
|||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
l2-cache-controller@20000 {
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8572-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
|
|
@ -115,6 +117,88 @@
|
|||
dfsrr;
|
||||
};
|
||||
|
||||
dma@c300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
|
||||
reg = <0xc300 0x4>;
|
||||
ranges = <0x0 0xc100 0x200>;
|
||||
cell-index = <1>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <76 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <77 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <78 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <79 2>;
|
||||
};
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -221,15 +305,41 @@
|
|||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0
|
||||
0xe4 0
|
||||
0xe5 0
|
||||
0xe6 0
|
||||
0xe7 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
|
||||
"fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2 58 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x9fe>;
|
||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -172,14 +172,28 @@
|
|||
};
|
||||
|
||||
mpic: interrupt-controller@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0
|
||||
0xe4 0
|
||||
0xe5 0
|
||||
0xe6 0
|
||||
0xe7 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 {
|
||||
|
|
@ -349,7 +363,7 @@
|
|||
0xe000 0 0 4 &mpic 1 1
|
||||
|
||||
/* IDSEL 0x1f */
|
||||
0xf800 0 0 1 &mpic 3 0
|
||||
0xf800 0 0 1 &mpic 3 2
|
||||
0xf800 0 0 2 &mpic 0 1
|
||||
>;
|
||||
|
||||
|
|
|
|||
|
|
@ -134,6 +134,47 @@
|
|||
dfsrr;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -239,14 +280,12 @@
|
|||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
};
|
||||
|
||||
global-utilities@e0000 {
|
||||
|
|
|
|||
|
|
@ -171,6 +171,17 @@
|
|||
fsl,cpm-command = <0000>;
|
||||
linux,network-index = <1>;
|
||||
};
|
||||
|
||||
i2c@860 {
|
||||
compatible = "fsl,mpc866-i2c",
|
||||
"fsl,cpm1-i2c";
|
||||
reg = <0x860 0x20 0x3c80 0x30>;
|
||||
interrupts = <16>;
|
||||
interrupt-parent = <&CPM_PIC>;
|
||||
fsl,cpm-command = <0x10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -215,6 +215,17 @@
|
|||
fsl,cpm-command = <0x80>;
|
||||
linux,network-index = <2>;
|
||||
};
|
||||
|
||||
i2c@860 {
|
||||
compatible = "fsl,mpc885-i2c",
|
||||
"fsl,cpm1-i2c";
|
||||
reg = <0x860 0x20 0x3c80 0x30>;
|
||||
interrupts = <16>;
|
||||
interrupt-parent = <&CPM_PIC>;
|
||||
fsl,cpm-command = <0x10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -18,6 +18,8 @@
|
|||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "SonyPS3";
|
||||
compatible = "sony,ps3";
|
||||
|
|
@ -34,7 +36,7 @@
|
|||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0 0 0>;
|
||||
reg = <0x00000000 0x00000000 0x00000000 0x00000000>;
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -55,14 +57,14 @@
|
|||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
ibm,ppc-interrupt-server#s = <0 1>;
|
||||
reg = <0x00000000>;
|
||||
ibm,ppc-interrupt-server#s = <0x0 0x1>;
|
||||
clock-frequency = <0>;
|
||||
timebase-frequency = <0>;
|
||||
i-cache-size = <8000>;
|
||||
d-cache-size = <8000>;
|
||||
i-cache-line-size = <80>;
|
||||
d-cache-line-size = <80>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-line-size = <128>;
|
||||
d-cache-line-size = <128>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -12,12 +12,14 @@
|
|||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,rainier";
|
||||
compatible = "amcc,rainier";
|
||||
dcr-parent = <&/cpus/cpu@0>;
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
|
|
@ -35,13 +37,13 @@
|
|||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,440GRx";
|
||||
reg = <0>;
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
timebase-frequency = <0>; /* Filled in by zImage */
|
||||
i-cache-line-size = <20>;
|
||||
d-cache-line-size = <20>;
|
||||
i-cache-size = <8000>;
|
||||
d-cache-size = <8000>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
|
|
@ -49,14 +51,14 @@
|
|||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0 0>; /* Filled in by zImage */
|
||||
reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller0 {
|
||||
compatible = "ibm,uic-440grx","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0c0 009>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
|
|
@ -66,11 +68,11 @@
|
|||
compatible = "ibm,uic-440grx","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0d0 009>;
|
||||
dcr-reg = <0x0d0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <1e 4 1f 4>; /* cascade */
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
|
|
@ -78,22 +80,22 @@
|
|||
compatible = "ibm,uic-440grx","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <2>;
|
||||
dcr-reg = <0e0 009>;
|
||||
dcr-reg = <0x0e0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <1c 4 1d 4>; /* cascade */
|
||||
interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
SDR0: sdr {
|
||||
compatible = "ibm,sdr-440grx", "ibm,sdr-440ep";
|
||||
dcr-reg = <00e 002>;
|
||||
dcr-reg = <0x00e 0x002>;
|
||||
};
|
||||
|
||||
CPR0: cpr {
|
||||
compatible = "ibm,cpr-440grx", "ibm,cpr-440ep";
|
||||
dcr-reg = <00c 002>;
|
||||
dcr-reg = <0x00c 0x002>;
|
||||
};
|
||||
|
||||
plb {
|
||||
|
|
@ -105,80 +107,80 @@
|
|||
|
||||
SDRAM0: sdram {
|
||||
compatible = "ibm,sdram-440grx", "ibm,sdram-44x-ddr2denali";
|
||||
dcr-reg = <010 2>;
|
||||
dcr-reg = <0x010 0x002>;
|
||||
};
|
||||
|
||||
DMA0: dma {
|
||||
compatible = "ibm,dma-440grx", "ibm,dma-4xx";
|
||||
dcr-reg = <100 027>;
|
||||
dcr-reg = <0x100 0x027>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-440grx", "ibm,mcmal2";
|
||||
dcr-reg = <180 62>;
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <2>;
|
||||
num-rx-chans = <2>;
|
||||
interrupt-parent = <&MAL0>;
|
||||
interrupts = <0 1 2 3 4>;
|
||||
interrupts = <0x0 0x1 0x2 0x3 0x4>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
|
||||
/*RXEOB*/ 1 &UIC0 b 4
|
||||
/*SERR*/ 2 &UIC1 0 4
|
||||
/*TXDE*/ 3 &UIC1 1 4
|
||||
/*RXDE*/ 4 &UIC1 2 4>;
|
||||
interrupt-map-mask = <ffffffff>;
|
||||
interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
|
||||
/*RXEOB*/ 0x1 &UIC0 0xb 0x4
|
||||
/*SERR*/ 0x2 &UIC1 0x0 0x4
|
||||
/*TXDE*/ 0x3 &UIC1 0x1 0x4
|
||||
/*RXDE*/ 0x4 &UIC1 0x2 0x4>;
|
||||
interrupt-map-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-440grx", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <00000000 1 00000000 80000000
|
||||
80000000 1 80000000 80000000>;
|
||||
ranges = <0x00000000 0x00000001 0x00000000 0x80000000
|
||||
0x80000000 0x00000001 0x80000000 0x80000000>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <7 4>;
|
||||
interrupts = <0x7 0x4>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-440grx", "ibm,ebc";
|
||||
dcr-reg = <012 2>;
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
interrupts = <5 1>;
|
||||
interrupts = <0x5 0x1>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
|
||||
nor_flash@0,0 {
|
||||
compatible = "amd,s29gl256n", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0 000000 4000000>;
|
||||
reg = <0x00000000 0x00000000 0x04000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "Kernel";
|
||||
reg = <0 180000>;
|
||||
reg = <0x00000000 0x00180000>;
|
||||
};
|
||||
partition@180000 {
|
||||
label = "ramdisk";
|
||||
reg = <180000 200000>;
|
||||
reg = <0x00180000 0x00200000>;
|
||||
};
|
||||
partition@380000 {
|
||||
label = "file system";
|
||||
reg = <380000 3aa0000>;
|
||||
reg = <0x00380000 0x03aa0000>;
|
||||
};
|
||||
partition@3e20000 {
|
||||
label = "kozio";
|
||||
reg = <3e20000 140000>;
|
||||
reg = <0x03e20000 0x00140000>;
|
||||
};
|
||||
partition@3f60000 {
|
||||
label = "env";
|
||||
reg = <3f60000 40000>;
|
||||
reg = <0x03f60000 0x00040000>;
|
||||
};
|
||||
partition@3fa0000 {
|
||||
label = "u-boot";
|
||||
reg = <3fa0000 60000>;
|
||||
reg = <0x03fa0000 0x00060000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -187,69 +189,69 @@
|
|||
UART0: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600300 8>;
|
||||
virtual-reg = <ef600300>;
|
||||
reg = <0xef600300 0x00000008>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
current-speed = <1c200>;
|
||||
current-speed = <115200>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0 4>;
|
||||
interrupts = <0x0 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600400 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600400 8>;
|
||||
virtual-reg = <ef600400>;
|
||||
reg = <0xef600400 0x00000008>;
|
||||
virtual-reg = <0xef600400>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <1 4>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
UART2: serial@ef600500 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600500 8>;
|
||||
virtual-reg = <ef600500>;
|
||||
reg = <0xef600500 0x00000008>;
|
||||
virtual-reg = <0xef600500>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <3 4>;
|
||||
interrupts = <0x3 0x4>;
|
||||
};
|
||||
|
||||
UART3: serial@ef600600 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600600 8>;
|
||||
virtual-reg = <ef600600>;
|
||||
reg = <0xef600600 0x00000008>;
|
||||
virtual-reg = <0xef600600>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <4 4>;
|
||||
interrupts = <0x4 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@ef600700 {
|
||||
compatible = "ibm,iic-440grx", "ibm,iic";
|
||||
reg = <ef600700 14>;
|
||||
reg = <0xef600700 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <2 4>;
|
||||
interrupts = <0x2 0x4>;
|
||||
};
|
||||
|
||||
IIC1: i2c@ef600800 {
|
||||
compatible = "ibm,iic-440grx", "ibm,iic";
|
||||
reg = <ef600800 14>;
|
||||
reg = <0xef600800 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <7 4>;
|
||||
interrupts = <0x7 0x4>;
|
||||
};
|
||||
|
||||
ZMII0: emac-zmii@ef600d00 {
|
||||
compatible = "ibm,zmii-440grx", "ibm,zmii";
|
||||
reg = <ef600d00 c>;
|
||||
reg = <0xef600d00 0x0000000c>;
|
||||
};
|
||||
|
||||
RGMII0: emac-rgmii@ef601000 {
|
||||
compatible = "ibm,rgmii-440grx", "ibm,rgmii";
|
||||
reg = <ef601000 8>;
|
||||
reg = <0xef601000 0x00000008>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
|
|
@ -257,23 +259,23 @@
|
|||
device_type = "network";
|
||||
compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4";
|
||||
interrupt-parent = <&EMAC0>;
|
||||
interrupts = <0 1>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0 &UIC0 18 4
|
||||
/*Wake*/ 1 &UIC1 1d 4>;
|
||||
reg = <ef600e00 70>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
|
||||
/*Wake*/ 0x1 &UIC1 0x1d 0x4>;
|
||||
reg = <0xef600e00 0x00000074>;
|
||||
local-mac-address = [000000000000];
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <2328>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <00000000>;
|
||||
phy-map = <0x00000000>;
|
||||
zmii-device = <&ZMII0>;
|
||||
zmii-channel = <0>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
|
|
@ -286,23 +288,23 @@
|
|||
device_type = "network";
|
||||
compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4";
|
||||
interrupt-parent = <&EMAC1>;
|
||||
interrupts = <0 1>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0 &UIC0 19 4
|
||||
/*Wake*/ 1 &UIC1 1f 4>;
|
||||
reg = <ef600f00 70>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
|
||||
/*Wake*/ 0x1 &UIC1 0x1f 0x4>;
|
||||
reg = <0xef600f00 0x00000074>;
|
||||
local-mac-address = [000000000000];
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <1>;
|
||||
mal-rx-channel = <1>;
|
||||
cell-index = <1>;
|
||||
max-frame-size = <2328>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <00000000>;
|
||||
phy-map = <0x00000000>;
|
||||
zmii-device = <&ZMII0>;
|
||||
zmii-channel = <1>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
|
|
@ -319,24 +321,25 @@
|
|||
#address-cells = <3>;
|
||||
compatible = "ibm,plb440grx-pci", "ibm,plb-pci";
|
||||
primary;
|
||||
reg = <1 eec00000 8 /* Config space access */
|
||||
1 eed00000 4 /* IACK */
|
||||
1 eed00000 4 /* Special cycle */
|
||||
1 ef400000 40>; /* Internal registers */
|
||||
reg = <0x00000001 0xeec00000 0x00000008 /* Config space access */
|
||||
0x00000001 0xeed00000 0x00000004 /* IACK */
|
||||
0x00000001 0xeed00000 0x00000004 /* Special cycle */
|
||||
0x00000001 0xef400000 0x00000040>; /* Internal registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed. Chip supports a second
|
||||
* IO range but we don't use it for now
|
||||
*/
|
||||
ranges = <02000000 0 80000000 1 80000000 0 10000000
|
||||
01000000 0 00000000 1 e8000000 0 00100000>;
|
||||
ranges = <0x02000000 0x0 0x80000000 0x1 0x80000000 0x0 0x40000000
|
||||
0x01000000 0x0 0x00000000 0x1 0xe8000000 0x0 0x00010000
|
||||
0x01000000 0x0 0x00000000 0x1 0xe8800000 0x0 0x03800000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 0 80000000>;
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* All PCI interrupts are routed to IRQ 67 */
|
||||
interrupt-map-mask = <0000 0 0 0>;
|
||||
interrupt-map = < 0000 0 0 0 &UIC2 3 8 >;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x0>;
|
||||
interrupt-map = < 0x0 0x0 0x0 0x0 &UIC2 0x3 0x8 >;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,293 @@
|
|||
/*
|
||||
* Device Tree Source for ACube Sam440ep based off bamboo.dts code
|
||||
* original copyrights below
|
||||
*
|
||||
* Copyright (c) 2006, 2007 IBM Corp.
|
||||
* Josh Boyer <jwboyer@linux.vnet.ibm.com>
|
||||
*
|
||||
* Modified from bamboo.dts for sam440ep:
|
||||
* Copyright 2008 Giuseppe Coviello <gicoviello@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
model = "acube,sam440ep";
|
||||
compatible = "acube,sam440ep";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
ethernet1 = &EMAC1;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
serial2 = &UART2;
|
||||
serial3 = &UART3;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,440EP";
|
||||
reg = <0>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
timebase-frequency = <0>; /* Filled in by zImage */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0 0>; /* Filled in by zImage */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller0 {
|
||||
compatible = "ibm,uic-440ep","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0x0c0 9>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
UIC1: interrupt-controller1 {
|
||||
compatible = "ibm,uic-440ep","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0x0d0 9>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x1e 4 0x1f 4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
SDR0: sdr {
|
||||
compatible = "ibm,sdr-440ep";
|
||||
dcr-reg = <0x00e 2>;
|
||||
};
|
||||
|
||||
CPR0: cpr {
|
||||
compatible = "ibm,cpr-440ep";
|
||||
dcr-reg = <0x00c 2>;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb-440ep", "ibm,plb-440gp", "ibm,plb4";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
SDRAM0: sdram {
|
||||
compatible = "ibm,sdram-440ep", "ibm,sdram-405gp";
|
||||
dcr-reg = <0x010 2>;
|
||||
};
|
||||
|
||||
DMA0: dma {
|
||||
compatible = "ibm,dma-440ep", "ibm,dma-440gp";
|
||||
dcr-reg = <0x100 0x027>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal";
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <4>;
|
||||
num-rx-chans = <2>;
|
||||
interrupt-parent = <&MAL0>;
|
||||
interrupts = <0 1 2 3 4>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*TXEOB*/ 0 &UIC0 10 4
|
||||
/*RXEOB*/ 1 &UIC0 11 4
|
||||
/*SERR*/ 2 &UIC1 0 4
|
||||
/*TXDE*/ 3 &UIC1 1 4
|
||||
/*RXDE*/ 4 &UIC1 2 4>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-440ep", "ibm,opb-440gp", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/* Bamboo is oddball in the 44x world and doesn't use the ERPN
|
||||
* bits.
|
||||
*/
|
||||
ranges = <0x00000000 0 0x00000000 0x80000000
|
||||
0x80000000 0 0x80000000 0x80000000>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <7 4>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc";
|
||||
dcr-reg = <0x012 2>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
interrupts = <5 1>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
};
|
||||
|
||||
UART0: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600300 8>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
current-speed = <0x1c200>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0 4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600400 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600400 8>;
|
||||
virtual-reg = <0xef600400>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <1 4>;
|
||||
};
|
||||
|
||||
UART2: serial@ef600500 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600500 8>;
|
||||
virtual-reg = <0xef600500>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <3 4>;
|
||||
};
|
||||
|
||||
UART3: serial@ef600600 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600600 8>;
|
||||
virtual-reg = <0xef600600>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <4 4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@ef600700 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
|
||||
index = <0>;
|
||||
reg = <0xef600700 0x14>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <2 4>;
|
||||
rtc@68 {
|
||||
compatible = "stm,m41t80";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
IIC1: i2c@ef600800 {
|
||||
compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
|
||||
index = <5>;
|
||||
reg = <0xef600800 0x14>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <7 4>;
|
||||
};
|
||||
|
||||
ZMII0: emac-zmii@ef600d00 {
|
||||
compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii";
|
||||
reg = <0xef600d00 0xc>;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600e00 {
|
||||
linux,network-index = <0>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x1c 4 0x1d 4>;
|
||||
reg = <0xef600e00 0x70>;
|
||||
local-mac-address = [000000000000];
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0 1>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <0x5dc>;
|
||||
rx-fifo-size = <0x1000>;
|
||||
tx-fifo-size = <0x800>;
|
||||
phy-mode = "rmii";
|
||||
phy-map = <00000000>;
|
||||
zmii-device = <&ZMII0>;
|
||||
zmii-channel = <0>;
|
||||
};
|
||||
|
||||
EMAC1: ethernet@ef600f00 {
|
||||
linux,network-index = <1>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x1e 4 0x1f 4>;
|
||||
reg = <0xef600f00 0x70>;
|
||||
local-mac-address = [000000000000];
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <2 3>;
|
||||
mal-rx-channel = <1>;
|
||||
cell-index = <1>;
|
||||
max-frame-size = <0x5dc>;
|
||||
rx-fifo-size = <0x1000>;
|
||||
tx-fifo-size = <0x800>;
|
||||
phy-mode = "rmii";
|
||||
phy-map = <00000000>;
|
||||
zmii-device = <&ZMII0>;
|
||||
zmii-channel = <1>;
|
||||
};
|
||||
usb@ef601000 {
|
||||
compatible = "ohci-be";
|
||||
reg = <0xef601000 0x80>;
|
||||
interrupts = <8 4 9 4>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
};
|
||||
};
|
||||
|
||||
PCI0: pci@ec000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb440ep-pci", "ibm,plb-pci";
|
||||
primary;
|
||||
reg = <0 0xeec00000 8 /* Config space access */
|
||||
0 0xeed00000 4 /* IACK */
|
||||
0 0xeed00000 4 /* Special cycle */
|
||||
0 0xef400000 0x40>; /* Internal registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed. Chip supports a second
|
||||
* IO range but we don't use it for now
|
||||
*/
|
||||
ranges = <0x02000000 0 0xa0000000 0 0xa0000000 0 0x20000000
|
||||
0x01000000 0 0x00000000 0 0xe8000000 0 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0 0 0 0 0 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = "/plb/opb/serial@ef600300";
|
||||
};
|
||||
};
|
||||
|
|
@ -95,6 +95,41 @@
|
|||
mode = "cpu";
|
||||
};
|
||||
|
||||
dma@82a8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
|
||||
reg = <0x82a8 4>;
|
||||
ranges = <0 0x8100 0x1a8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x180 0x28>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
};
|
||||
|
||||
/* phy type (ULPI or SERIAL) are only types supported for MPH */
|
||||
/* port = 0 or 1 */
|
||||
usb@22000 {
|
||||
|
|
@ -186,19 +221,15 @@
|
|||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
/* May need to remove if on a part without crypto engine */
|
||||
crypto@30000 {
|
||||
model = "SEC2";
|
||||
compatible = "talitos";
|
||||
compatible = "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x0000007e>;
|
||||
/* desc mask is for rev2.0,
|
||||
* we need runtime fixup for >2.0 */
|
||||
descriptor-types-mask = <0x01010ebf>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x7e>;
|
||||
fsl,descriptor-types-mask = <0x01010ebf>;
|
||||
};
|
||||
|
||||
/* IPIC
|
||||
|
|
|
|||
|
|
@ -44,6 +44,7 @@
|
|||
timebase-frequency = <0>; // From uboot
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -161,7 +162,7 @@
|
|||
interrupts = <0x12 0x2>;
|
||||
};
|
||||
|
||||
l2-cache-controller@20000 {
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,8548-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <0x20>; // 32 bytes
|
||||
|
|
@ -192,6 +193,47 @@
|
|||
dfsrr;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -262,15 +304,24 @@
|
|||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0xfe>;
|
||||
fsl,descriptor-types-mask = <0x12b0ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -43,6 +43,7 @@
|
|||
timebase-frequency = <0>; // From uboot
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -66,7 +67,7 @@
|
|||
interrupts = <0x12 0x2>;
|
||||
};
|
||||
|
||||
l2-cache-controller@20000 {
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,8560-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <0x20>; // 32 bytes
|
||||
|
|
@ -97,6 +98,47 @@
|
|||
dfsrr;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8560-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8560-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8560-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8560-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -155,8 +197,8 @@
|
|||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "chrp,open-pic";
|
||||
reg = <0x40000 0x40000>;
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -151,6 +151,47 @@
|
|||
dfsrr;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -12,12 +12,14 @@
|
|||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,sequoia";
|
||||
compatible = "amcc,sequoia";
|
||||
dcr-parent = <&/cpus/cpu@0>;
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
|
|
@ -35,13 +37,13 @@
|
|||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,440EPx";
|
||||
reg = <0>;
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
timebase-frequency = <0>; /* Filled in by zImage */
|
||||
i-cache-line-size = <20>;
|
||||
d-cache-line-size = <20>;
|
||||
i-cache-size = <8000>;
|
||||
d-cache-size = <8000>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
|
|
@ -49,14 +51,14 @@
|
|||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0 0>; /* Filled in by zImage */
|
||||
reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller0 {
|
||||
compatible = "ibm,uic-440epx","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0c0 009>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
|
|
@ -66,11 +68,11 @@
|
|||
compatible = "ibm,uic-440epx","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0d0 009>;
|
||||
dcr-reg = <0x0d0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <1e 4 1f 4>; /* cascade */
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
|
|
@ -78,22 +80,22 @@
|
|||
compatible = "ibm,uic-440epx","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <2>;
|
||||
dcr-reg = <0e0 009>;
|
||||
dcr-reg = <0x0e0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <1c 4 1d 4>; /* cascade */
|
||||
interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
SDR0: sdr {
|
||||
compatible = "ibm,sdr-440epx", "ibm,sdr-440ep";
|
||||
dcr-reg = <00e 002>;
|
||||
dcr-reg = <0x00e 0x002>;
|
||||
};
|
||||
|
||||
CPR0: cpr {
|
||||
compatible = "ibm,cpr-440epx", "ibm,cpr-440ep";
|
||||
dcr-reg = <00c 002>;
|
||||
dcr-reg = <0x00c 0x002>;
|
||||
};
|
||||
|
||||
plb {
|
||||
|
|
@ -105,44 +107,44 @@
|
|||
|
||||
SDRAM0: sdram {
|
||||
compatible = "ibm,sdram-440epx", "ibm,sdram-44x-ddr2denali";
|
||||
dcr-reg = <010 2>;
|
||||
dcr-reg = <0x010 0x002>;
|
||||
};
|
||||
|
||||
DMA0: dma {
|
||||
compatible = "ibm,dma-440epx", "ibm,dma-4xx";
|
||||
dcr-reg = <100 027>;
|
||||
dcr-reg = <0x100 0x027>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-440epx", "ibm,mcmal2";
|
||||
dcr-reg = <180 62>;
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <2>;
|
||||
num-rx-chans = <2>;
|
||||
interrupt-parent = <&MAL0>;
|
||||
interrupts = <0 1 2 3 4>;
|
||||
interrupts = <0x0 0x1 0x2 0x3 0x4>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
|
||||
/*RXEOB*/ 1 &UIC0 b 4
|
||||
/*SERR*/ 2 &UIC1 0 4
|
||||
/*TXDE*/ 3 &UIC1 1 4
|
||||
/*RXDE*/ 4 &UIC1 2 4>;
|
||||
interrupt-map-mask = <ffffffff>;
|
||||
interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
|
||||
/*RXEOB*/ 0x1 &UIC0 0xb 0x4
|
||||
/*SERR*/ 0x2 &UIC1 0x0 0x4
|
||||
/*TXDE*/ 0x3 &UIC1 0x1 0x4
|
||||
/*RXDE*/ 0x4 &UIC1 0x2 0x4>;
|
||||
interrupt-map-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
USB1: usb@e0000400 {
|
||||
compatible = "ohci-be";
|
||||
reg = <0 e0000400 60>;
|
||||
reg = <0x00000000 0xe0000400 0x00000060>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <15 8>;
|
||||
interrupts = <0x15 0x8>;
|
||||
};
|
||||
|
||||
USB0: ehci@e0000300 {
|
||||
compatible = "ibm,usb-ehci-440epx", "usb-ehci";
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <1a 4>;
|
||||
reg = <0 e0000300 90 0 e0000390 70>;
|
||||
interrupts = <0x1a 0x4>;
|
||||
reg = <0x00000000 0xe0000300 0x00000090 0x00000000 0xe0000390 0x00000070>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
|
|
@ -150,50 +152,50 @@
|
|||
compatible = "ibm,opb-440epx", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <00000000 1 00000000 80000000
|
||||
80000000 1 80000000 80000000>;
|
||||
ranges = <0x00000000 0x00000001 0x00000000 0x80000000
|
||||
0x80000000 0x00000001 0x80000000 0x80000000>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <7 4>;
|
||||
interrupts = <0x7 0x4>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-440epx", "ibm,ebc";
|
||||
dcr-reg = <012 2>;
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
interrupts = <5 1>;
|
||||
interrupts = <0x5 0x1>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
|
||||
nor_flash@0,0 {
|
||||
compatible = "amd,s29gl256n", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0 000000 4000000>;
|
||||
reg = <0x00000000 0x00000000 0x04000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "Kernel";
|
||||
reg = <0 180000>;
|
||||
reg = <0x00000000 0x00180000>;
|
||||
};
|
||||
partition@180000 {
|
||||
label = "ramdisk";
|
||||
reg = <180000 200000>;
|
||||
reg = <0x00180000 0x00200000>;
|
||||
};
|
||||
partition@380000 {
|
||||
label = "file system";
|
||||
reg = <380000 3aa0000>;
|
||||
reg = <0x00380000 0x03aa0000>;
|
||||
};
|
||||
partition@3e20000 {
|
||||
label = "kozio";
|
||||
reg = <3e20000 140000>;
|
||||
reg = <0x03e20000 0x00140000>;
|
||||
};
|
||||
partition@3f60000 {
|
||||
label = "env";
|
||||
reg = <3f60000 40000>;
|
||||
reg = <0x03f60000 0x00040000>;
|
||||
};
|
||||
partition@3fa0000 {
|
||||
label = "u-boot";
|
||||
reg = <3fa0000 60000>;
|
||||
reg = <0x03fa0000 0x00060000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -202,69 +204,69 @@
|
|||
UART0: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600300 8>;
|
||||
virtual-reg = <ef600300>;
|
||||
reg = <0xef600300 0x00000008>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
current-speed = <1c200>;
|
||||
current-speed = <115200>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0 4>;
|
||||
interrupts = <0x0 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600400 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600400 8>;
|
||||
virtual-reg = <ef600400>;
|
||||
reg = <0xef600400 0x00000008>;
|
||||
virtual-reg = <0xef600400>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <1 4>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
UART2: serial@ef600500 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600500 8>;
|
||||
virtual-reg = <ef600500>;
|
||||
reg = <0xef600500 0x00000008>;
|
||||
virtual-reg = <0xef600500>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <3 4>;
|
||||
interrupts = <0x3 0x4>;
|
||||
};
|
||||
|
||||
UART3: serial@ef600600 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600600 8>;
|
||||
virtual-reg = <ef600600>;
|
||||
reg = <0xef600600 0x00000008>;
|
||||
virtual-reg = <0xef600600>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <4 4>;
|
||||
interrupts = <0x4 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@ef600700 {
|
||||
compatible = "ibm,iic-440epx", "ibm,iic";
|
||||
reg = <ef600700 14>;
|
||||
reg = <0xef600700 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <2 4>;
|
||||
interrupts = <0x2 0x4>;
|
||||
};
|
||||
|
||||
IIC1: i2c@ef600800 {
|
||||
compatible = "ibm,iic-440epx", "ibm,iic";
|
||||
reg = <ef600800 14>;
|
||||
reg = <0xef600800 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <7 4>;
|
||||
interrupts = <0x7 0x4>;
|
||||
};
|
||||
|
||||
ZMII0: emac-zmii@ef600d00 {
|
||||
compatible = "ibm,zmii-440epx", "ibm,zmii";
|
||||
reg = <ef600d00 c>;
|
||||
reg = <0xef600d00 0x0000000c>;
|
||||
};
|
||||
|
||||
RGMII0: emac-rgmii@ef601000 {
|
||||
compatible = "ibm,rgmii-440epx", "ibm,rgmii";
|
||||
reg = <ef601000 8>;
|
||||
reg = <0xef601000 0x00000008>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
|
|
@ -272,23 +274,23 @@
|
|||
device_type = "network";
|
||||
compatible = "ibm,emac-440epx", "ibm,emac4";
|
||||
interrupt-parent = <&EMAC0>;
|
||||
interrupts = <0 1>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0 &UIC0 18 4
|
||||
/*Wake*/ 1 &UIC1 1d 4>;
|
||||
reg = <ef600e00 70>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
|
||||
/*Wake*/ 0x1 &UIC1 0x1d 0x4>;
|
||||
reg = <0xef600e00 0x00000074>;
|
||||
local-mac-address = [000000000000];
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <2328>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <00000000>;
|
||||
phy-map = <0x00000000>;
|
||||
zmii-device = <&ZMII0>;
|
||||
zmii-channel = <0>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
|
|
@ -301,23 +303,23 @@
|
|||
device_type = "network";
|
||||
compatible = "ibm,emac-440epx", "ibm,emac4";
|
||||
interrupt-parent = <&EMAC1>;
|
||||
interrupts = <0 1>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0 &UIC0 19 4
|
||||
/*Wake*/ 1 &UIC1 1f 4>;
|
||||
reg = <ef600f00 70>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
|
||||
/*Wake*/ 0x1 &UIC1 0x1f 0x4>;
|
||||
reg = <0xef600f00 0x00000074>;
|
||||
local-mac-address = [000000000000];
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <1>;
|
||||
mal-rx-channel = <1>;
|
||||
cell-index = <1>;
|
||||
max-frame-size = <2328>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <00000000>;
|
||||
phy-map = <0x00000000>;
|
||||
zmii-device = <&ZMII0>;
|
||||
zmii-channel = <1>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
|
|
@ -334,10 +336,10 @@
|
|||
#address-cells = <3>;
|
||||
compatible = "ibm,plb440epx-pci", "ibm,plb-pci";
|
||||
primary;
|
||||
reg = <1 eec00000 8 /* Config space access */
|
||||
1 eed00000 4 /* IACK */
|
||||
1 eed00000 4 /* Special cycle */
|
||||
1 ef400000 40>; /* Internal registers */
|
||||
reg = <0x00000001 0xeec00000 0x00000008 /* Config space access */
|
||||
0x00000001 0xeed00000 0x00000004 /* IACK */
|
||||
0x00000001 0xeed00000 0x00000004 /* Special cycle */
|
||||
0x00000001 0xef400000 0x00000040>; /* Internal registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed. Chip supports a second
|
||||
|
|
@ -347,16 +349,16 @@
|
|||
* I/O 1 E800 0000 1 E800 FFFF 64KB
|
||||
* I/O 1 E880 0000 1 EBFF FFFF 56MB
|
||||
*/
|
||||
ranges = <02000000 0 80000000 1 80000000 0 40000000
|
||||
01000000 0 00000000 1 e8000000 0 00010000
|
||||
01000000 0 00000000 1 e8800000 0 03800000>;
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x00000001 0x80000000 0x00000000 0x40000000
|
||||
0x01000000 0x00000000 0x00000000 0x00000001 0xe8000000 0x00000000 0x00010000
|
||||
0x01000000 0x00000000 0x00000000 0x00000001 0xe8800000 0x00000000 0x03800000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 0 80000000>;
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* All PCI interrupts are routed to IRQ 67 */
|
||||
interrupt-map-mask = <0000 0 0 0>;
|
||||
interrupt-map = < 0000 0 0 0 &UIC2 3 8 >;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x0>;
|
||||
interrupt-map = < 0x0 0x0 0x0 0x0 &UIC2 0x3 0x8 >;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -95,6 +95,7 @@
|
|||
|
||||
mpic: interrupt-controller@40000 {
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
device_type = "open-pic";
|
||||
compatible = "chrp,open-pic";
|
||||
interrupt-controller;
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@
|
|||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -62,7 +63,7 @@
|
|||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
l2-cache-controller@20000 {
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,8540-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>;
|
||||
|
|
@ -82,6 +83,47 @@
|
|||
dfsrr;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8560-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8560-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8560-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8560-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -131,6 +173,7 @@
|
|||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -10,12 +10,14 @@
|
|||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,taishan";
|
||||
compatible = "amcc,taishan";
|
||||
dcr-parent = <&/cpus/cpu@0>;
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC2;
|
||||
|
|
@ -31,13 +33,13 @@
|
|||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,440GX";
|
||||
reg = <0>;
|
||||
clock-frequency = <2FAF0800>; // 800MHz
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <800000000>; // 800MHz
|
||||
timebase-frequency = <0>; // Filled in by zImage
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <8000>; /* 32 kB */
|
||||
d-cache-size = <8000>; /* 32 kB */
|
||||
i-cache-line-size = <50>;
|
||||
d-cache-line-size = <50>;
|
||||
i-cache-size = <32768>; /* 32 kB */
|
||||
d-cache-size = <32768>; /* 32 kB */
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
|
|
@ -45,7 +47,7 @@
|
|||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0 0>; // Filled in by zImage
|
||||
reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -53,7 +55,7 @@
|
|||
compatible = "ibm,uic-440gx", "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <3>;
|
||||
dcr-reg = <200 009>;
|
||||
dcr-reg = <0x200 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
|
|
@ -64,11 +66,11 @@
|
|||
compatible = "ibm,uic-440gx", "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0c0 009>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <01 4 00 4>; /* cascade - first non-critical */
|
||||
interrupts = <0x1 0x4 0x0 0x4>; /* cascade - first non-critical */
|
||||
interrupt-parent = <&UICB0>;
|
||||
|
||||
};
|
||||
|
|
@ -77,11 +79,11 @@
|
|||
compatible = "ibm,uic-440gx", "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0d0 009>;
|
||||
dcr-reg = <0x0d0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <03 4 02 4>; /* cascade */
|
||||
interrupts = <0x3 0x4 0x2 0x4>; /* cascade */
|
||||
interrupt-parent = <&UICB0>;
|
||||
};
|
||||
|
||||
|
|
@ -89,29 +91,29 @@
|
|||
compatible = "ibm,uic-440gx", "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <2>; /* was 1 */
|
||||
dcr-reg = <210 009>;
|
||||
dcr-reg = <0x210 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <05 4 04 4>; /* cascade */
|
||||
interrupts = <0x5 0x4 0x4 0x4>; /* cascade */
|
||||
interrupt-parent = <&UICB0>;
|
||||
};
|
||||
|
||||
|
||||
CPC0: cpc {
|
||||
compatible = "ibm,cpc-440gp";
|
||||
dcr-reg = <0b0 003 0e0 010>;
|
||||
dcr-reg = <0x0b0 0x003 0x0e0 0x010>;
|
||||
// FIXME: anything else?
|
||||
};
|
||||
|
||||
L2C0: l2c {
|
||||
compatible = "ibm,l2-cache-440gx", "ibm,l2-cache";
|
||||
dcr-reg = <20 8 /* Internal SRAM DCR's */
|
||||
30 8>; /* L2 cache DCR's */
|
||||
cache-line-size = <20>; /* 32 bytes */
|
||||
cache-size = <40000>; /* L2, 256K */
|
||||
dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
|
||||
0x030 0x008>; /* L2 cache DCR's */
|
||||
cache-line-size = <32>; /* 32 bytes */
|
||||
cache-size = <262144>; /* L2, 256K */
|
||||
interrupt-parent = <&UIC2>;
|
||||
interrupts = <17 1>;
|
||||
interrupts = <0x17 0x1>;
|
||||
};
|
||||
|
||||
plb {
|
||||
|
|
@ -119,41 +121,41 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <9896800>; // 160MHz
|
||||
clock-frequency = <160000000>; // 160MHz
|
||||
|
||||
SDRAM0: memory-controller {
|
||||
compatible = "ibm,sdram-440gp";
|
||||
dcr-reg = <010 2>;
|
||||
dcr-reg = <0x010 0x002>;
|
||||
// FIXME: anything else?
|
||||
};
|
||||
|
||||
SRAM0: sram {
|
||||
compatible = "ibm,sram-440gp";
|
||||
dcr-reg = <020 8 00a 1>;
|
||||
dcr-reg = <0x020 0x008 0x00a 0x001>;
|
||||
};
|
||||
|
||||
DMA0: dma {
|
||||
// FIXME: ???
|
||||
compatible = "ibm,dma-440gp";
|
||||
dcr-reg = <100 027>;
|
||||
dcr-reg = <0x100 0x027>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-440gx", "ibm,mcmal2";
|
||||
dcr-reg = <180 62>;
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <4>;
|
||||
num-rx-chans = <4>;
|
||||
interrupt-parent = <&MAL0>;
|
||||
interrupts = <0 1 2 3 4>;
|
||||
interrupts = <0x0 0x1 0x2 0x3 0x4>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
|
||||
/*RXEOB*/ 1 &UIC0 b 4
|
||||
/*SERR*/ 2 &UIC1 0 4
|
||||
/*TXDE*/ 3 &UIC1 1 4
|
||||
/*RXDE*/ 4 &UIC1 2 4>;
|
||||
interrupt-map-mask = <ffffffff>;
|
||||
interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
|
||||
/*RXEOB*/ 0x1 &UIC0 0xb 0x4
|
||||
/*SERR*/ 0x2 &UIC1 0x0 0x4
|
||||
/*TXDE*/ 0x3 &UIC1 0x1 0x4
|
||||
/*RXDE*/ 0x4 &UIC1 0x2 0x4>;
|
||||
interrupt-map-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
|
|
@ -162,29 +164,56 @@
|
|||
#size-cells = <1>;
|
||||
/* Wish there was a nicer way of specifying a full 32-bit
|
||||
range */
|
||||
ranges = <00000000 1 00000000 80000000
|
||||
80000000 1 80000000 80000000>;
|
||||
dcr-reg = <090 00b>;
|
||||
ranges = <0x00000000 0x00000001 0x00000000 0x80000000
|
||||
0x80000000 0x00000001 0x80000000 0x80000000>;
|
||||
dcr-reg = <0x090 0x00b>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <7 4>;
|
||||
clock-frequency = <4C4B400>; // 80MHz
|
||||
interrupts = <0x7 0x4>;
|
||||
clock-frequency = <80000000>; // 80MHz
|
||||
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-440gx", "ibm,ebc";
|
||||
dcr-reg = <012 2>;
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <4C4B400>; // 80MHz
|
||||
clock-frequency = <80000000>; // 80MHz
|
||||
|
||||
/* ranges property is supplied by zImage
|
||||
* based on firmware's configuration of the
|
||||
* EBC bridge */
|
||||
|
||||
interrupts = <5 4>;
|
||||
interrupts = <0x5 0x4>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
|
||||
/* TODO: Add other EBC devices */
|
||||
nor_flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
bank-width = <4>;
|
||||
device-width = <2>;
|
||||
reg = <0x0 0x0 0x4000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0x0 0x180000>;
|
||||
};
|
||||
partition@180000 {
|
||||
label = "root";
|
||||
reg = <0x180000 0x200000>;
|
||||
};
|
||||
partition@380000 {
|
||||
label = "user";
|
||||
reg = <0x380000 0x3bc0000>;
|
||||
};
|
||||
partition@3f40000 {
|
||||
label = "env";
|
||||
reg = <0x3f40000 0x80000>;
|
||||
};
|
||||
partition@3fc0000 {
|
||||
label = "u-boot";
|
||||
reg = <0x3fc0000 0x40000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -192,103 +221,103 @@
|
|||
UART0: serial@40000200 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <40000200 8>;
|
||||
virtual-reg = <e0000200>;
|
||||
clock-frequency = <A8C000>;
|
||||
current-speed = <1C200>; /* 115200 */
|
||||
reg = <0x40000200 0x00000008>;
|
||||
virtual-reg = <0xe0000200>;
|
||||
clock-frequency = <11059200>;
|
||||
current-speed = <115200>; /* 115200 */
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0 4>;
|
||||
interrupts = <0x0 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@40000300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <40000300 8>;
|
||||
virtual-reg = <e0000300>;
|
||||
clock-frequency = <A8C000>;
|
||||
current-speed = <1C200>; /* 115200 */
|
||||
reg = <0x40000300 0x00000008>;
|
||||
virtual-reg = <0xe0000300>;
|
||||
clock-frequency = <11059200>;
|
||||
current-speed = <115200>; /* 115200 */
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <1 4>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@40000400 {
|
||||
/* FIXME */
|
||||
compatible = "ibm,iic-440gp", "ibm,iic";
|
||||
reg = <40000400 14>;
|
||||
reg = <0x40000400 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <2 4>;
|
||||
interrupts = <0x2 0x4>;
|
||||
};
|
||||
IIC1: i2c@40000500 {
|
||||
/* FIXME */
|
||||
compatible = "ibm,iic-440gp", "ibm,iic";
|
||||
reg = <40000500 14>;
|
||||
reg = <0x40000500 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <3 4>;
|
||||
interrupts = <0x3 0x4>;
|
||||
};
|
||||
|
||||
GPIO0: gpio@40000700 {
|
||||
/* FIXME */
|
||||
compatible = "ibm,gpio-440gp";
|
||||
reg = <40000700 20>;
|
||||
reg = <0x40000700 0x00000020>;
|
||||
};
|
||||
|
||||
ZMII0: emac-zmii@40000780 {
|
||||
compatible = "ibm,zmii-440gx", "ibm,zmii";
|
||||
reg = <40000780 c>;
|
||||
reg = <0x40000780 0x0000000c>;
|
||||
};
|
||||
|
||||
RGMII0: emac-rgmii@40000790 {
|
||||
compatible = "ibm,rgmii";
|
||||
reg = <40000790 8>;
|
||||
reg = <0x40000790 0x00000008>;
|
||||
};
|
||||
|
||||
TAH0: emac-tah@40000b50 {
|
||||
compatible = "ibm,tah-440gx", "ibm,tah";
|
||||
reg = <40000b50 30>;
|
||||
reg = <0x40000b50 0x00000030>;
|
||||
};
|
||||
|
||||
TAH1: emac-tah@40000d50 {
|
||||
compatible = "ibm,tah-440gx", "ibm,tah";
|
||||
reg = <40000d50 30>;
|
||||
reg = <0x40000d50 0x00000030>;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@40000800 {
|
||||
unused = <1>;
|
||||
unused = <0x1>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-440gx", "ibm,emac4";
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <1c 4 1d 4>;
|
||||
reg = <40000800 70>;
|
||||
interrupts = <0x1c 0x4 0x1d 0x4>;
|
||||
reg = <0x40000800 0x00000074>;
|
||||
local-mac-address = [000000000000]; // Filled in by zImage
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <5dc>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
max-frame-size = <1500>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rmii";
|
||||
phy-map = <00000001>;
|
||||
phy-map = <0x00000001>;
|
||||
zmii-device = <&ZMII0>;
|
||||
zmii-channel = <0>;
|
||||
};
|
||||
EMAC1: ethernet@40000900 {
|
||||
unused = <1>;
|
||||
unused = <0x1>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-440gx", "ibm,emac4";
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <1e 4 1f 4>;
|
||||
reg = <40000900 70>;
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>;
|
||||
reg = <0x40000900 0x00000074>;
|
||||
local-mac-address = [000000000000]; // Filled in by zImage
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <1>;
|
||||
mal-rx-channel = <1>;
|
||||
cell-index = <1>;
|
||||
max-frame-size = <5dc>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
max-frame-size = <1500>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rmii";
|
||||
phy-map = <00000001>;
|
||||
phy-map = <0x00000001>;
|
||||
zmii-device = <&ZMII0>;
|
||||
zmii-channel = <1>;
|
||||
};
|
||||
|
|
@ -297,18 +326,18 @@
|
|||
device_type = "network";
|
||||
compatible = "ibm,emac-440gx", "ibm,emac4";
|
||||
interrupt-parent = <&UIC2>;
|
||||
interrupts = <0 4 1 4>;
|
||||
reg = <40000c00 70>;
|
||||
interrupts = <0x0 0x4 0x1 0x4>;
|
||||
reg = <0x40000c00 0x00000074>;
|
||||
local-mac-address = [000000000000]; // Filled in by zImage
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <2>;
|
||||
mal-rx-channel = <2>;
|
||||
cell-index = <2>;
|
||||
max-frame-size = <2328>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <00000001>;
|
||||
phy-map = <0x00000001>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <0>;
|
||||
zmii-device = <&ZMII0>;
|
||||
|
|
@ -321,18 +350,18 @@
|
|||
device_type = "network";
|
||||
compatible = "ibm,emac-440gx", "ibm,emac4";
|
||||
interrupt-parent = <&UIC2>;
|
||||
interrupts = <2 4 3 4>;
|
||||
reg = <40000e00 70>;
|
||||
interrupts = <0x2 0x4 0x3 0x4>;
|
||||
reg = <0x40000e00 0x00000074>;
|
||||
local-mac-address = [000000000000]; // Filled in by zImage
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <3>;
|
||||
mal-rx-channel = <3>;
|
||||
cell-index = <3>;
|
||||
max-frame-size = <2328>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <00000003>;
|
||||
phy-map = <0x00000003>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <1>;
|
||||
zmii-device = <&ZMII0>;
|
||||
|
|
@ -344,9 +373,9 @@
|
|||
|
||||
GPT0: gpt@40000a00 {
|
||||
/* FIXME */
|
||||
reg = <40000a00 d4>;
|
||||
reg = <0x40000a00 0x000000d4>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <12 4 13 4 14 4 15 4 16 4>;
|
||||
interrupts = <0x12 0x4 0x13 0x4 0x14 0x4 0x15 0x4 0x16 0x4>;
|
||||
};
|
||||
|
||||
};
|
||||
|
|
@ -360,34 +389,34 @@
|
|||
primary;
|
||||
large-inbound-windows;
|
||||
enable-msi-hole;
|
||||
reg = <2 0ec00000 8 /* Config space access */
|
||||
0 0 0 /* no IACK cycles */
|
||||
2 0ed00000 4 /* Special cycles */
|
||||
2 0ec80000 100 /* Internal registers */
|
||||
2 0ec80100 fc>; /* Internal messaging registers */
|
||||
reg = <0x00000002 0x0ec00000 0x00000008 /* Config space access */
|
||||
0x00000000 0x00000000 0x00000000 /* no IACK cycles */
|
||||
0x00000002 0x0ed00000 0x00000004 /* Special cycles */
|
||||
0x00000002 0x0ec80000 0x00000100 /* Internal registers */
|
||||
0x00000002 0x0ec80100 0x000000fc>; /* Internal messaging registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <02000000 0 80000000 00000003 80000000 0 80000000
|
||||
01000000 0 00000000 00000002 08000000 0 00010000>;
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x00000003 0x80000000 0x00000000 0x80000000
|
||||
0x01000000 0x00000000 0x00000000 0x00000002 0x08000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 0 80000000>;
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 1 */
|
||||
0800 0 0 1 &UIC0 17 8
|
||||
0800 0 0 2 &UIC0 18 8
|
||||
0800 0 0 3 &UIC0 19 8
|
||||
0800 0 0 4 &UIC0 1a 8
|
||||
0x800 0x0 0x0 0x1 &UIC0 0x17 0x8
|
||||
0x800 0x0 0x0 0x2 &UIC0 0x18 0x8
|
||||
0x800 0x0 0x0 0x3 &UIC0 0x19 0x8
|
||||
0x800 0x0 0x0 0x4 &UIC0 0x1a 0x8
|
||||
|
||||
/* IDSEL 2 */
|
||||
1000 0 0 1 &UIC0 18 8
|
||||
1000 0 0 2 &UIC0 19 8
|
||||
1000 0 0 3 &UIC0 1a 8
|
||||
1000 0 0 4 &UIC0 17 8
|
||||
0x1000 0x0 0x0 0x1 &UIC0 0x18 0x8
|
||||
0x1000 0x0 0x0 0x2 &UIC0 0x19 0x8
|
||||
0x1000 0x0 0x0 0x3 &UIC0 0x1a 0x8
|
||||
0x1000 0x0 0x0 0x4 &UIC0 0x17 0x8
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -70,6 +70,20 @@
|
|||
fsl,has-wdt;
|
||||
};
|
||||
|
||||
can@900 {
|
||||
compatible = "fsl,mpc5200-mscan";
|
||||
interrupts = <2 17 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
reg = <0x900 0x80>;
|
||||
};
|
||||
|
||||
can@980 {
|
||||
compatible = "fsl,mpc5200-mscan";
|
||||
interrupts = <2 18 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
reg = <0x980 0x80>;
|
||||
};
|
||||
|
||||
gpio@b00 {
|
||||
compatible = "fsl,mpc5200-gpio";
|
||||
reg = <0xb00 0x40>;
|
||||
|
|
|
|||
|
|
@ -12,8 +12,8 @@
|
|||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "tqm,8540";
|
||||
compatible = "tqm,8540", "tqm,85xx";
|
||||
model = "tqc,tqm8540";
|
||||
compatible = "tqc,tqm8540";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
|
|
@ -40,6 +40,7 @@
|
|||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -64,7 +65,7 @@
|
|||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
l2-cache-controller@20000 {
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,8540-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>;
|
||||
|
|
@ -89,6 +90,47 @@
|
|||
};
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8540-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8540-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8540-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8540-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -177,6 +219,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
device_type = "open-pic";
|
||||
compatible = "chrp,open-pic";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -12,8 +12,8 @@
|
|||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "tqm,8541";
|
||||
compatible = "tqm,8541", "tqm,85xx";
|
||||
model = "tqc,tqm8541";
|
||||
compatible = "tqc,tqm8541";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
|
|
@ -39,6 +39,7 @@
|
|||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -63,7 +64,7 @@
|
|||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
l2-cache-controller@20000 {
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,8540-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>;
|
||||
|
|
@ -88,6 +89,47 @@
|
|||
};
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8541-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8541-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8541-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8541-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -158,12 +200,24 @@
|
|||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x7e>;
|
||||
fsl,descriptor-types-mask = <0x01010ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
device_type = "open-pic";
|
||||
compatible = "chrp,open-pic";
|
||||
};
|
||||
|
||||
cpm@919c0 {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,406 @@
|
|||
/*
|
||||
* TQM8548 Device Tree Source
|
||||
*
|
||||
* Copyright 2006 Freescale Semiconductor Inc.
|
||||
* Copyright 2008 Wolfgang Grandegger <wg@denx.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "tqc,tqm8548";
|
||||
compatible = "tqc,tqm8548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8548@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <0x8000>; // L1, 32K
|
||||
i-cache-size = <0x8000>; // L1, 32K
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000>; // Filled in by U-Boot
|
||||
};
|
||||
|
||||
soc8548@a0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0x0 0xa0000000 0x100000>;
|
||||
reg = <0xa0000000 0x1000>; // CCSRBAR
|
||||
bus-frequency = <0>;
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8548-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8548-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x80000>; // L2, 512K
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x24520 0x20>;
|
||||
|
||||
phy1: ethernet-phy@0 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <1>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy2: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <2>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <3>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy4: ethernet-phy@4 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <4>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy5: ethernet-phy@5 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <5>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy2>;
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
|
||||
enet2: ethernet@26000 {
|
||||
cell-index = <2>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x26000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <31 2 32 2 33 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy3>;
|
||||
};
|
||||
|
||||
enet3: ethernet@27000 {
|
||||
cell-index = <3>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x27000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <37 2 38 2 39 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy4>;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>; // reg base, size
|
||||
clock-frequency = <0>; // should we fill in in uboot?
|
||||
current-speed = <115200>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>; // reg base, size
|
||||
clock-frequency = <0>; // should we fill in in uboot?
|
||||
current-speed = <115200>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { // global utilities reg
|
||||
compatible = "fsl,mpc8548-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
};
|
||||
|
||||
localbus@a0005000 {
|
||||
compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
|
||||
"simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xa0005000 0x100>; // BRx, ORx, etc.
|
||||
|
||||
ranges = <
|
||||
0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
|
||||
1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0
|
||||
2 0x0 0xa3000000 0x00008000 // CAN (2 x i82527)
|
||||
3 0x0 0xa3010000 0x00008000 // NAND FLASH
|
||||
|
||||
>;
|
||||
|
||||
flash@1,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <1 0x0 0x8000000>;
|
||||
bank-width = <4>;
|
||||
device-width = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0x00000000 0x00200000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "root";
|
||||
reg = <0x00200000 0x00300000>;
|
||||
};
|
||||
partition@500000 {
|
||||
label = "user";
|
||||
reg = <0x00500000 0x07a00000>;
|
||||
};
|
||||
partition@7f00000 {
|
||||
label = "env1";
|
||||
reg = <0x07f00000 0x00040000>;
|
||||
};
|
||||
partition@7f40000 {
|
||||
label = "env2";
|
||||
reg = <0x07f40000 0x00040000>;
|
||||
};
|
||||
partition@7f80000 {
|
||||
label = "u-boot";
|
||||
reg = <0x07f80000 0x00080000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
/* Note: CAN support needs be enabled in U-Boot */
|
||||
can0@2,0 {
|
||||
compatible = "intel,82527"; // Bosch CC770
|
||||
reg = <2 0x0 0x100>;
|
||||
interrupts = <4 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
can1@2,100 {
|
||||
compatible = "intel,82527"; // Bosch CC770
|
||||
reg = <2 0x100 0x100>;
|
||||
interrupts = <4 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
/* Note: NAND support needs to be enabled in U-Boot */
|
||||
upm@3,0 {
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,upm-nand";
|
||||
reg = <3 0x0 0x800>;
|
||||
fsl,upm-addr-offset = <0x10>;
|
||||
fsl,upm-cmd-offset = <0x08>;
|
||||
chip-delay = <25>; // in micro-seconds
|
||||
|
||||
nand@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "fs";
|
||||
reg = <0x00000000 0x01000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pci@a0008000 {
|
||||
cell-index = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
reg = <0xa0008000 0x1000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 28 */
|
||||
0xe000 0 0 1 &mpic 2 1
|
||||
0xe000 0 0 2 &mpic 3 1>;
|
||||
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <24 2>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
|
||||
0x01000000 0 0x00000000 0xa2000000 0 0x01000000>;
|
||||
};
|
||||
|
||||
pci1: pcie@a000a000 {
|
||||
cell-index = <2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 (PEX) */
|
||||
0x00000 0 0 1 &mpic 0 1
|
||||
0x00000 0 0 2 &mpic 1 1
|
||||
0x00000 0 0 3 &mpic 2 1
|
||||
0x00000 0 0 4 &mpic 3 1>;
|
||||
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <26 2>;
|
||||
bus-range = <0 0xff>;
|
||||
ranges = <0x02000000 0 0xb0000000 0xb0000000 0 0x10000000
|
||||
0x01000000 0 0x00000000 0xaf000000 0 0x08000000>;
|
||||
clock-frequency = <33333333>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xa000a000 0x1000>;
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0 0xb0000000 0x02000000 0
|
||||
0xb0000000 0 0x10000000
|
||||
0x01000000 0 0x00000000 0x01000000 0
|
||||
0x00000000 0 0x08000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,411 @@
|
|||
/*
|
||||
* TQM8548 Device Tree Source
|
||||
*
|
||||
* Copyright 2006 Freescale Semiconductor Inc.
|
||||
* Copyright 2008 Wolfgang Grandegger <wg@denx.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "tqc,tqm8548";
|
||||
compatible = "tqc,tqm8548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8548@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <0x8000>; // L1, 32K
|
||||
i-cache-size = <0x8000>; // L1, 32K
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000>; // Filled in by U-Boot
|
||||
};
|
||||
|
||||
soc8548@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0x0 0xe0000000 0x100000>;
|
||||
reg = <0xe0000000 0x1000>; // CCSRBAR
|
||||
bus-frequency = <0>;
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8548-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8548-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x80000>; // L2, 512K
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1337";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x24520 0x20>;
|
||||
|
||||
phy1: ethernet-phy@0 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <1>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy2: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <2>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <3>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy4: ethernet-phy@4 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <4>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy5: ethernet-phy@5 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <5>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy2>;
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
|
||||
enet2: ethernet@26000 {
|
||||
cell-index = <2>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x26000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <31 2 32 2 33 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy3>;
|
||||
};
|
||||
|
||||
enet3: ethernet@27000 {
|
||||
cell-index = <3>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x27000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <37 2 38 2 39 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy4>;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>; // reg base, size
|
||||
clock-frequency = <0>; // should we fill in in uboot?
|
||||
current-speed = <115200>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>; // reg base, size
|
||||
clock-frequency = <0>; // should we fill in in uboot?
|
||||
current-speed = <115200>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { // global utilities reg
|
||||
compatible = "fsl,mpc8548-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
};
|
||||
|
||||
localbus@e0005000 {
|
||||
compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
|
||||
"simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xe0005000 0x100>; // BRx, ORx, etc.
|
||||
|
||||
ranges = <
|
||||
0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
|
||||
1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0
|
||||
2 0x0 0xe3000000 0x00008000 // CAN (2 x i82527)
|
||||
3 0x0 0xe3010000 0x00008000 // NAND FLASH
|
||||
|
||||
>;
|
||||
|
||||
flash@1,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <1 0x0 0x8000000>;
|
||||
bank-width = <4>;
|
||||
device-width = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0x00000000 0x00200000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "root";
|
||||
reg = <0x00200000 0x00300000>;
|
||||
};
|
||||
partition@500000 {
|
||||
label = "user";
|
||||
reg = <0x00500000 0x07a00000>;
|
||||
};
|
||||
partition@7f00000 {
|
||||
label = "env1";
|
||||
reg = <0x07f00000 0x00040000>;
|
||||
};
|
||||
partition@7f40000 {
|
||||
label = "env2";
|
||||
reg = <0x07f40000 0x00040000>;
|
||||
};
|
||||
partition@7f80000 {
|
||||
label = "u-boot";
|
||||
reg = <0x07f80000 0x00080000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
/* Note: CAN support needs be enabled in U-Boot */
|
||||
can0@2,0 {
|
||||
compatible = "intel,82527"; // Bosch CC770
|
||||
reg = <2 0x0 0x100>;
|
||||
interrupts = <4 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
can1@2,100 {
|
||||
compatible = "intel,82527"; // Bosch CC770
|
||||
reg = <2 0x100 0x100>;
|
||||
interrupts = <4 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
/* Note: NAND support needs to be enabled in U-Boot */
|
||||
upm@3,0 {
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,upm-nand";
|
||||
reg = <3 0x0 0x800>;
|
||||
fsl,upm-addr-offset = <0x10>;
|
||||
fsl,upm-cmd-offset = <0x08>;
|
||||
chip-delay = <25>; // in micro-seconds
|
||||
|
||||
nand@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "fs";
|
||||
reg = <0x00000000 0x01000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pci@e0008000 {
|
||||
cell-index = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
reg = <0xe0008000 0x1000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 28 */
|
||||
0xe000 0 0 1 &mpic 2 1
|
||||
0xe000 0 0 2 &mpic 3 1>;
|
||||
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <24 2>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
|
||||
0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
|
||||
};
|
||||
|
||||
pci1: pcie@e000a000 {
|
||||
cell-index = <2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 (PEX) */
|
||||
0x00000 0 0 1 &mpic 0 1
|
||||
0x00000 0 0 2 &mpic 1 1
|
||||
0x00000 0 0 3 &mpic 2 1
|
||||
0x00000 0 0 4 &mpic 3 1>;
|
||||
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <26 2>;
|
||||
bus-range = <0 0xff>;
|
||||
ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x20000000
|
||||
0x01000000 0 0x00000000 0xef000000 0 0x08000000>;
|
||||
clock-frequency = <33333333>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xe000a000 0x1000>;
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0 0xc0000000 0x02000000 0
|
||||
0xc0000000 0 0x20000000
|
||||
0x01000000 0 0x00000000 0x01000000 0
|
||||
0x00000000 0 0x08000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
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