clk: samsung: exynos5433: Add clocks for CMU_G3D domain
This patch adds the mux/divider/gate clocks for CMU_G3D domain which contains the clocks for GPU(3D Graphics Engine). Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Chanwoo Choi
Sylwester Nawrocki
Родитель
4b8013554b
Коммит
453e519e5a
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@ -3120,3 +3120,130 @@ CLK_OF_DECLARE(exynos5433_cmu_bus##id, \
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exynos5433_cmu_bus_init(0);
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exynos5433_cmu_bus_init(1);
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exynos5433_cmu_bus_init(2);
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/*
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* Register offset definitions for CMU_G3D
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*/
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#define G3D_PLL_LOCK 0x0000
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#define G3D_PLL_CON0 0x0100
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#define G3D_PLL_CON1 0x0104
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#define G3D_PLL_FREQ_DET 0x010c
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#define MUX_SEL_G3D 0x0200
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#define MUX_ENABLE_G3D 0x0300
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#define MUX_STAT_G3D 0x0400
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#define DIV_G3D 0x0600
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#define DIV_G3D_PLL_FREQ_DET 0x0604
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#define DIV_STAT_G3D 0x0700
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#define DIV_STAT_G3D_PLL_FREQ_DET 0x0704
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#define ENABLE_ACLK_G3D 0x0800
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#define ENABLE_PCLK_G3D 0x0900
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#define ENABLE_SCLK_G3D 0x0a00
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#define ENABLE_IP_G3D0 0x0b00
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#define ENABLE_IP_G3D1 0x0b04
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#define CLKOUT_CMU_G3D 0x0c00
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#define CLKOUT_CMU_G3D_DIV_STAT 0x0c04
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#define CLK_STOPCTRL 0x1000
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static unsigned long g3d_clk_regs[] __initdata = {
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G3D_PLL_LOCK,
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G3D_PLL_CON0,
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G3D_PLL_CON1,
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G3D_PLL_FREQ_DET,
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MUX_SEL_G3D,
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MUX_ENABLE_G3D,
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MUX_STAT_G3D,
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DIV_G3D,
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DIV_G3D_PLL_FREQ_DET,
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DIV_STAT_G3D,
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DIV_STAT_G3D_PLL_FREQ_DET,
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ENABLE_ACLK_G3D,
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ENABLE_PCLK_G3D,
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ENABLE_SCLK_G3D,
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ENABLE_IP_G3D0,
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ENABLE_IP_G3D1,
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CLKOUT_CMU_G3D,
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CLKOUT_CMU_G3D_DIV_STAT,
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CLK_STOPCTRL,
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};
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/* list of all parent clock list */
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PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", };
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PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", };
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static struct samsung_pll_clock g3d_pll_clks[] __initdata = {
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PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
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G3D_PLL_LOCK, G3D_PLL_CON0, exynos5443_pll_rates),
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};
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static struct samsung_mux_clock g3d_mux_clks[] __initdata = {
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/* MUX_SEL_G3D */
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MUX(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p,
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MUX_SEL_G3D, 8, 1),
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MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
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MUX_SEL_G3D, 0, 1),
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};
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static struct samsung_div_clock g3d_div_clks[] __initdata = {
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/* DIV_G3D */
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DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D,
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8, 2),
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DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D,
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4, 3),
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DIV(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D,
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0, 3),
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};
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static struct samsung_gate_clock g3d_gate_clks[] __initdata = {
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/* ENABLE_ACLK_G3D */
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GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d",
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ENABLE_ACLK_G3D, 7, 0, 0),
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GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d",
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ENABLE_ACLK_G3D, 6, 0, 0),
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GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d",
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ENABLE_ACLK_G3D, 5, 0, 0),
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GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d",
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ENABLE_ACLK_G3D, 4, 0, 0),
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GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d",
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ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d",
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ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d",
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ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d",
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ENABLE_ACLK_G3D, 0, 0, 0),
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/* ENABLE_PCLK_G3D */
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GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d",
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ENABLE_PCLK_G3D, 3, 0, 0),
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GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d",
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ENABLE_PCLK_G3D, 2, 0, 0),
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GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d",
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ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d",
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ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0),
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/* ENABLE_SCLK_G3D */
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GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d",
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ENABLE_SCLK_G3D, 0, 0, 0),
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};
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static struct samsung_cmu_info g3d_cmu_info __initdata = {
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.pll_clks = g3d_pll_clks,
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.nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
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.mux_clks = g3d_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
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.div_clks = g3d_div_clks,
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.nr_div_clks = ARRAY_SIZE(g3d_div_clks),
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.gate_clks = g3d_gate_clks,
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.nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
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.nr_clk_ids = G3D_NR_CLK,
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.clk_regs = g3d_clk_regs,
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.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
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};
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static void __init exynos5433_cmu_g3d_init(struct device_node *np)
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{
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samsung_cmu_register_one(np, &g3d_cmu_info);
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}
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CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d",
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exynos5433_cmu_g3d_init);
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@ -794,4 +794,29 @@
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#define BUSx_NR_CLK 11
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/* CMU_G3D */
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#define CLK_FOUT_G3D_PLL 1
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#define CLK_MOUT_ACLK_G3D_400 2
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#define CLK_MOUT_G3D_PLL 3
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#define CLK_DIV_SCLK_HPM_G3D 4
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#define CLK_DIV_PCLK_G3D 5
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#define CLK_DIV_ACLK_G3D 6
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#define CLK_ACLK_BTS_G3D1 7
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#define CLK_ACLK_BTS_G3D0 8
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#define CLK_ACLK_ASYNCAPBS_G3D 9
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#define CLK_ACLK_ASYNCAPBM_G3D 10
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#define CLK_ACLK_AHB2APB_G3DP 11
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#define CLK_ACLK_G3DNP_150 12
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#define CLK_ACLK_G3DND_600 13
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#define CLK_ACLK_G3D 14
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#define CLK_PCLK_BTS_G3D1 15
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#define CLK_PCLK_BTS_G3D0 16
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#define CLK_PCLK_PMU_G3D 17
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#define CLK_PCLK_SYSREG_G3D 18
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#define CLK_SCLK_HPM_G3D 19
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#define G3D_NR_CLK 20
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
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